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rors. Unconstrained arrays are LISTING 12—TWO COUNTER INSTANCES INSTANTIATED using unconstrained arrays to
particularly suitable for ad- IN A TOP-LEVEL ENTITY support efficient reuse.
dress, data, and register
widths. You can use these ar- TIP 6: VHDL ATTRIBUTES
rays for formal parameters in A few attributes of compos-
functions and procedures as ite types are useful in creating
well as for entity ports. reusable designs. The attrib-
VHDL allows the use of un- utes “left,” “right,” “range,”
constrained-array types that “length,” “low,” and “high” are
let you indicate the type of in- synthesizable and make the
dex values without specifying code independent of data type.
the index bounds. Uncon- Refer to the examples using
strained arrays are useful for unconstrained arrays (listings
making designs that you can 8 and 9), where the function
reuse in different applications Gray2bin and the entity
just by modifying their bit counter use the “range” attrib-
widths. The previous counter ute to promote reusability.
example uses unconstrained
arrays for the count output TIP 7: CONFIGURATION SPECS
(Listing 8). This technique You use configuration spec-
lets you connect the counter ifications to bind component
entity to array signals of any instances to design entities.
size or with any range of index You can also use these config-
values. Note the use of the urations to pass parameters
VHDL attribute “range” to such as generics at the top-
LISTING 13—COUNTER CONFIGURATION IN A TOP-LEVEL ENTITY
create a signal of the same most level in a testbench, to se-
width and range specification lect an architecture for an en-
as the port count. You cannot tity, or to override port
synthesize this design by itself, mappings in an instantiation.
and you have to instantiate it Some synthesis tools do not
in a top-level entity to bind support configuration specifi-
the array values to a finite cations.
range (Listing 9). You must Consider the previous
synthesize the code in Listing counter example that illus-
9 in a top-down manner so trates the use of generics for
that you can synthesize the parameterization. Listing 11
counter along with the rest of illustrates the same counter
the design. with another architecture that
Another use of uncon- buffers the counter outputs
strained arrays occurs in functions and makes efficient reuse possible. Listing 10 with a generate statement. The counter is
procedures. You should write functions is a bit-width-independent implementa- now instantiated in a top-level design us-
and procedures that you design for syn- tion for the binary-code-to-gray-code ing two instances of the counter (Listing
thesis as generically as possible, inde- converter. As another example, consider 12). A configuration specification con-
pendently of bit widths. Consider an ex- the functions and procedures in the IEEE figures the counter in the entity top, as
ample of a binary-code-to-gray-code std_logic libraries. Most of these func- shown in Listing 13. Configuration spec-
converter. To create a gray code from a bi- tions and procedures are implemented ifications let you configure various lev-
nary code, use the algorithm in Figure els of the design’s hierarchy.
5a. Figure 5b is an example of how to TABLE 1—GRAY CODES CORRESPONDING
convert binary 100 to its gray-code TO 3-BIT BINARY CODES TIP 8: BLOCK STATEMENTS
equivalent of 110. Table 1 shows the gray Binary Gray Block statements are VHDL constructs
codes for the 3-bit binary values that the 000 000 that allow inline design partitioning. For
algorithm of Figure 5a creates. You hard- 001 001 example, if you partition a design such
code and optimize this algorithm for a 3- 010 011 that the datapath exists in a separate
bit case. When the design has to accom- 011 010 VHDL entity, then you can partition the
modate more counts, the function has to 100 110 architecture for that entity using block
change, requiring you to revalidate all the 101 111 statements. Block statements are a
logic. Writing a generic function that is 110 101 method of grouping related logic. Block
independent of the bit-vector lengths 111 100 statements also provide the ability to de-
clare signals within the blocks and, if you modify code for a specific application, Technological University (Cookeville, TN).
remove the block, unnecessary signals do through the use of preprocessor direc- His interests include computer architec-
not remain unconnected in the code. You tives.□ ture, design automation, volleyball, and
can combine a generate statement with travel.
the block statement to selectively include References
or exclude blocks. 1. Meiyappan, Subbu, and Peter Ken Jaramillo is a staff engineer at VLSI
Chambers, “Design Reuse Using Script- Technology. In his three years with the
TIP 9: UNUSED PORTS ing Methodologies,” DesignCon98, On- company, he has worked on high-speed
In a hierarchical design, if you do not Chip System Design Conference, pg 629. networking designs, such as fiber-distrib-
use certain ports in an entity, then the 2. Ashenden, PJ, The Designer’s Guide uted data interfaces, Firewire, and high-
usual practice is to connect them to a to VHDL, Morgan Kaufman Publishers, speed satellite modems. He has a BSEE
dummy signal. From a top-down syn- San Francisco, CA, 1996. from the University of Missouri (Kansas
thesis approach, this scenario makes the 3. Smith, Douglas J, HDL Chip Design, City, MO) and a BSCoE from the Univer-
synthesizer assume that you’ve connect- Doone Publications, Madison, AL, 1996, sity of Missouri (Columbia, MO). His hob-
ed the signal to a net. You can avoid this ISBN 0-9651934-3-8. bies include basketball, rock climbing, and
problem by leaving the port unconnect- travel.
ed or by specifying with the VHDL key- Authors’ bio graphies
word “open.” Subbu Meiyappan is a senior design engi- Peter Chambers is an engineering fellow at
neer at VLSI Technology. He has worked VLSI Technology, where he has worked for
TIP 10: PREPROCESSORS for the company for nearly three years, de- six years developing many PCI-based de-
In many situations, designers cannot signing, developing, synthesizing,simulat- signs, ASICs, chip sets, and reusable IP
accomplish what they want using the ing, and validating high-performance IP cores. He has a BS from the University of
available features. In some cases, it is de- blocks for PCI, ARM-ASB-based devices, Exeter (UK) and an MS from Arizona
sirable to see only the code that is rele- and high-performance ASICs. He has a BE State University (Tempe, AZ). He is a
vant to the design. In such cases, you can from Annamalai University (Annamalai member of both IEE and IEEE.
use a preprocessor to add, eliminate, or Nagar, India) and an MS from Tennessee