Integrated Digital Systems

Introduction to
Fabrication Technologies

Professor Yusuf Leblebici

Microelectronic Systems Laboratory (LSM)

yusuf.leblebici@epfl.ch

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 Organization

§ Materials Used in VLSI Fabrication

§ VLSI Fabrication Technologies
§ Overview of Fabrication Methods
§ CMOS Process Stages
§ Issues in Deep-Submicron Process

2 EE569 Advanced VLSI Dsign Techniques

 Main Categories of Materials

Materials can be categorized into three main

groups regarding their electrical conduction
properties:
§ Insulators
§ Conductors
§ Semiconductors

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 Conductors

Conductors are used in IC design for electrical

connectivity. The following are good conducting
elements:

§ Silver
§ Gold
§ Copper
§ Aluminum
§ Platinum
§ Bismuth
§ Tungsten

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 Insulators

Insulators are used to isolate conducting and/or

semi-conducting materials from each other.

MOS devices and Capacitors rely on an insulator

for their physical operation.

The choice of the insulators (and the conductors)

in IC design depends heavily on how the materials
interact with each other, especially with the
semiconductors.

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 Semiconductors
While there are numerous
semiconductor materials
available, by far the most
popular material is Silicon.

GaAs, InP and SiGe are

compound semiconductors
that are used in specialized
devices.

The success of a semiconductor material depends on how easy it is to

process and how well it allows reliable high-volume fabrication.

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 Organization

§ Materials Used in VLSI Fabrication

§ VLSI Fabrication Technologies
§ Overview of Fabrication Methods
§ CMOS Process Stages
§ Issues in Deep-Submicron Process

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 Overview of Processing Technologies

Although a number of processing technologies are

available, few are actively used. The majority of the
production is done with traditional CMOS, other
processes are limited to areas where CMOS is not
very suitable (like high speed RF applications):

§ CMOS (90%)
§ BiCMOS (5%) Typical breakdown of the
§ Bipolar (2%) worldwide semiconductor
§ GaAs (2%) fabrication
§ SOI (1%)

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 Simplified View of MOSFET

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 CMOS Process
The CMOS process allows fabrication of nMOS
and pMOS transistors side-by-side on the same
Silicon substrate.

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 BiCMOS Technology
Bipolar transistors have superior current driving characteristics
compared to MOS transistors. The Bipolar-CMOS (BiCMOS)
process has additional layers for the inclusion of bipolar transistors
alongside regular CMOS structures.

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 Silicon on Insulator (SOI)
The key innovation
in SOI is to build the
transistor structures
on an insulating
material rather than
a common substrate
as in CMOS. This
reduces parasitic
capacitances and
eliminates substrate
noise coupling.

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 Organization

§ Materials Used in VLSI Fabrication

§ VLSI Fabrication Technologies
§ Overview of Fabrication Methods
§ CMOS Process Stages
§ Issues in Deep-Submicron Process

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 Single Crystal Growth
Pure silicon is melted in a
pot (1400C) and a small
seed containing the
desired crystal orientation
is inserted into molten
silicon and slowly
(1mm/minute) pulled out.

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 Single Crystal Growth

The silicon crystal (in some

cases also containing
doping) is manufactured
(pulled) as a cylinder with
a diameter of 8-12 inches.

This cylinder is carefully

sawed into thin disks
(wafers). The wafers are
later polished and marked
for crystal orientation.

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 Lithography

An IC consists of
several layers of
material that are
manufactured in
successive steps.

Lithography is used
to selectively process
the layers, where the
2-D mask geometry is
copied on the surface.

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 Lithography
The surface of the wafer is coated
with a photosensitive material, the
photoresist. The mask pattern is
developed on the photoresist, with
UV light exposure.

Depending on the type of the

photoresist (negative or positive),
the exposed or unexposed parts
of the photoresist change their
property and become resistant
to certain types of solvents.

Subsequent processing steps remove the undeveloped photoresist from

the wafer. The developed pattern (usually) protects the underlying layer
from an etching process. The photoresist is removed after patterning on
the lower layer is completed.
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 Lithography

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 Lithography

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 Etching
Etching is a common process to
pattern material on the surface.
Once the desired shape is
patterned with photoresist, the
unprotected areas are etched
away, using wet or dry etch
techniques.

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 Oxide Growth / Oxide Deposition
Oxidation of the silicon
surface creates a SiO2
layer that acts as an
insulator. Oxide layers
are also used to isolate
metal interconnections.

An annealing step is required to restore the

crystal structure after thermal oxidation.

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 Ion Implantation

Ion implantation is
used to add doping
materials to change
the electrical
characteristics of
silicon locally. The
dopant ions penetrate
the surface, with a
penetration depth that
is proportional to their
kinetic energy.

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 Thin Film Deposition
While some of the structures can be
grown on silicon substrate, most of
the other materials (especially metal
and oxide) need to be deposited on
the surface.

In most cases, the material that is

deposited on the whole surface will
be patterned and selectively etched.

There are two main methods for thin

film deposition:

§ PVD Physical Vapor Deposition

§ CVD Chemical Vapor Deposition

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 Organization

§ Materials Used in VLSI Fabrication

§ VLSI Fabrication Technologies
§ Overview of Fabrication Methods
§ CMOS Process Stages
§ Issues in Deep-Submicron Process

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 Well Creation

The first step of

processing is to
create a deeply
implanted n-well.

This is done either

by diffusion or ion
implantation.

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 Definition of Active Areas
The next step is to
define the active
areas where the
transistors will later
be created.

A thermal oxide is
grown uniformly on
the surface. Then
the active areas are
covered by nitride.
A second thermal
oxidation process
grows thick silicon
dioxide outside the
active areas.
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 Polysilicon Deposition

The entire surface

is covered with a
thin oxide layer
(gate oxide).

Polysilicon is deposited and

patterned to form the gates of the
nMOS and pMOS transistors.

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 Source/Drain Implantation

The drain and source

regions of the nMOS
and pMOS transistors
are created by doping.

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 Oxide Deposition
The whole surface is
covered with a field
oxide and the contact
holes are etched into
this oxide to enable
connection to the
underlying layers.

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 1st Level Metallization
The metal layer is
deposited using a
Physical Vapor
Deposition (PVD)
method, patterned,
and etched.

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 2nd Level Metallization
The whole surface is
covered with a field
oxide and the contact
holes are etched into
this oxide to enable
connection to the
underlying layers.

Then, the second

(third, fourth, etc…)
layer of metal can be
deposited, patterned
and etched according
to the mask layout.

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 Alternative CMOS Process Sequence

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 Alternative CMOS Process Sequence

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 Alternative CMOS Process Sequence

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 Alternative CMOS Process Sequence

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 What Do These Transistors Look Like ?

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 What Do These Transistors Look Like ?

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 Multi-Level Metal Interconnect

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 Multi-Level Metal Interconnect

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 Multi-Level Metal Interconnect

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 Organization

§ Materials Used in VLSI Fabrication

§ VLSI Fabrication Technologies
§ Overview of Fabrication Methods
§ CMOS Process Stages
§ Issues in Deep-Submicron Process

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 Lithography Resolution is Decreasing

2002: 130 nm

2003: 90 nm
…

2010: 35 nm (?)

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 Lithography Resolution is Decreasing

“design shrink”

180 nm 130 nm 90 nm

With each new technology generation, we would be able to fit the

same amount of functionality into a smaller silicon area (ideally).

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 Lithography Resolution is Decreasing
1989

1982
1979

1971

10 µm technology 3 µm technology 1.5 µm technology 0.8 µm technology

12 sqmm 33 sqmm 50 sqmm 81 sqmm

But at the same time, we try to put more functionality in each chip
for each new technology generation, so that the average chip size
actually increases over the years !

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 logic
empty
shrinks
well area !

memory
does not
shrink

180 nm 130 nm

• Not all components can shrink at the same rate.

• Memory arrays do not scale very well !
• Potential limit to area utilization in new technology.

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 Fabrication is EXPENSIVE !

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 Alignment of Masks

IC production requires as many

as 20 masks per design. In order
to ensure proper connectivity all
of these masks must align
exactly.

The tolerance in alignment is an

essential parameter for defining
the limits of the technology.

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 Process Variations

Although a large number

of IC’s are manufactured
on the same wafer, there
can be large variations of
critical parameters across
the surface.

Example shows variation

of oxide thickness for two
different samples.

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 Step Coverage
Covering and filling
inter-layer connections
is one of the most
important problems.
“Reflow” technique is
used to smooth the
edges.

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 Crystal Faults
Crystal faults are faults in
the crystal structure of the
semiconductor. They can
change the electrical and
mechanical properties of
the material.

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 Stacking Faults
Stacking faults appear because many
layers are deposited on top of each
other. The vertical displacement
causes a number of problems for
alignment and coverage

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 Yield
Yield defines the number of working IC’s as a percentage
of total manufactured ICs. Typically, the yield drops with
increasing chip dimensions.

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 References
Books
§ S.M. Sze, “Semiconductor Devices, Physics and Technology”, John
Wiley & Sons, 1985
§ F. Shimura, “Semiconductor Silicon Crystal Technology”, Academic
Press, 1989
§ D. Elliot, “Microlithorgraphy, Process Technology for IC Fabrication”,
McGraw Hill, 1986
§ W. Maly, “Atlas of IC Technologies”, Benjamin Cummings, 1987
§ A. Christou, “Electromigration & Electronic Device Degradation”, John
Wiley & Sons, 1994
§ S.M. Kang, Y. Leblebici, “CMOS Digital Integrated Circuits, Analysis
and Design”, McGraw Hill, 1999

WWW sites
§ http://pcvlsi5.cern.ch/MicDig/VLSI_Trieste/Technology
§ http://www.fullman.com/semiconductors/index.html
§ http://www.chips.ibm.com

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