The VHDL Handbook

The VHDL Handbook

by

David R. Coelho
Vantage Analysis Systems, Inc.

~.

"
Kluwer Academic Publishers
KALA llRPORATION
Distributors for North America:
Kluwer Academic Publishers
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Assinippi Park
Norwell, MA 02061, USA

Distributors for all other countries:

Kluwer Academic Publishers Group
Distribution Centre
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3300 AH Dordrecht, THE NETHERLANDS

Consulting Editor: Jonathan Allen, Massachusetts Institute of Technology

Library of Congress Cataloging~ln·Publicatlon Data

Coelho, David R.
The VHDL handbook.

Bibliography: p.
Includes index.
1. VHDL (Computer program language) I. Title.
TK7874.C6 1989 621.39 '2 89-11084
ISBN-13: 978-1-4612-8902-9 e-ISBN-13: 978-1-4613-1633-6
DOl: 10.1007/978-1-4613-1633-6

This reprint edition has been published by KALA CORPORATION

under copyright arrangements with KLUWER ACADEMIC PUBLISHERS.

Copyright © 19X9 by Kluwer Academic Publishers. Third Printing, 1990.

Softcover reprint of the hardcover 1st edition 1989
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system
or transmitted in any form or by any means, mechanical, photocopying, recording, or other-
wise, without the prior written permission of the publisher, Kluwer Academic Publishers, 101
Philip Drive, Assinippi Park, Norwell, Massachusetts 02061.
Contents

1 Introduction 1
1.1 Introduction to the VHDL Language 1
1.1.1 History of VHDL . . . . . . . 1
1.1.2 DOD Requirements and VHDL 2
1.1.3 VHDL As a Design Tool. 3
1.2 Multi-Level Design . . . . . . . . 5
1.3 The Model Accuracy Continuum 7

2 Anatomy of a VHDL Model 11

2.1 Describing Electronic Hardware in VHDL 11
2.2 A VHDL File . . . . . . . . . 14
2.3 The Standard Logic Package ....... 20
2.4 User Defined Packages . . . . . . . . . . . 21
2.5 VHDL Models and the Accuracy Continuum 25
2.5.1 2-Value Unit-Delay Approach . 25
2.5.2 46-Value Unit-Delay Approach 28
2.5.3 Fixed-Delay Approach . . . . . 30
2.5.4 Variable-Delay Approach ... 31
2.5.5 Generic Variable-Delay Approach. 33
2.5.6 Full-Delay Approach . . . . . . . . 36
2.5.7 Error Checking and Model Structure . 38
2.6 Handling Timing Using Configurations . . . . 42
2.7 Using VHDL as a Stimulus Language . . . . 46
2.8 Standardized VHDL Modelling Conventions 48
2.8.1 Generic Parameters 50
2.8.2 Naming Conventions 53
2.8.3 Constraints ..... 54
2.8.4 Unknown Handling. 54
3 Combinational Devices 57
3.1 Simple Gates . . . . . . . . . . . . . . . . . . . . . . . . .. 57
3.1.1 2-Ioput Positive-Nand Gate. . . . . . . . . . . . .. 57
3.1.2 2-Input Positive-Nand with Open-Collector Outputs 60
3.1.3 2-Input Positive-Nor Gate . . . . . . . 62
3.1.4 Inverter................. 64
3.1.5 Inverter with Open-Collector Outputs 66
3.1.6 3-Input Positive-And Gate. 68
3.1.7 3-Input Positive-Nand Gate 71
3.1.8 2-Input Positive-Or Gate 73
3.1.9 2-Input Positive-Xor Gate . 76
3.2 Selectors/Multiplexers . . . . . . . 78
3.2.1 3 to 8 Decoder/Multiplexer 79
3.2.2 2 to 4 Decoder/Multiplexer 84
3.2.3 1 of 8 Selector/Multiplexer 87
3.2.4 1 of 4 Selector/Multiplexer 92
3.2.5 1 of 2 Selector/Multiplexer 96
3.3 Switch Level Devices . . . . . . . . 99
3.3.1 Switch Modelling Utilities . 100
3.3.2 Bidirectional Transmission Element 104
3.3.3 Basic Complementary Transmission Gate 107
3.3.4 Basic Transmission Gate. 107
3.4 Simple ALU's . . . . . . . . . . . 108
3.4.1 ALU/Function Generator 109
3.5 One Shots . . . . . . . . . . . . . 119
3.5.1 Mooostable Multivibrator 119
3.6 Comparators . . . . . . . . . . . 123
3.6.1 4 Bit Magnitude Comparator 124
3.7 Parity Generators/Checkers . . . . . 129
3.7.1 9 bit Odd/Even Parity Generator/Checker 129

4 Sequential Devices 135

4.1 Flip-Flops............................ 135
4.1.1 D-Type Positive-Edge Triggered Flip-Flop with Pre-
set/Clear ... . . . . . . . . . . . . . . . . . . . .. 136
4.1.2 JK Pos-Edge Triggered Flip-Flop with Preset/Clear 140
4.1.3 JK Neg-Edge Triggered Flip-Flop with Preset/Clear 146
4.1.4 JK Negative-Edge Triggered Flip-Flop with Preset 152
4.2 Registers......................... 157
4.2.1 4-Bit Parallel-Access Shift Register. . . . . . 158
4.2.2 3 to 8 Decoder/Demultiplexer with Register. 165
4.2.3 3 to 8 Decoder/Demultiplexer with Latch . . 171
 4.2.4 8 Bit Parallel-Out Serial Shift Register. . . . 177
4.2.5 Parallel Load 8 Bit Shift Register. . . . . . . 182
4.2.6 Parallel Load 8 Bit Shift Register with Clear 188
4.3 Counters......................... 195
4.3.1 Synchronous 4 Bit Decade Counter with Asynchronous
Clear . . . . . . . . . . . . . . . . . . . . . . . . . . 196
4.3.2 Synchronous 4 Bit Binary Counter with Asynchronous
Clear . . . . . . . . . . . . . . . . . . . 202
4.3.3 Synchronous 4 Bit Decade Counter . . . . . . . . 208
4.3.4 Synchronous 4 Bit Binary Counter . . . . . . . 214
4.3.5 Synchronous Up/Down 4-Bit Decade Counter. 220

5 Memory Devices 227

5.1 Memory Initialization . . . . . . 227
5.2 Read Only Memories . . . . . . . 231
5.2.1 1024 bit (256 by 4) ROM 231
5.2.2 16,384 bit (4096 by 4) register PROM 236
5.3 Random Access Memories 242
5.3.1 64 bit RAM . . . . . . 243
5.4 PALs, PLDs . . . . . . . . . . 251
5.4.1 Calculating Products. 252
5.4.2 10 input, 2 output, 6 I/O PAL . 255
5.4.3 8 input, 2 I/O, 6 clocked output PAL 259
5.4.4 8 input, 8 clocked output PAL 264

6 Complex Devices 269

6.1 Getting Started. . . . . . . . . . . . . . . . . . 269
6.1.1 Partial versus Full Functional Models . 270
6.1.2 Architecture 271
6.1.3 Behavior.... 278
6.2 The Timing Model. . 288
6.2.1 Device Speeds. 288
6.2.2 Min/Max Timing. . 290
6.2.3 Drive/Loading Dependencies .. 290
6.2.4 A Uniform Approach to Device Dependent Data .. 291
6.3 Error Handling . . . . . . . . . . . . . 293
6.3.1 Unknowns............. 293
6.3.2 Setup / Hold Time Techniques 295
6.3.3 Waveform Checking 296
6.4 Techniques for Modeling . . . . 299
6.4.1 Bus Handlers . . . . . 299
6.4.2 Instruction Decoders . . 300
 6.4.3 Sequencers . . . 301
6.4.4 Instruction Sets. 301
6.5 Quality Assurance . . . 301
6.5.1 Developing a Test Plan 302
6.5.2 Validation of the Model 304

7 The Standard Logic Package 309

7.1 Using the Standard Logic Package 310
7.2 The Logic Value System . . . . . . 311
7.3 Technology Rules . . . . . . . . . . 315
7.3.1 ECL - Emitter Coupled Logic. 322
7.3.2 CMOS - Complementary MOS 324
7.3.3 NMOS - n-Channel MOS . . . 326
7.3.4 TTL - Transistor transistor logic 328
7.3.5 TTLOC - Open-collector TTL 330
7.4 Bus Resolution . . . . . . . . . . . . . . 332
7.5 Logic Manipulation . . . . . . . . . . . . 337
7.5.1 Overloaded Comparison Operators 337
7.5.2 State/Strength Lookup Tables 339
7.5.3 Logic Lookup Tables. 352
7.6 Timing Utilities . . . . 357
7.7 Integer Data Utilities. 364

Bibliography 377

Index 381
List of Figures

1.1 DOD/VHDL Documentation Requirements 3

1.2 Accuracy/Speed/Abstraction Continuum 7
2.1 Structure of Design as Schematic 12
2.2 Circuit Simulation Results. 15
2.3 RSFF Structure. . . . . . . . . 18
2.4 RSFF Simulation Results . . . 19
2.5 Circuit Initialization Problems 26
2.6 Circuit Behavior and Timing 27
2.7 Simulation of Variable Delay 32
2.8 Schematic with Generic Parameter Values 35
2.9 Delay Model . . . . . . . . 37
2.10 Input Delays . . . . . . . . 38
2.11 Configurations and Timing 46
2.12 VHDL Test Bench 48
2.13 RSFF Test Bench. . . . . . 49

3.1 Logic Diagram 2-Input Positive-Nand 58

3.2 Logic Diagram Open Collector 2-Input Positive Nand 60
3.3 Logic Diagram 2-Input Positive-Nor .. 62
3.4 Logic Diagram Inverter . . . . . . . . . 65
3.5 Logic Diagram Open-Collector Inverter 67
3.6 Logic Diagram 3-Input Positive-And 68
3.7 Logic Diagram 3-Input Positive-Nand 71
3.8 Logic Diagram 2-Input Positive-Or . . 74
3.9 Logic Diagram 2-Input Positive-Xor 76
3.10 Logic Diagram 3 to 8 Decoder/Multiplexer 80
3.11 Logic Diagram 2 to 4 Decoder/Multiplexer 84
3.12 Logic Diagram 1 of 8 Selector/Multiplexer. 87
3.13 Logic Diagram 1 of 4 Selector/Multiplexer. 92
3.14 Logic Diagram 1 of 2 Selector/Multiplexer. 96
3.15 Resistor strength drop . . . . . . . . . . . 102
3.16 Capacitor application . . . . . . . . . . . 103
3.17 Logic Diagram ALU /Function Generator 109
3.18 Logic Diagram One Shot. . . . . . . . . . 120
3.19 Logic Diagram 4 Bit Magnitude Comparator 124
3.20 Logic Diagram 9 Bit Odd/Even Parity Generator/Checker. 130

4.1 Logic Diagram D Pos Edge Flip-Flop with Preset/Clear 136

4.2 Logic Diagram JK Pos Edge Flip-Flop with Preset/Clear 141
4.3 Logic Diagram JK Neg Edge Flip-Flop with Preset/Clear 147
4.4 Logic Diagram JK Neg Edge Flip-Flop with Preset 153
4.5 Logic Diagram 4 Bit Parallel-Access Shift Register . . .. 159
4.6 Logic Diagram 3 to 8 Decoder/Demultiplexer . . . . . .. 165
4.7 Logic Diagram 3 to 8 Decoder/Demultiplexer with Latch 171
4.8 Logic Diagram 8 Bit Parallel-Out Serial Shift Register .. 177
4.9 Logic Diagram 8 Bit Parallel Load Shift Register . . . .. 183
4.10 Logic Diagram 8 Bit Parallel Load Shift Register with Clear 189
4.11 Logic Diagram 4 Bit Decade Counter with Async Clear 196
4.12 Logic Diagram 4 Bit Binary Counter with Async Clear. 202
4.13 Logic Diagram 4 Bit Decade Counter. . . . . . . . . 209
4.14 Logic Diagram 4 Bit Sync Binary Counter. . . . . . 215
4.15 Logic Diagram Bit Up/Down Sync Decade Counter. 221

5.1 Logic Diagram 1024 Bit ROM .. 232

5.2 Logic Diagram 16384 Bit PROM 236
5.3 Logic Diagram 64 Bit RAM 243
5.4 PAL16L8 Block Diagram 258
5.5 PAL16R6 Block Diagram 262
5.6 PAL16R8 Block Diagram 267

6.1 Bus Functional Model .. 270

6.2 TDC1028 Block Diagram 272
6.3 Capacitive Loading for Fujitsu MB86901 . 291
6.4 Model Development Time 304
6.5 Setup/Hold Time . . . . . 306
6.6 Hardware Model Testing . 307
 Preface

This book is intended to be a working reference for electronic hardware de-

signers who are interested in writing VHDL models. A handbook/cookbook
approach is taken, with many complete examples used to illustrate the fea-
tures of the VHDL language and to provide insight into how particular
classes of hardware devices can be modelled in VHDL. It is possible to use
these models directly or to adapt them to similar problems with minimal
effort.
This book is not intended to be a complete reference manual for the
VHDL language. It is possible to begin writing VHDL models with little
background in VHDL by copying examples from the book and adapting
them to particular problems. Some exposure to the VHDL language prior
to using this book is recommended. The reader is assumed to have a solid
hardware design background, preferably with some simulation experience.
For the reader who is interested in getting a complete overview of the VHDL
language, the following publications are recommended reading:
• An Introduction to VHDL: Hardware Description and Design [LIP89]

• IEEE Standard VHDL Language Reference Manual [IEEE87]

• Chip-Level Behavioral Modelling [ARMS88]

• Multi-Level Simulation of VLSI Systems [COEL87]

Other references of interest are [USG88], [DOD88] and [CLSI87]

Use of the Book

If the reader is familiar with VHDL, the models described in chapters 3

through 7 can be applied directly to design problems. A review of chapters
1 and 2 will give a clear overview of the methodology and intended scope
of the models described in this book. All other chapters can be used in
a reference fashion, reading only those sections which discuss the specific
type of device for which a VHDL model is desired.
Chapter 1 describes the history and background of the VHDL language
and provides recommendations on how to get started quickly with VHDL.
 Chapter 2 discusses the overall format of a VHDL file and the particular
methodology used in models described in this book.
Chapter 3 describes the VHDL models for a number of combinational
devices. The reader is encouraged to review this chapter before studying
other more complex device models.
Chapter 4 describes the VHDL models code for a wide variety of se-
quential devices including registers, flip-flops, counters and others.
Chapter 5 discusses memory devices and includes the VHDL source code
for devices ranging from RAMs and ROMS to PLAs.
Chapter 6 discusses the VHDL modelling of complex devices such as
microprocessors. Examples are given to highlight modelling techniques.
Recommendations regarding proper methodologies for complex devices are
given.
Finally, chapter 7 gives the complete VHDL source code for the standard
logic package and discusses how to build a logic value system, bus resolution
functions, logic modelling utilities and timing utilities.

Getting Started Quickly with VHDL

All of the examples in this book are written using strictly standard
VHDL which adheres to the IEEE standard 1076-1987 [IEEE87]. The mod-
elling features and approaches used in the VHDL code in this book have
been tested against both the Vantage and Intermetrics tools. Other tools
which adhere to the VHDL standard should handle the examples with-
out difficulty (assuming that the required VHDL features are available).
Virtually all of the examples in this book rely on the availability of the
Standard Logic Package described in chapter 7. The easiest and fastest
way to get started writing and simulating with VHDL models discussed in
this book is to get a copy of this standard package. This package is in the
public domain and is not specific to any particular VHDL environment.
Once compiled in your VHDL environment, you can reference this package
from your models and begin creating models which follow the conventions
and approaches discussed exactly as shown or with your own modifications
incorporated. By following this approach it should be possible to begin
writing VHDL models which simulate effectively within an afternoon. In
order to facilitate this process, all examples including the Standard Logic
Package discussed in this book are available on IBM PC floppy format for
MS-DOS. If you are interested in getting on-line VHDL source code for
the examples in this book send your request to Coelho Publications, 43000
Christy Street, Fremont, CA 94538-3167.
Background on the Writing of this Book

All examples cited in this book have been validated using the Vantage-
Spreadsheet simulation environment [VANU89] [VANT89] developed and
marketed by Vantage Analysis Systems, Inc. The text for this book was pre-
pared using the 'lEX text formatting system [LAM86] [KNU86] developed
by Donald Knuth at Stanford University running on an Apollo worksta-
tion with camera ready copy produced on an Apple Laserwriter. Graphics
figures were created using the Vantage environment for simulation results,
and AutoCAD [AUT88] for schematic and free form graphics.

Acknowledgments

Bill Billowitch provided insightful input into techniques for modelling

complex devices and is largely responsible for the discussions regarding the
modelling of microprocessors. Bill also contributed heavily in review of the
manuscript. I am greatful for Bill's substantial contribution.
I am indebted to Ken Scott, Doug Perry, Andy Tsay and Alec Stan-
culescu all of whom contributed to the development and evolution of the
standard logic package and the switch level modelling techniques. Thanks
also goes to others who reviewed the manuscript including Rick Lazansky,
Paul Krol, Tom Miller, Al Dewey, John Hines, John Van Tassel, Karen
Serafino, John Evans and David Hemmendinger.
The VHDL Handbook