{ STUDENT ID NO MULTIMEDIA @@— UNIVERSITY a MULTIMEDIA UNIVERSITY FINAL EXAMINATION ‘TRIMESTER 2, 20152016 TAOQ1221 -COMPUTER ARCHITECTURE AND ORGANIZATION (All sections / Groups ) 02 MARCH2016 230 pm. 430 pam, (2hows) INSTRUCTIONS TO STUDENTS 1. This Question paper consists of 5 pages including cover page with 6 Questions only. 2. Attempt FIVE out of SIX questions. All questions carry equal marks and the Aistibution ofthe marks foreach question is given, 3. Please print all your answers in the Answer Booklet provided,sora (onUTE ARCITECTURE AND ORCANZATION arc QUESTION 1 (@) Contemporary computer designs are based on concepts developed by Jobn von ‘Neumann at the Institue for Advanced Studies, Princeton. Describe the THREE @) key concepts of von Neumann architecture. [B masis) (©) Consider a hypothetical 24-bit microprocessor having 24-bit instructions composed of two fields: the first byte contains the opcode and the reminder contains the immediate operand or operand address, Assume that the word size is bits, i. Wha:is the maximum directly addressable memory cancity (in bytes)? ii, Discuss the impact on the system speed ifthe microprocessor bus has a 16- bit Tecal address bus and an 8-bit local data bus. iil, How many bits ere needed for the program counter and the instruction register, ifthe instruction register is to conten the whole instruction of only the opcode? [1 +3-+3 marks} ‘QUESTION? (@) List THREE.) major components in computer architecture. Explain the function ‘of each component (masks) (©) Explain TWO (2) basic tasks performed by a contol unit. [2 marks] (© Ininstuction processing, the basic instruction cycle is shown below: Fetch Cycle Execute Cycle ‘Assume tha the processor contains a program counter (PCI, « memory addzest ‘ester (MAR), a memory buffer repster (MBR), and an inscuction register (RR). ist the steps of actions taking pice during the Feteh Cycle [marks]‘gunstioN 3 (@) Given that A= (23), B= (4l)ia and C= (36) i. Represent A,B, and Cin 8-bit two's complement form. (3 marks] li, Perform the following arithmetic operatias in two's complement representation. Detect and provide reason if any overflow occurs alA+B) 0 mask bIC-B] Et mark] () Given the Booth's Algorithm flowchart: Gat) a= AeM ‘Arithmetic shit Right: A,Q,Q-1 f— Count Count] Show the steps using Booth’s Algorithm for performing the multiplication of two ‘bit two's complement binary numbers as given below: ‘Multipicand (4), = (0011) oF io Multiplier (Q) — =(1011)s0r(-5)o [Smaris} Continuedona \CONTUTER ANHOTECTURE AND ORGANATIN manca2a6 QUESTIONS (@ List any SIX (6) of the most common adiressing techniques used in microprocessors. (3 masks} () Given the following seaistes and memory values for an Intel 8085 microprocessor: Registers (a6 c [00H] O[77H E [10H (06H) 5H) ‘What js the value in the Accumulator (Register A) when the following instructions ae executed in sequence? Show the result for each instruction execution. i MVIB, SoH i, LDAXD i MOVMA iv. MVIAACH v. MOVDA vi MOVAM vii. ADDM vii, ADDE [smarks) (© Certain instructions in assembly language change the sequence of instruction execution. When this type of instructions is executed, the operation pecformed by the processor isto update the Program Counter (FC) to contsin the address of the next insruction in memory. These operations are called transfr-of-contrl; examples include Branch, Skip, and Procedure Call. Briefly discuss THREE (3) reasons why these operations are require. (Barks) Continued...mous COMPUTER ARCTECTURE AND ORGANZATION anc a6 QUESTION 5 (@) in caches, associative mapping is one of the mapping techniques used in smicroprocestor. What isthe advantage and disadvantage ofthis technique? [marks] (©) Consider a machire witha byte addressable main memory of 28 bytes and block size of 4 bytes. Assume that a direct mapped cache consisting of 8 lines is used ‘With this machine. How is an 8-bit memory address dived into tg, line number, sand byte number? Show the address format. [5 marks} (© Compare the following semiconductor memory types in terms of category, erasure, write mechanism, and volatlty: i. Random-ascess memory (RAM) Programmable read-only memory (PROM) iii. lash memory (3 marks) QUESTION 6 (@) An YO module is used to link external devices to the computer Briefly discuss FIVE (6) cetegories of function for an VO module, [S marks} (®)A bus organization is one of the approaches that could be used in the implementation of symmetric multiprocessor organization, Discass TAREE. (3) tractive features of this epprosch (6 mais] (© Snoopy prowcols distibute the responsibilty for maintaining eache coherence among all of the cache controllers in a multiprocessor system. One of the basic approaches in snoopy protocols is ‘write invalidate’. Briefly explain how ‘write {invalidate is able to maintain coherence among processors. [2 marks} End of Paper.