STUDENT ID NO MULTIMEDIA @ UNIVERSITY MULTIMEDIA UNIVERSITY FINAL EXAMINATION TRIMESTER 2, 2017/2018 TAO1221 - COMPUTER ARCHITECTURE AND ORGANIZATION (All sections / Groups ) 2 MARCH 2018 3.00 p.m. ~ 5.00 p.m. (2 hours ) INSTRUCTIONS TO STUDENTS 1. This Question paper consists of 6 pages including cover page with 5 Questions only. 2. Attempt ALL questions. All questions carry equal marks and the distribution of the marks for each question is given, 3. Please print all your answers in the Answer Booklet provided.raowa1 COMPUTER ARCHITECTURE AND ORGANIZATION AMARCH 2018, QUESTION 1 (@) The first major change in the electronic computer came with the replacement of the vacuum tube by the transistor. State FOUR (4) characteristics of transistors (2 marks} (b) Define Moore’s Law. Identify FIVE (5) consequences of Moore’s Law. (3 matks] (©) List the content of program counter (PC), instruction register (IR), memory address register (MAR) and memory buffer register (MBR) during execution of an instruction. [2 marks] (@) Contemporary computer designs are based on concepts developed by John von Neumann at the Institute for Advanced Studies, Princeton. Describe the THREE (3) key concepts of von Neumann architecture (3 merks] Continued ... MEALWYK 216TAOI2a1 COMPUTER ARCHITECTURE AND ORGANIZATION, 2. MARCH 2018; QUESTION 2 (@) Given the following instruction cycle state diagram, re-illustrate the state diagram to include the interrupt eycle processing. (2 marks} Multiple results Instruction complete, Retum for sting fetch next instruction or vector data (b) Instruction pipelining is an implementation technique where multiple instructions are overlapped in execution to increase the throughput. Given a scenario where 4 instructions take 5 time units each to complete the execution, and cach instruction has a number of 5 stages, namely FI, DI, FO, EI and WO. (Draw a timing diagram for the instruction pipeline operation described in the given scenario. [2 marks] (ii) Caleulate the total time required to complete the execution of all the instructions. [I mark] (iii) Calculate the speedup factor for the instruotion pipeline compared to the execution without the pipeline. (0 mark] (©) Explain TWO (2) basic tasks performed by a control unit. (2 marks] (@ Assume that the processor contains a program counter (PC), 2 memory address register (MAR), a memory buffer register (MBR), and an instruction register (IR). Illustrate the data flow for the sequences of micto-operations during fetch cycle. [2 marks} Continued .... MFAALWYR 376AOL (COMPUTER ARCHITECTURE AND ORGANIZATION 2 MARCH 2018, QUESTION 3 (@ Assume the usage of IEEE 64-bit format for the representation of floating-point number as given belo a 10000000011 | 0111010000000000000000000000000000000000000000000000 Sign | Biased Normalized Mantissa Bit [Exponent | (59 gts) (1 bit) | (11 bits) Identify the following: i, Biased exponent value in decimal [0.5 marks} ii, True exponent value in decimal {0.5 marks} iii, Sign of the number [0.5 marks} iv. Decimal equivalent of the given 64-bit floating point number [1.5 marks] (b) Given the Booth’s Algorithm flowchart: A~ 0, Q1-0 M-—— Muttiplicand Q + Multiplier Count = ¢ Am AGM Arithmetic shift Right: A,@,Q-1 }+—— Count ~~ Count-1 Continued MFAILWYK 476A012 (COMPUTER ARCHITECTURE AND ORGANIZATION 2MARCH2018 Show the steps using Booth’s Algorithm for performing the multiplication of two 4-bit two’s complement binary numbers as given below: Multipticand (M) Multiplier (Q) (0011)2 or (3)t0 (L011): or -5)i0 [4 marks] (© A computer system has a memory architecture made up of main memory of 5 GB and cache of 1 GB. In order to perform an efficient mapping function, the main memory is arranged in blocks of X bytes. Given the number of word bits = 10, find value X. Then, draw the address structure for Direct Mapping. [3 marks] QUESTION 4 (@) Describe the result after executing the following instructions in 8085 microprocessor: MVIB, 45H ii, ADDC [2 marks] (b) List FOUR(4) elements of computer instruction. [2 marks} (© Compare one-, two-, and three-address microprocessor by writing programs to compute: X=(AXB+C)/@-EXF) for each of the three microprocessor. The instructions available for use are as follows: T Address 2 Address 3 Address LOADM, MOVEX, YX €Y) MOVE X, YX €¥) STOREM | ADDX, Y& €X#¥) ADDX, ¥, ZK € YZ) ADDM SUBX, YK € XY) SUBX, V,ZK EVD) SUBM MUL X, YK € X¥Y) MULX, V, ZK € YZ) MULM DIVX, Y¥(X € XY) DIVX, Y,ZK EVD) DIVM [3x2 marks = 6 marks] Continued ... MRAILWYK 376AQHA (COMPUTER ARCHITECTURE AND ORGANIZATION 2MARCH 2016 QUESTION 5 (a) Describe FOUR(4) functions of /O module. [4 marks] (b) Compare memory-mapped I/O with isolated /O. [4 marks) (©) Ona typical microprocessor, a distinct I/O address is used to refer to the I/O data registers for a given device. Such registers are referred to as ports. In the Intel 8088, two 1/0 instruction formats are used. i. In one format, it uses 8-bit port address. Compute the number of ports that can be addressed using this format. ii, The second format uses 16-bit DX register. Compute the number of ports that can be addressed using this format. {2 marks] End of Paper. MFALWYK 676