F03 Hardware Design Guide: Release Date: July, 2019

F03 Hardware
Design Guide
Version: V1.0.0
Release Date: July, 2019

China Mobile IoT Co, Ltd.
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1
Revision History
Version Date Author Major Changes
V1.0.0 July 31, 2019 Initial version
2
Content
REVISION HISTORY .................................................................................................................................. 2
CONTENT................................................................................................................................................... 3
TABLE INDEX ............................................................................................................................................. 5
FIGURE INDEX ........................................................................................................................................... 7
1 FOREWORD ........................................................................................................................................ 8
1.1 Introduction .................................................................................................................................................. 8

1.2 Safety Information ...................................................................................................................................... 9
1.3 Reference Standard .................................................................................................................................. 10
1.4 Related Documents .................................................................................................................................. 12
2 OVERVIEW ....................................................................................................................................... 13
2.1 Introduction ................................................................................................................................................ 13

2.2 Specification ............................................................................................................................................... 14
2.3 Application Framework........................................................................................................................... 16
2.4 Hardware Block Diagram ....................................................................................................................... 17
3 APPLICATION INTERFACE .............................................................................................................. 18
3.1 F03 Interface ............................................................................................................................................... 18

3.1.1 Pin Map ............................................................................................................................................... 18
3.1.2 Pin Definition ..................................................................................................................................... 19
3.2 Power Supply.............................................................................................................................................. 22
3.2.1 Power Supply ..................................................................................................................................... 22
3.2.2 Logic Level .......................................................................................................................................... 24
3.2.3 Power Consumption ....................................................................................................................... 25
3.3 Control Signal ............................................................................................................................................ 27
3.3.1 Module Start-Up............................................................................................................................... 27
3.3.1.1 Start-up Circuit ......................................................................................................................... 27
3.3.1.2 Start-up Timing Sequence .................................................................................................... 28
3.3.2 Module Shutdown ........................................................................................................................... 29
3.3.3 Module Reset .................................................................................................................................... 30
3.3.4 PCIe Reset ........................................................................................................................................... 31
3.4 PCIe&USB .................................................................................................................................................... 32
3.4.1 PCIe Reset ........................................................................................................................................... 32
3.4.1.1 PCIe Interface Definition ....................................................................................................... 32
3.4.1.2 PCIe Interface Application .................................................................................................... 33
3.4.2 USB Interface ..................................................................................................................................... 35
3.4.2.1 USB Interface Definition ........................................................................................................ 35
3.4.2.2 USB Interface Application ..................................................................................................... 35
3
3.4.2.3 USB Interface Layout Guide ................................................................................................. 36

3.5 USIM Interface ........................................................................................................................................... 37
3.5.1 USIM1 Pins ......................................................................................................................................... 37
3.5.2 USIM Interface Circuit .................................................................................................................... 38
3.5.2.1 N.C. SIM Card Slot ................................................................................................................... 38
3.5.2.2 N.O. SIM Card Slot................................................................................................................... 38
3.5.2.3 Embedded UICC ....................................................................................................................... 39
3.5.3 USIM Hot-Plugging ......................................................................................................................... 40
3.5.4 USIM Design ...................................................................................................................................... 40
3.6 Status Indicator.......................................................................................................................................... 41
3.6.1 LED#1 Signal............................................................................................................................................... 41
3.7 Interrupt Control ....................................................................................................................................... 42
3.7.1 W_DISABLE1# .................................................................................................................................... 42
3.7.2 BODYSAR ............................................................................................................................................ 42
3.8 ANT Tunable Interface ............................................................................................................................ 43
3.9 Configuration Interface .......................................................................................................................... 44
3.10 Audio Interface .......................................................................................................................................... 45
3.11 Other Interfaces ........................................................................................................................................ 45
4 RADIO FREQUENCY ........................................................................................................................ 46
4.1 RF and mmWave IF Interface................................................................................................................ 46

4.1.1 RF and mmWave IF Interface Functionality ............................................................................ 46
4.1.2 RF Connector Characteristic ......................................................................................................... 48
4.1.3 RF Connector Dimension .............................................................................................................. 49
4.2 Operating Band ......................................................................................................................................... 51
4.3 Transmitting Power .................................................................................................................................. 52
4.4 Receiver Sensitivity ................................................................................................................................... 54
4.5 GNSS Receiver............................................................................................................................................ 57
4.6 Antenna Design ......................................................................................................................................... 58
4.6.1 Cellular Primary Antenna Requirements.................................................................................. 58
4.6.2 Cellular Rx MIMO Antenna Requirements .............................................................................. 58
4.6.3 GPS L1, GLO, BDS and GAL Antenna Requirements ............................................................ 59
4.7 Antenna Installation Guidelines........................................................................................................... 60
5 STRUCTURE SPECIFICATION .......................................................................................................... 61
5.1 Product Appearance ................................................................................................................................ 61

5.2 Dimension of Structure and Placement Concept .......................................................................... 61
5.3 F03 Connector............................................................................................................................................ 62
5.4 Storage ......................................................................................................................................................... 63
5.4.1 Storage Life ........................................................................................................................................ 63
5.5 Packing ......................................................................................................................................................... 63
6 RELIABILITY TEST ............................................................................................................................ 65
4
Table Index
Table 1-1 3GPP Standards ................................................................................................................................................ 10
Table 1-2 Non-3GPP Documentation .......................................................................................................................... 11
Table 3-1 Pin Definition .................................................................................................................................................... 19
Table 3-2 Power Interface ................................................................................................................................................ 22
Table 3-3 Filter Capacitor Design .................................................................................................................................. 23
Table 3-4 1.8V Logic Level Definition ........................................................................................................................... 24
Table 3-5 3.3V Logic Level Definition ........................................................................................................................... 24
Table 3-6 Power Consumption ....................................................................................................................................... 25
Table 3-7 Control Signal ................................................................................................................................................... 27
Table 3-8 Start-up Timing Prameter ............................................................................................................................. 28
Table 3-9 Shutdown Controls ......................................................................................................................................... 29
Table 3-10 Power off Timing Parameter ..................................................................................................................... 29
Table 3-11 Reset Timing Parameter .............................................................................................................................. 31
Table 3-12 PCIe Interface Definition ............................................................................................................................ 32
Table 3-13 PCIe Routing Constraints ........................................................................................................................... 34
Table 3-14 USB Interface Definition ............................................................................................................................. 35
Table 3-15 USB 2.0 Routing Constraints ..................................................................................................................... 36
Table 3-16 USB 3.1 Routing Constraints ..................................................................................................................... 36
Table 3-17 USIM1 Pins Definition ................................................................................................................................. 37
Table 3-18 AT Command Description .......................................................................................................................... 40
Table 3-19 Status Indicator Pin ...................................................................................................................................... 41
Table 3-20 LED#1 Signal ................................................................................................................................................... 41
Table 3-21 Interrupt Control Pin Definition ............................................................................................................... 42
Table 3-22 W_DISABLE1# Signal Definition ............................................................................................................... 42
Table 3-23 DPR Signal Definition .................................................................................................................................. 42
Table 3-24 ANT Tunable Interface ................................................................................................................................. 43
Table 3-25 Configuration Pin .......................................................................................................................................... 44
Table 3-26 Module Configuration ................................................................................................................................. 44
Table 3-27 Audio Interface .............................................................................................................................................. 45
Table 4-1 Functions Supported and Band Groups .................................................................................................. 47
Table 4-2 Supported air Interfaces ............................................................................................................................... 47
Table 4-3 mmWave IF Interface (option) .................................................................................................................... 48
Table 4-4 RF Connector Characteristic ........................................................................................................................ 48
Table 4-5 Operating Bands .............................................................................................................................................. 51
Table 4-6 WCDMA .............................................................................................................................................................. 52
Table 4-7 LTE FDD ............................................................................................................................................................... 52
Table 4-8 LTE TDD ............................................................................................................................................................... 53
Table 4-9 NR-FR1 FDD ...................................................................................................................................................... 53
Table 4-10 NR-FR1 TDD .................................................................................................................................................... 53
5
Table 4-11 WCDMA ............................................................................................................................................................ 54

Table 4-12 LTE FDD............................................................................................................................................................. 54
Table 4-13 LTE TDD ............................................................................................................................................................ 55
Table 4-14 NR-FR1 FDD .................................................................................................................................................... 55
Table 4-15 NR-FR1 TDD .................................................................................................................................................... 55
Table 4-16 GNSS Performance ....................................................................................................................................... 57
Table 4-17 Cellular Primary Antenna Requirements............................................................................................... 58
Table 4-18 Cellular Rx MIMO Antenna Requirements ........................................................................................... 58
Table 4-19 GPS L1, GLO, BDS and GAL Antenna Requirements ......................................................................... 59
Table 6-1 Test Conditions of the Reliability of the F03 LGA Module ................................................................ 65
6
Figure Index
Figure 2-1 Application Framework ............................................................................................................................... 16
Figure 2-2 Hardware Block Diagram ............................................................................................................................ 17
Figure 3-1 Pin Map ............................................................................................................................................................. 18
Figure 3-2 Power Supply Design ................................................................................................................................... 22
Figure 3-3 Power Supply Requirement ....................................................................................................................... 23
Figure 3-4 Circuit for Module Start-up Controlled by AP..................................................................................... 27
Figure 3-5 Timing Control for Start-up ....................................................................................................................... 28
Figure 3-6 Software Control Power off Timing......................................................................................................... 29
Figure 3-7 Recommended Design for Reset Circuit ............................................................................................... 30
Figure 3-8 Reset Control Timing1st ............................................................................................................................... 30
Figure 3-9 Reset Control Timing2nd.............................................................................................................................. 31
Figure 3-10 PCIe Reset Timing ....................................................................................................................................... 31
Figure 3-11 Requirement of PCIe Line ........................................................................................................................ 33
Figure 3-12 Length Match Design of PCIe Difference Pair .................................................................................. 34
Figure 3-13 Reference Circuit for PCIe Interface ..................................................................................................... 34
Figure 3-14 Reference Circuit for USB Interface ...................................................................................................... 35
Figure 3-15 Reference Circuit for N.C. ......................................................................................................................... 38
Figure 3-16 Reference Circuit for N.O. ........................................................................................................................ 38
Figure 3-17 Reference Circuit for e-UICC ................................................................................................................... 39
Figure 3-18 LED Driving Circuit ...................................................................................................................................... 41
Figure 3-19 Circuit Diagram of I2S Interface............................................................................................................. 45
Figure 4-1 RF Connectors ................................................................................................................................................ 46
Figure 4-2 RF Connector Dimensions .......................................................................................................................... 49
Figure 4-3 0.81mm Coaxial Antenna Dimensions ................................................................................................... 49
Figure 4-4 Schematic Diagram of 0.81mm Coaxial Antenna Connected to the RF Connector .............. 49
Figure 4-5 MM3929 Connector Dimension ............................................................................................................... 50
Figure 5-1 Module Appearance ..................................................................................................................................... 61
Figure 5-2 Dimension of Structure and Placement Concept ............................................................................... 61
Figure 5-3 F03 Dimension of Structure ....................................................................................................................... 62
7
1 Foreword
1.1 Introduction
This document describes the hardware of the F03 Module products. It helps you quickly retrieve
interface specifications, electrical and mechanical details, and information on the requirements to be
considered for integrating further components.
8
1.2 Safety Information

The following safety precautions must be observed during all phases of operation, such as usage,
service or repair of any cellular terminal or mobile incorporating with F03 module. Manufacturers of
the cellular terminal should send the following safety information to users and operating personnel,
and incorporate these guidelines into all manuals supplied with the product. If not so, China Mobile
assumes no liability for customers’ failure to comply with these precautions.
Full attention must be given to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes distraction
and can lead to an accident. Please comply with laws and regulations restricting the
use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation of
wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If the device offers an Airplane Mode, then it should be
enabled prior to boarding an aircraft. Please consult the airline staff for more
restrictions on the use of wireless devices on boarding the aircraft.
Wireless devices may cause interference on sensitive medical equipment, so please be

aware of the restrictions on the use of wireless devices when in hospitals, clinics or
other healthcare facilities.
Cellular terminals or mobiles operating over radio signals and cellular network cannot
be guaranteed to connect in all possible conditions (for example, with unpaid bills or
with an invalid SIM card). When emergent help is needed in such conditions, please
remember using emergency call. In order to make or receive a call, the cellular
terminal or mobile must be switched on in a service area with adequate cellular signal
strength.
The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it
receives and transmits radio frequency signals. RF interference can occur if it is used
close to TV set, radio, computer or other electric- equipment.
In locations with potentially explosive atmospheres, obey all posted signs to turn off
wireless devices such as your phone or other cellular terminals. Areas with potentially
explosive atmospheres include fueling areas, below decks on boats, fuel or chemical
transfer or storage facilities, areas where the air contains chemicals or particles such as
grain, dust or metal powders, etc.
9
1.3 Reference Standard

The design of the product complies with the following standards:
Table 1-1 3GPP Standards

3GPP TS 3GPP Release used as
specification Title the basis for this
reference declaration
Non-Access-Stratum functions related to Mobile Station (MS) in idle
23.122 11.4.0
mode
Mobile radio interface Layer 3 specification; Core network protocols;
24.008 11.5.0
Stage 3
25.331 Radio Resource Control (RRC); protocol specification 9.0.0
25.133 Requirements for Support of Radio Resource Management (FDD) 13.2.0
25.101 Radio Transmission and Reception (FDD) 14.0.0
24.301 (NAS) protocol for Evolved Packet System (EPS); Stage 3 11.7.0
36.101 (E-UTRA); User Equipment (UE) radio transmission and reception 12.14.1
36.133 (E-UTRA); Requirements for support of radio resource management 14.14.0
36.213 (E-UTRA) Physical layer procedures 12.11.0
36.214 (E-UTRA) Physical layer measurements 12.3.0
36.304 (E-UTRA); User Equipment (UE) procedures in idle mode 12.8.0
36.321 (E-UTRA); Medium Access Control (MAC) protocol specification 12.9.0
36.322 (E-UTRA); Radio Link Control (RLC) protocol specification 12.4.0
36.323 (E-UTRA); Packet Data Convergence Protocol (PDCP) specification 12.6.0
36.331 (E-UTRA); Radio Resource Control (RRC); Protocol specification 15.3.0
24.501 Non-Access-Stratum (NAS) protocol for 5G System (5GS); Stage 3 15.1.0
38.331 NR; Radio Resource Control (RRC) protocol specification 15.3.0
38.133 NR; Requirements for support of radio resource management 15.3.0
38.213 NR; Physical layer procedures for control 15.3.0
NR; Packet Data Convergence Protocol (PDCP) protocol
38.323 15.3.0
specification
37.324 Service Data Adaptation Protocol (SDAP) specification 15.1.0
Specification of the Subscriber Identity Module - Mobile Equipment
11.11/51.011 4.15.0
(SIM-ME) Interface
Characteristics of the Universal Subscriber Identity Module (USIM)
31.102 12.11.0
application
Characteristics of the IP Multimedia Services Identity Module (ISIM)
31.103 12.2.0
application
31.101 UICC-terminal interface; Physical and logical characteristics 12.2.0
27.007 AT command set for 3GPP User Equipment (UE) 9.9.0
36.355 (E-UTRA); LTE Positioning Protocol (LPP) 14.2.0
Location Services (LCS)– MS-SMLC Radio Resource LCS Protocol
44.031 14.3.0
(RRLP)
10
Table 1-2 Non-3GPP Documentation

ETSI
Document Source Title Version
ETSI TS 102 221: "UICC-Terminal interface; Physical and logical characteristics". 12.1.0
ETSI TS 102 223: “Smart Cards; Card Application Toolkit". 12.3.0
GSMA

GSMA IR.92 IMS Profile for Voice and SMS 8.0.0
GSMA IR.94 IMS Profile for Conversational Video Service 7.0.0
OMA
OMA OMA-AD-SUPL-V1
OMA OMA-AD-SUPL-V2
11
1.4 Related Documents

F02/F03 Module System Driver Integration and Application Guidance
F02/F03 AT Command User Guide
12
2 Overview
2.1 Introduction
F03 MODULE is a highly integrated 5G NR wireless communication module that supports standard
PCIe F03 interface and backward supports with LTE/WCDMA system. It is applicable to most
broadband communication networks of the mobile operator across the world. All relevant HW spec,
figures and design guidelines in this document are common specification for F03X, which is the sub-
series of F03.
13
2.2 Specification
Table 2-1 F03 Module Features
Specification
Platform QCT SDX55

5G Refarmed Sub6:
n1, n2, n3, n5, n7, n8, n12, n20, n28, n41, n66, n71
New Sub6:
n77, n78, n79
5G NR_mmWave:
n257, n258, n260, n261
LTE FDD:
Operating Band B1, B2, B3, B4, B5, B7, B8, B12, B13, B14, B17, B18, B19, B20, B25, B26, B28, B29, B30,
B32, B66, B71
LTE TDD:
B34, B38, B39, B40, B41, B42, B46, B48
WCDMA/HSPA+:
B1, B2, B3/9, B4, B5/6/19, B8
Simultaneous GPS:
L1/L5, GLONASS(GLO), Galileo (GAL) and BeiDou (BDS)
LTE LTE CAT20
5G sub-6 >2Gbps; 100MHz BW; MIMO 4x4
Downlink
5G mmWave >4Gbps; 800MHz BW; MIMO 2x2
LTE LTE CAT18
5G sub-6 1.2Gbps; 100MHz BW; MIMO 2x2
Uplink
5G mmWave >2Gbps; 400MHz BW; MIMO 2x2
UL 2x2 MIMO n41, n77, n78, n79
B1, B2, B3, B4, B7, B25, B30, B32, B38, B40, B41, B42, B48, B66
DL 4x4 MIMO
n1, n2, n3, n7, n41, n66, n77, n78, n79
Carrier Aggregation ULCA, DLCA and EN-DC
Power Supply DC 3.135V～3.465V (Typical value is 3.3V)
Operating temperature1:-10°C ～+55°C
Temperature Extended temperature2: -25°C ～+75°C
Storage temperature: -40°C ～+85°C
Interface: F03 Key-B
Physical Dimension: 30x52mm, Thickness=2.2mm(typ.)

Characteristics Weight: TBD
1. When temperature goes beyond normal operating temperature range of -10°C~+55°C,

RF performance of module may be slightly off 3GPP specifications.
2. When the module works at this temperature. NOT all its RF specifications comply with
the 3GPP RF specifications.
14
Interface
Antenna x 4
Antenna Connector mmWave Antenna x 3 (option)
Support 4x4 MIMO
Single USIM 2.95V/1.8V
PCIe Gen3_1xlane
USB2.0 HS /USB3.1 SS
W_Disable#
Function Interface
Body Sar
LED control pin
Tunable antenna(1xMIPI)
I2S(Reserved)
Software
Driver Windows 19H1 and later, Linux kernel v4.4 [3]
Protocol Stack IPV4/IPV6
AT Commands 3GPP TS 27.007 and 27.005
Firmware Update FOTA

Windows MBIM support
Windows update
Others Feature Support 5G NR NSA and SA
Multiple carrier aggregation
AGNSS
SW driver plan to support Android platform.
15
2.3 Application Framework

The peripheral applications for 5G F03 Module are shown in Figure 2-1.
Figure 2-1 Application Framework
16
2.4 Hardware Block Diagram

The hardware block diagram in Figure 2-2 shows the main hardware functions of 5G F03 Module,
including base band and RF functions.
Baseband contains the followings:
SDX55: 5G modem for mmWave and Sub-6G

PMU: PMX55 power management IC
MCP: NAND Flash and LPDDR4X
Application interface RF contains the followings:
RF Transceiver
RF Power/PA
RF Front end
RF Filter
Antenna Connector
Figure 2-2 Hardware Block Diagram
17
3 Application Interface
3.1 F03 Interface
The 5G F03 Module applies standard F03 Key-B interface, with a total of 75 pins.
3.1.1 Pin Map
Figure 3-1 Pin Map
Pin “Notch” represents the gap of the gold fingers.
18
3.1.2 Pin Definition
Table 3-1 Pin Definition

Reset DC
Pin Pin Name I/O Pin Description
Value Parameter
NC,5G 03X module is configured as the WWAN –
1 CONFIG_3 O NC
PCIe interface type
2 +3.3V PI Power input Power Supply
3 GND GND Power Supply
Power enable, Module power on input, internal pull
6 FULL_CARD_POWER_OFF# I PU CMOS 3.3V
up.
7 USB D+ I/O USB Data Plus 0.3---3V
8 W_DISABLE1# I TBD WWAN Disable, active low CMOS 3.3V
9 USB D- I/O USB Data Minus 0.3---3V
Support
10 LED1# O T System status LED control pin
10mA
12 Notch Notch
13 Notch Notch
14 Notch Notch
15 Notch Notch
16 Notch Notch
17 Notch Notch
18 Notch Notch
19 Notch Notch
20 I2S_CLK I/O Primary audio interface, MI2S clock 1.8V
NC,5G F03 module is configured as the WWAN –
21 CONFIG_0 NC
PCIe interface type
22 I2S_RX I/O Primary audio interface, MI2S codec 1.8V
23 WOWWAN# O TBD Wake up host, Reserved CMOS 1.8V
24 I2S_TX I/O Primary audio interface, MI2S codec 1.8V
25 DPR I TBD Body SAR Detect, active low CMOS 1.8V
26 W_DISABLE2# I TBD GNSS disable, active low, Reserved CMOS 1.8V
28 I2S_WA I/O Primary audio interface, MI2S word select 1.8V
AI/A
29 USB_3.1_TX- USB SS Tx Negative 1.8V
O
30 UIM1_RESET O TBD SIM1 reset signal 1.8V/2.95V
AI/A
31 USB_3.1_TX+ USB SS Tx Positive 1.8V
O
32 UIM1_CLK O TBD SIM1 clock Signal 1.8V/2.95V
19
Reset DC
Value Parameter
34 UIM1_DATA I/O TBD SIM1 data input/output 1.8V/2.95V
AI/A
35 USB_3.1_RX- USB SS Rx Negative 1.8V
O
36 UIM1_PWR O SIM1 power supply,2.95V/1.8V 1.8V/2.95V
AI/A
37 USB_3.1_RX+ USB SS Rx Positive 1.8V
O
Status indicator to request LAA QLNA to high
38 WLAN_TX_EN (I) I CMOS 1.8V
isolation
40 UIM2_DETECT2 I TBD SIM2 Detect, internal pull up(470KΩ), active high CMOS 1.8V
41 PETn0 O PCIe TX Differential signals Negative
42 UIM2_DATA2 I/O TBD SIM2 data input/output 1.8V/2.95V
43 PETp0 O PCIe TX Differential signals Positive
44 UIM2_CLK2 O TBD SIM2 clock Signal 1.8V/2.95V
46 UIM2_RESET2 O TBD SIM2 reset signal 1.8V/2.95V
47 PERn0 I PCIe RX Differential signals Negative
48 UIM2_PWR2 O SIM2 power supply,2.95V/1.8V 1.8V/2.95V
49 PERp0 I PCIe RX Differential signals Positive
Asserted to reset module PCIe interface default. If
module went into core dump, it will reset whole CMOS
50 PERST# I TBD module, not only PCIe interface. 3.3V(For
Active low. WoS)
(For Intel platform, NB side need level shift to 3.3V)
Asserted by device to request a PCIe reference
clock be available (active clock state) in order to
CMOS
transmit data. It also used by L1 PM Sub states
52 CLKREQ# O TBD 3.3V(For
mechanism, asserted by either host or device to
WoS)
initiate an L1 exit. Active low. (For Intel platform,
NB side need level shift to 3.3V)
53 REFCLKN I PCIe Reference Clock signal Negative
Asserted to wake up system and reactivate PCIe
CMOS
link from L2 to L0, it depends on system whether
54 PEWAKE# O TBD 3.3V(For
supports wake up functionality. Active low.
WoS)
55 REFCLKP I PCIe Reference Clock signal Positive
MIPI Interface Tunable ANT,
56 RFFE1_SDATA O CMOS 1.8V
RFFE1 data, Open Drain output
20
Reset DC
Value Parameter
MIPI Interface Tunable ANT,
58 RFFE1_SCLK O CMOS 1.8V
RFFE1 clock, Open Drain output
1.8V GPIO of
59 QTM0_PON # O TBD Enable for mmWave ANT0
SMR526
Status indicator to request QCA639x xFEMs to high
60 LAA_TX_ENABLE (O) O CMOS 1.8V
isolation
1.8V GPIO of
61 QTM1_PON# O TBD Enable for mmWave ANT1
SMR526
Wireless Coexistence between WWAN and WiFi/BT
62 COEX_RXD I TBD modules. CMOS 1.8V
IDC_UART_RXD
1.8V GPIO of
63 QTM2_PON# O TBD Enable for mmWave ANT2
SMR526
Wireless Coexistence between WWAN and WiFi/BT
64 COEX_TXD O TBD CMOS 1.8V
modules. IDC_UART_TXD
mmWave Antenna power supply, 1.9V Power supply
65 QTM_1P9 O TBD
VREG_S4E_1P904 of PMX55 1.9V
66 SIM1_DETECT1 I TBD SIM1 Detect, internal pull up(470KΩ), active high CMOS 1.8V
WWAN reset input, internal pull up(10KΩ), active
67 RESET# I CMOS 1.8V
low
68 1P8_GPIO (General purpose)
GND,5G F03 module is configured as the WWAN –
69 CONFIG_1 O GND
PCIe, interface type
GND,5G F03 module is configured as the WWAN –
75 CONFIG_2 O GND
PCIe, interface type
Reset Value: The initial status after module reset, not the status when working.
H: High Voltage Level OD: Open Drain
L: Low Voltage Level PP: Push-Pull
PD: Pull-Down PI: Power Input
PU: Pull-Up PO: Power Output
T: Tristate
The unused pins can be left floating.
21
3.2 Power Supply

The power interface of 5G F03 Module as shown in the following table 3-2:
Table 3-2 Power Interface

DC Parameter（V）
Pin Pin Name I/O Pin Description Minimum Typical Maximum
Value Value Value
2,4,70,72,74 +3.3V PI Power supply input 3.135 3.3 3.465
36 UIM_PWR PO USIM power supply - 1.8V/2.95V -
5G F03 Module uses PCIe interface, according to the PCIe specification, the PCIe Vmain should be
used as the +3.3V power source, not the Vaux. The Vaux is the PCIe backup power source and it is not
sufficient as the power supply. In addition, the DC/DC power supply other than PCIe ports should not
be used as the external power cannot control the module status through the PCIe protocol.
3.2.1 Power Supply
The 5G F03 Module should be powered through the +3.3V pins, and the power supply design is shown
in Figure 3-2:
Figure 3-2 Power Supply Design
22
The filter capacitor design for power supply as shown in the following table 3-3:
Table 3-3 Filter Capacitor Design

Capacitance Function Description
Reduce power fluctuations of the module in
operation, requiring capacitors with low ESR.
1. LDO or DC/DC power supply requires the
220uF x 2 Voltage-stabilizing capacitors
capacitor of no less than 440uF
2. The capacitor for battery power supply can
be reduced to 100~200uF
Filter out the interference generated from the
1uF,100nF Digital signal noise
clock and digital signals
700/800, 850/900 MHz frequency
39pF,33pF Filter out low frequency band RF interference
band
1500/1700/1800/1900,2100/2300
18pF,10pF,8.2pF, Filter out medium/high frequency band RF
,2500/2600MHz,3500/3700MHz,
6.8pF,3.3pF interference
5GHz frequency band
The stable power supply can ensure the normal operation of 5G F03 Module; and the ripple of the
power supply should be less than 300mV in design. Because module support 4x4 MIMO download,
when module operates with the maximum data transfer throughput, the maximum operating current
can reach to upper 3000mA. It requests the power source voltage should not be lower than 3.135V,
otherwise module may shut down or restart. The power supply requirement is shown in Figure 3-3:
Figure 3-3 Power Supply Requirement
23
3.2.2 Logic Level
5G F03 Module 1.8V logic level definition as shown in the following table 3-4:
Table 3-4 1.8V Logic Level Definition

Parameters Minimum Typical Maximum Unit
1.8V logic level 1.71 1.8 1.89 V

VIH 1.3 1.8 1.89 V
VIL -0.3 0 0.3 V
The 5G F03 Module 3.3V logic level definition as shown in the following table 3-5:
Table 3-5 3.3V Logic Level Definition

Parameters Minimum Typical Maximum Unit
3.3V logic level 3.135 3.3 3.465 V

VIH 2.3 3.3 3.465 V
VIL -0.3 0 0.3 V
24
3.2.3 Power Consumption
In the condition of 3.3V power supply, the 5G F03 MODULE power consumption as shown in the
following table 3-6:
Table 3-6 Power Consumption

Parameter Mode Condition
I Power off Power supply, module power off TBD
Off
DRX=6 TBD
WCDMA DRX=8 TBD
DRX=9 TBD
I
Sleep
LTE FDD Paging cycle #64 frames (0.64 sec DRx cycle) TBD
LTE TDD Paging cycle #64 frames (0.64 sec DRx cycle) TBD
Radio Off AT+CFUN=4, Flight mode TBD
WCDMA Data call Band 1 @+23.5dBm TBD
I WCDMA
WCDMA-RMS
LTE FDD Data call Band 1 @+23dBm TBD
I LTE FDD
LTE-RMS
25
Parameter Mode Condition
LTE TDD Data call Band 34 @+23dBm TBD

I LTE TDD
LTE-RMS
FR1 Data call n1 @+23dBm TBD
FDD FR1 Data call n8 @+23dBm TBD
Sub- FR1 Data call n20 @+23dBm TBD

6G FR1 Data call n28 @+23dBm TBD

I
5G NR-RMS
TDD FR1 Data call n77 @+26dBm TBD
FR2 Data call n257 @ TBD dBm TBD

mmWave
The data above is an average value obtained by testing some samples.
26
3.3 Control Signal

The 5G F03 Module provides power on/off and reset operations, the pin defined as shown in the
following table 3-7:
Table 3-7 Control Signal

Pin Pin Name I/O Reset Value Functions Type
Module power on/off input, internal pull up
6 FULL_CARD_POWER_OFF# I PU Power on: High/Floating 3.3V
Power off: Low
WWAN reset input, internal pull
67 RESET# I - 1.8V
up(10KΩ), active low
Asserted to reset module PCIe interface
default. If module went into core dump, it CMOS
50 PERST# I TBD will reset whole module, not only PCIe 3.3V(For
interface. Active low. (For Intel platform, NB WoS)
side need level shift to 3.3V)
RESET# and PERST# need to be controlled by independent GPIO, and not shared with other
devices on the host.
3.3.1 Module Start-Up
3.3.1.1 Start-up Circuit
The FULL_CARD_POWER_OFF# pin when transitioning from low to high. AP (Application Processor)
controls the module start-up，and the circuit design is shown in Figure3-4:
Figure 3-4 Circuit for Module Start-up Controlled by AP
27
3.3.1.2 Start-up Timing Sequence
When power supply is ready, the PMU of module will power on and start initialization process by
pulling high FULL_CARD_POWER_OFF# signal. After about 10s-time, module will complete
initialization process. The start-up timing is shown in Figure 3-5.
Figure 3-5 Timing Control for Start-up
Table 3-8 Start-up Timing Prameter

Index Minimum Typical Notes
+3.3V power supply rises time. If power supply always ready,
tpr - -
there is no tpr
ton1 TBD TBD If the RESET# has a residual voltage, then 30ms is necessary
ton2 TBD TBD PERST# should de-asserted after FULL_CARD_POWER_OFF#
28
3.3.2 Module Shutdown
The module can be shut down by the following controls table 3-9:
Table 3-9 Shutdown Controls

Shutdown Control Action Condition
Software Sending AT+CFUN=0 command Normal shutdown(recommend)

Pull down Only used when a hardware exception occurs
Hardware
FULL_CARD_POWER_OFF# pin and the software control cannot be used.
The module can be shut down by sending AT+CFUN=0 command. When the module receives the
software shutdown command, the module will start the finalization process (the reverse process of
initialization), and it will be completed after tsd time(tsd is the time which AP receive OK of
“AT+CFUN=0”,if there is no response, the max tsd is 5s). In the finalization process, the module will
save the network, SIM card and some other parameters from memory, then clear the memory and
shut down PMU. The software control timing is shown in Figure 3-6:
Figure 3-6 Software Control Power off Timing
Table 3-10 Power off Timing Parameter

Index Minimum Typical Maxim Notes
+3.3V power supply goes down time. If power supply is always
tpd TBD TBD -
on, there is no tpd
toff1 TBD TBD - RESET# should asserted before FULL_CARD_POWER_OFF#
toff2 TBD TBD toff1 PERST# should asserted after RESET#
29
3.3.3 Module Reset
The 5G F03 Module can reset to its initial status by pulling down the RESET# signal for more than
10ms (30msis recommended), and module will restart after RESET# signal is released. When customer
executes RESET# function, the PMU remains its power inside the module. The recommended circuit
design is shown in the Figure 3-7:
Figure 3-7 Recommended Design for Reset Circuit
There are two reset control timings as below:
− Host may keep FULL_CARD_POWER_OFF# high when system restarting, module reset timing is
shown in the Figure 3-8
− Host may assert FULL_CARD_POWER_OFF# high when system restarting, module reset timing is
shown in the Figure 3-9
Figure 3-8 Reset Control Timing1st
30
Figure 3-9 Reset Control Timing2nd
Table 3-11 Reset Timing Parameter

Index Minimum Typical Notes
tres1 TBD TBD RESET# should asserted time

PERST# should asserted after RESET#.
tres2 TBD TBD PERST# is not required for modem restart, thus this pin can be
remains high during restart
RESET# is a sensitive signal, it’s recommended to add a filter capacitor close to the module. In
case of PCB layout, the RESET# signal lines should keep away from the RF interference and
protected by GND. Also, the RESET# signal lines shall neither near the PCB edge nor route on
the surface planes to avoid module from reset caused by ESD problems.
3.3.4 PCIe Reset
Module supports PCIe goes in to D3cold L2 state in Win10 system. The D0->D3cold
L2@S0/S0ix/S3->D0 timing is shown in figure 3-10:
Figure 3-10 PCIe Reset Timing
31
3.4 PCIe&USB
5G F03 Module supports PCIe 3.0 1xlane for data throughput and USB 3.1 for commond.
3.4.1 PCIe Reset
5G F03 Module supports PCIe Gen3.0,1xlanes. After 5G F03 Module is inserted into PC, PCIe interface
can work with the driver, then map a MBIM port and a GNSS port in Win10 system. While MBIM
interface is used for initiating data service in Win10 system and GNSS interface for receiving GNSS
data.
3.4.1.1 PCIe Interface Definition
Table 3-12 PCIe Interface Definition

Pin# Pin Name I/O Reset Value Description Type
41 PETn0 O - PCIe TX Differential signals Negative -

43 PETP0 O - PCIe TX Differential signals Positive -
47 PERn0 I - PCIe RX Differential signals NegativeBit0 -
49 PERP0 I - PCIe RX Differential signals Positive -
53 REFCLKN I - PCIe Reference Clock signal Negative -
55 REFCLKP I - PCIe Reference Clock signal Positive -
Asserted to reset module PCIe interface default. If
module went into core dump, it will reset whole CMOS
50 PERST# I TBD
module, not only PCIe interface. Active low. 3.3V(For WoS)
Asserted by device to request a PCIe reference clock
be available (active clock state) in order to transmit
data. It also used by L1 PM Sub states mechanism, CMOS
52 CLKREQ# O TBD
asserted by either host or device to initiate an L1 exit. 3.3V(For WoS)
Active low.
Asserted to wake up system and reactivate PCIe link
from L2 to L0, it depends on system CMOS
54 PEWAKE# O TBD
whether supports wake up functionality. Active low. 3.3V(For WoS)
32
3.4.1.2 PCIe Interface Application
5G F03 Module supports PCIe Gen3.0, 1xlanes interface, including three difference pairs: transmit pair
TXP/N, receiving pair RXP/N and clock pair CLKP/N.
PCIe can achieve the maximum transmission rate of 8Gbit/s, and must strictly follow the rules below
in PCB Layout:
− The differential signal pair lines shall be parallel and equal in length;
− The differential signal pair lines shall be short if possible and be controlled within 300 mm for AP
end;
− The impedance of differential signal pair lines is recommended to be 85 ohm, and can be controlled
to 70～100 ohm in accordance with PCIe protocol;
− When the differential signal lines go through different layers, the via hole of grounding signal
should be in close to that of signal, and generally, each pair of signals require 1-3 grounding signal
via holes and the lines shall never cross the segment of plane;
− Try to avoid bended lines and avoid introducing common-mode noise in the system, which will
influence the signal integrity and EMI of difference pair. As shown in Figure 3-11, the bending angle
of all lines should be equal or greater than 135°, the spacing between difference pair lines should
be larger than 20mil, and the line caused by bending should be greater than 1.5 times line width
at least. When a serpentine line is used for length match with another line, the bended length of
each segment shall be at least 3 times the line width (≥3W). The largest spacing between the
bended part of the serpentine line and another one of the differential lines must be less than 2
times the spacing of normal differential lines (S1<2S);
Figure 3-11 Requirement of PCIe Line
33
− The difference in length of two data lines in difference pair should be within 5mil, and the length
match is required for all parts. When the length match is conducted for the differential lines, the
designed position of correct match should be close to that of incorrect match, as shown in Figure
3-12. However, there is no specific requirements for the length match of transmit pair and receiving
pair, that is, the length match is only required in the internal differential lines rather than between
different difference pairs. The length match should be close to the signal pin and pass the small-
angle bending design.
Figure 3-12 Length Match Design of PCIe Difference Pair
Table 3-13 PCIe Routing Constraints

Metrics Guidance
Data rate 8 Gbps (Gen 3.0) 5 Gbps (Gen 2.0)
Channel differential insertion loss -10 dB at 4 GHz -6 dB at 2.5 GHz
Bus length 290 mm 240 mm
Impedance* Differential Field route 70 to 100 
Length match Interline length match 5 ps (0.7 mm)
To all other signals 4 × line width
Spacing Field route
Rx-to-Tx 4 × line width 3 × line width
Component AC capacitor 176 to 265 nF 75 to 265 nF
Figure 3-13 Reference Circuit for PCIe Interface
34
3.4.2 USB Interface
− The 5G F03 Module supports both USB 3.1 Gen2 and USB 2.0 mode.
− For the USB timing and electrical specification of 5G F03 Module, please refer to “Universal Serial
Bus Specification, Revision 3.1”.
− When module inserted PC, USB can enumerate three ACM and three NCM ports in Android/Linux
system, the ports can be configured in practical application.
3.4.2.1 USB Interface Definition
Table 3-14 USB Interface Definition

Pin# Pin Name I/O Description Type
7 USB_D+ I/O USB Data Plus 0.3---3V, USB2.0

9 USB_D- I/O USB Data Minus 0.3---3V, USB2.0
29 USB_3.1_TX- AI/AO USB SS Tx Negative 1.8V
31 USB_3.1_TX+ AI/AO USB SS Tx Positive 1.8V
35 USB_3.1_RX- AI/AO USB SS Rx Negative 1.8V
37 USB_3.1_RX+ AI/AO USB SS Rx Positive 1.8V
3.4.2.2 USB Interface Application
The reference circuit is shown in Figure 3-14:
Figure 3-14 Reference Circuit for USB Interface
35
3.4.2.3 USB Interface Layout Guide
HS-USB and SS-USB guidelines

− External components must be located near the USB connector.
− There are relatively fast edge rates, so they must be routed away from sensitive circuits and
signals (RF, audio, and 38.4 MHz XO).
− If a USB connector is used as a charger input: The USB_VBUS node must be routed to the PMIC
device using extremely wide traces or sub-planes.
Additional SS-USB guidelines

− Maintain good isolation between the USB connector and RF antennas (especially 2.4 GHz).
− Route the RF signals operating at a 2.4 GHz frequency with the highest isolation possible from
USB_SS_TX/RX traces.
− USB SS Tx AC coupling can be anywhere along the line, but better be placed close to source
or the ESD/connector side to keep good SI of main route on PCB.
− Route differential pairs in the inner layers with a solid GND reference to have good impedance
control and to minimize discontinuities.
− Keep isolation between the Tx pair, Rx pair, and DP/DM to avoid crosstalk.
− If core vias are used, use no more than two core vias per signal line to limit stubs.
− If the total length exceeds 50 mm, route the lines with a zigzag pattern greater than 10°to
avoid ER mismatch caused by the glass-weave effect.
Table 3-15 USB 2.0 Routing Constraints

Metrics Guidance
Data rate 480 Mbps
Impedance Differential Field route 75-105 
Length match Intralane match 2 mm
Maximum PCB trace length 160 mm
Spacing To other signals Field route 3 × line width
Table 3-16 USB 3.1 Routing Constraints

Metrics Guidance
Data rate 10 Gbps (Gen 2) 5 Gbps (Gen 1)
Impedance* Differential Field route 70 to 100 
Channel insertion loss budget -7 dB at 5 GHz -5.5 dB at 2.5 GHz
USB SS or DisplayPort date lane intralane
5 ps (700 m)
match
Length match USB SS or DisplayPort date lane intralane
70 ps (10 mm)
match
DP_AUX_P/DP_AUX_M intralane match 50 ps (7 mm)
Rx-to-Tx 4 × line width 3 × line width
Spacing Field route
Space to other signals 4 × line width
Component AC capacitor 75 to 265 nF 75 to 200 nF
*The range of PCB impedance includes manufacturing variation. The PCB designer is responsible for
working with their PCB vendor to ensure each design falls within the published impedance range.
36
3.5 USIM Interface

The 5G F03 Module has dual built-in USIM card interface, which supports 1.8V and 2.95V SIM cards.
3.5.1 USIM1 Pins
Table 3-17 USIM1 Pins Definition

Pin Pin Name I/O Reset Value Description Type
36 UIM_PWR PO - USIM power supply 1.8V/2.95V
30 UIM_RESET O TBD USIM reset 1.8V/2.95V
32 UIM_CLK O TBD USIM clock 1.8V/2.95V
34 UIM_DATA I/O TBD USIM data, internal pull up(4.7KΩ) 1.8V/2.95V
USIM card detect, internal 470K pull- up.
Active high, and high level indicates SIM card
66 SIM_DETECT I TBD 1.8V
is inserted; and low level indicates SIM card
is detached.
37
3.5.2 USIM Interface Circuit
3.5.2.1 N.C. SIM Card Slot
The reference circuit design for N.C. (Normally Closed) SIM card slot is shown in Figure 3-15:
Figure 3-15 Reference Circuit for N.C.
SIM Card Slot The principles of the N.C.SIM card slot are described as follows:
− When the SIM card is detached, it connects the short circuit between CD and SW pins, and drives
the SIM_DETECT pin low.
− When the SIM card is inserted, it connects an open circuit between CD and SW pins, and drives the
SIM_DETECT pin high.
3.5.2.2 N.O. SIM Card Slot
The reference circuit design for N.O. (Normally Open) SIM card slot is shown in Figure 3-16:
Figure 3-16 Reference Circuit for N.O.
SIM Card Slot The principles of the N.O.SIM card slot are described as follows:
− When the SIM card is detached, it connects an open circuit between CD and SW pins, and drives
the SIM_DETECT pin low.
− When the SIM card is inserted, it connects the short circuit between CD and SW pins, and drives
the SIM_DETECT pin high.
38
3.5.2.3 Embedded UICC
Figure 3-17 Reference Circuit for e-UICC
eUICC being based on a microcontroller chip, when SW download the UICC profile and turn on UICC
function.
39
3.5.3 USIM Hot-Plugging
The 5G F03 Module supports the SIM card hot-plugging function, which determines whether the
SIM card is inserted or detached by detecting the SIM_DETECT pin state of the SIM card slot.
The SIM card hot-plugging function can be configured by “AT+MSMPD” command, and the
description for AT command as shown in the following table 3-18:
Table 3-18 AT Command Description

Hot-plugging
AT Command Function Description
Detection
Default value, the SIM card hot-plugging detection function is
enabled.
AT+MSMPD=1 Enable
The module can detect whether the SIM card is inserted or not
through the SIM_DETECT pin state.
The SIM card hot-plugging detect function is disabled. The module
AT+MSMPD=0 Disable reads the SIM card when starting up, and the SIM_DETECT status will
not be detected.
After the SIM card hot-plugging detection function is enabled, the module detects that the SIM card
is inserted when the SIM_DETECT pin is high, then executes the initialization program and finish the
network registration after reading the SIM card information. When the SIM_DETECT pin is low, the
module determines that the SIM card is detached and does not read the SIM card.
By default, SIM_DETECT is active-high, which can be switched to active-low by the AT

command. Please refer to the AT Commands Manual for the AT command.
3.5.4 USIM Design
The SIM card circuit design shall meet the EMC standards and ESD requirements with the improved
capability to resist interference, to ensure that the SIM card can work stably. The following guidelines
should be noted in case of design:
− The SIM card slot placement should near the module as close as possible, and away from the RF
antenna, DC/DC power supply, clock signal lines, and other strong interference sources.
− The SIM card slot with a metal shielding housing can improve the anti-interference ability.
− The trace length between the SIM card slot and the module should not exceed 100mm, or it could
reduce the signal quality.
− The UIM_CLK and UIM_DATA signal lines should be isolated by GND to avoid crosstalk interference.
If it is difficult for the layout, the whole SIM signal lines should be wrapped with GND as a group
at least.
− The filter capacitors and ESD devices for SIM card signals should be placed near to the SIM card
slot, and the ESD devices with 22~33pF capacitance should be used.
40
3.6 Status Indicator

The 5G F03 Module provides two signals to indicate the operating status of the module, and the status
indicator pins as shown in the following table 3-19:
Table 3-19 Status Indicator Pin

Pin Pin Name I/O Reset Value Pin Description Type
10 LED1# O TBD System status LED control pin Support10mA
23 WOWWAN# O TBD Module wakes up Host (AP)，Reserved CMOS 1.8V
3.6.1 LED#1 Signal

The LED#1 signal is used to indicate the operating status of the module, and the detailed description
as shown in the following table 3-20:
Table 3-20 LED#1 Signal

Module Status LED1# Signal
RF function ON Low level (LED On)

RF function OFF High level (LED Off)
The LED driving circuit is shown in figure 3-18:
Figure 3-18 LED Driving Circuit
Support 10mA for LED
41
3.7 Interrupt Control

The 5G F03 Module provides three interrupt signals, and the pin definition is as follow Table 3-21:
Table 3-21 Interrupt Control Pin Definition

Enable/Disable RF network
8 W_DISABLE1# I PD (For WOS is 1.8V, but need to add level shift CMOS 3.3V
3.3V for other application on platform side.)
25 DPR I PU Body SAR detection CMOS 1.8V
26 W_DISABLE2# I PU GNSS Disable signal, Reserved CMOS 1.8V
3.7.1 W_DISABLE1#
The module provides a hardware pin to enable/disable WWAN RF function, and the function can also
be controlled by the AT command. The module enters the Flight mode after the RF function is disabled.
The definition of W_DISABLE1# signal is as below table 3-22:
Table 3-22 W_DISABLE1# Signal Definition

W_DISABLE1# signal Function
High/Floating WWAN function is enabled, the module exits the Flight mode.
Low WWAN function is disabled, the module enters Flight mode.
3.7.2 BODYSAR
The 5G F03 Module supports Body SAR function by detecting the DPR pin. The voltage level of DPR
is high by default, and when the SAR sensor detects the closing human body, the DPR signal will be
pulled down. As the result, the module then lowers down its emission power to its default threshold
value, thus reducing the RF radiation on the human body. The threshold of emission power can be set
by the AT Commands. The definition of DPR signal as shown in the following table 3-23:
Table 3-23 DPR Signal Definition

DPR signal Function
High/Floating The module keeps the default emission power
Low Lower the maximum emission power to the threshold value of the module.
42
3.8 ANT Tunable Interface

The module supports ANT Tunable interfaces with two MIPI interface. Through cooperating with
external antenna adapter switch via ANT Tunable, it can flexibly configure the bands of LTE/Sub6G
antenna to improve the antenna’s working efficiency and save space for the antenna.
Table 3-24 ANT Tunable Interface

Pin Pin Name I/O Pin Description Type
65 RFFE_VIO O Tunable ANT control, MIPI Interface, RFFE VIO Power 1.8V
Tunable ANT control, MIPI Interface, RFFE1 clock, Open
63 RFFE1_SCLK O CMOS 1.8V
Drain output
Tunable ANT control, MIPI Interface, RFFE1 data, Open
61 RFFE1_SDATA O CMOS 1.8V
Drain output
43
3.9 Configuration Interface

The 5G F03 Module provides four configuration pins for the configuration as the PCIe-based WWAN
type F03 module:
Table 3-25 Configuration Pin

21 CONFIG_0 O NC
69 CONFIG_1 O NC
75 CONFIG_2 O L Internally connected to GND
1 CONFIG_3 O NC
The F03 module configuration as the following table:
Table 3-26 Module Configuration

Config_0 Config_1 Config_2 Config_3 Module Type and Main Port
(pin21) (pin69) (pin75) (pin1) Host Interface Configuration
NC NC GND NC WWAN–PCIe 3
Please refer to “PCI Express F03 Specification Rev1.1” for more details.
44
3.10 Audio Interface

F03 module provided one I2S PCM digital audio interface.
Table shows signals on the digital audio interface.
Table 3-27 Audio Interface

20 I2S_CLK I/O Primary audio interface, MI2S clock 1.8V

22 I2S_RX I/O Primary audio interface, MI2S codec 1.8V
24 I2S_TX I/O Primary audio interface, MI2S codec 1.8V
28 I2S_WA I/O Primary audio interface, MI2S word select 1.8V
Figure 3-19 Circuit Diagram of I2S Interface
1. The I2S function of F03 module is only supported in master mode.

2. It is recommended that a TVS be used on the related interface, to prevent electrostatic
3. Discharge and protect integrated circuit (IC) components.
4. The signal level of CODEC must match that of the F03 module.
3.11 Other Interfaces

The module does not support other interfaces yet.
45
4 Radio Frequency
4.1 RF and mmWave IF Interface
4.1.1 RF and mmWave IF Interface Functionality
The 5G F03 Module is equipped with four RF connectors and six mmWave IF connectors as shown in
Figure 4-1.
Figure 4-1 RF Connectors
46
The available RF connectors are:
Ant#0 and #2: Cellular primary Tx/Rx path
Ant#1: Combined Cellular Rx MIMO
Ant#3: Combined Cellular Rx MIMO and GPS GPS L1/GLONASS/BeiDou/Galileo Rx path
mmWave connector 0: module 0 (option)
mmWave connector1: module 1 (option)
mmWave connector 2: module 2 (option)
Detailed functionalities supported and band groups for each of RF connectors are listed in the
following table 4-1.
Table 4-1 Functions Supported and Band Groups

Ant_0 Ant_3 Ant_2 Ant_1
LB Tx/Rx Tx/Rx
MB Tx/Rx Rx Rx Rx
HB Tx/Rx Rx Rx Rx
5G n41 Tx/Rx Rx Tx/Rx Rx
5G n77/n78 Tx/Rx Rx Tx/Rx Rx
5G n79 Tx/Rx Rx Tx/Rx Rx
LTE B46 Rx Rx
GPS L1/GLO/BDS/GAL Rx
Supported air Interfaces for each of band groups are listed in the following table 4-2.
Table 4-2 Supported air Interfaces

Band Group Fmin (MHz) Fmax (MHz) Air Interface
WCDMA: B5/6/8/19
LTE FDD: B5/8/12/13/14/17/18/19/20/26/28/29/71
LB 600 960 LTE TDD: N/A
5G NR FR1 FDD: n5/8/12/20/28/71
5G NR FR1 TDD: N/A
WCDMA: B1/2/3/4/9
LTE FDD: B1/2/3/4/25/32/66
MB 1452 2170 LTE TDD: B34/39
5G NR FR1 FDD: n1/2/3/66
5G NR FR1 TDD: N/A
WCDMA: N/A
LTE FDD: B7/30
HB 2300 2690 LTE TDD: B38/40/41
5G NR FR1 FDD: n7
5G NR FR1 TDD: n41
47
n77 group also include B42/B48 function.
Table 4-3 mmWave IF Interface (option)

IF Interface Operating Band
mmWave Ant#0 5G NR FR2 TDD: n257/n258/n260/n261

4.1.2 RF Connector Characteristic
Table 4-4 RF Connector Characteristic

Rated Condition Environment Condition
Frequency Range DC to 6GHz Temperature Range

Characteristic Impedance 50Ω –40°C to +85°C
48
4.1.3 RF Connector Dimension
1. ANT_0/ ANT_1/ ANT_2 /ANT_3
5G F03 Module adopts standard F03 module RF connectors, the model name is 20449-001E from IPEX
company, and the connector size is 2*2*0.6m. The connector dimension is shown as following picture:
Figure 4-2 RF Connector Dimensions
Figure 4-3 0.81mm Coaxial Antenna Dimensions
Figure 4-4 Schematic Diagram of 0.81mm Coaxial Antenna Connected to the RF Connector
49
2. mmWave connector 0/1/2
mmWave connector adopts standard MM3929 from muRata company, and the connector size is
2*3*1.96m. The connector dimension is shown as following picture:
Figure 4-5 MM3929 Connector Dimension
50
4.2 Operating Band

The 5G F03 Module operating bands of the antennas are as follow table 4-5:
Table 4-5 Operating Bands

Band name Tx (MHz) Rx (MHz) LTE UMTS 5G NR
IMT (2100) 1920 - 1980 2110 - 2170 B1 B1 n1

PCS (1900) 1850 - 1910 1930 - 1990 B2 B2 n2
DCS (1800) 1710 - 1785 1805 - 1880 B3 B3 n3
AWS 1710 - 1755 2110 - 2155 B4 B4 –
Cell (850) 824 - 849 869 - 894 B5 B5 n5
JCELL (800) 830 - 840 875 - 885 B6
IMT-E (2600) 2500 - 2570 2620 - 2690 B7 n7
EGSM (950) 880 - 915 925 - 960 B8 B8 n8
B9 1749.9 - 1784.9 1844.9 - 1879.9 B9
700 lower A–C 699 - 716 729 - 746 B12 n12
700 upper C 777 - 787 746 - 756 B13
700 D 788 - 798 758 - 768 B14
B17 704 - 716 734 - 746 B17
B18 815 - 830 860 - 875 B18
B19 830 - 845 875 - 890 B19 B19
EU800 832 - 862 791 - 821 B20 n20
PCS + G 1850 - 1915 1930 - 1995 B25
B26 814 - 849 859 - 894 B26
700 APAC 703 - 748 758 - 803 B28 n28
FLO N/A 716 - 728 B29
WCS 2305 - 2315 2350 - 2360 B30
L-band N/A 1452 – 1496 B32
B34 2010 - 2025 B34
B38 2570 - 2620 B38
B39 1880 - 1920 B39
B40 2300 - 2400 B40
B41/B41-XGP 2496 - 2690 B41 n41
B42 3400 - 3600 B42
B46 5150–5925 B46
B48 3550 - 3700 B48
B66 1710 - 1780 2110 - 2200 B66 n66
B71 663 - 698 617 - 652 B71 n71
n77 3300 - 4200 n77
n78 3300 - 3800 n78
n79 4400 - 5000 n79
51
4.3 Transmitting Power

The transmitting power for each band of the L860 module as shown in the following table:
Table 4-6 WCDMA

Mode Band Typical Value (dBm) Note
Band 1 24 ±1
Band 2 24 ±1
Band 3 24 ±1
Band 4 24 ±1
Band 5 24 ±1
WCDMA
Band 6 24 ±1
Band 8 24 ±1
Band 9 24 ±1
Band 19 24 ±1
Table 4-7 LTE FDD

Band 1 23 ±1
Band 2 23 ±1
Band 3 23 ±1
Band 4 23 ±1
Band 5 23 ±1
Band 7 23 ±1
Band 8 23 ±1
Band 12 23 ±1
Band 13 23 ±1
Band 14 23 ±1
Band 17 23 ±1
LTE FDD
Band 18 23 ±1
Band 19 23 ±1
Band 20 23 ±1
Band 25 23 ±1
Band 26 23 ±1
Band 28 23 ±1
Band 29 23 NA
Band 30 23 ±1
Band 32 23 NA
Band 66 23 ±1
Band 71 23 ±1
52
Table 4-8 LTE TDD

Band 34 23 ±1
Band 38 23 ±1
Band 39 23 ±1
Band 40 23 ±1
LTE TDD Band 41 23 ±1
Band 42 23 ±1
Band 43 23 ±1
Band 46 23 ±1
Band 48 23 ±1
Table 4-9 NR-FR1 FDD

n1 23 ±1
n2 23 ±1
n3 23 ±1
n5 23 ±1
n7 23 ±1
NR-FR1
n8 23 ±1
FDD
n12 23 ±1
n20 23 ±1
n28 23 ±1
n66 23 ±1
n71 23 ±1
Table 4-10 NR-FR1 TDD

n38 24 ±1
n41 26 ±1
NR-FR1
n77 26 ±1
TDD
n78 26 ±1
n79 26 ±1
53
4.4 Receiver Sensitivity

The receiver sensitivity for each band of the 5G F03 Module as shown in the following table:
Table 4-11 WCDMA

Band 1 -110 BER<0.1%
Band 2 -110 BER<0.1%
Band 3 -110 BER<0.1%
Band 4 -110 BER<0.1%
Band 5 -111 BER<0.1%

WCDMA
Band 6 -111 BER<0.1%
Band 8 -111 BER<0.1%
Band 9 -110 BER<0.1%
Band 19 -111 BER<0.1%
Table 4-12 LTE FDD

Band 1 -101 Throughput ≥ 95%, 10 MHz Bandwidth
LTE FDD Band 18 -101 Throughput ≥ 95%, 10 MHz Bandwidth
54
Table 4-13 LTE TDD

LTE TDD Band 41 -101 Throughput ≥ 95%, 10 MHz Bandwidth
Table 4-14 NR-FR1 FDD

n1 -101 Throughput ≥ 95%, 10 MHz Bandwidth

NR-FR1
FDD
Table 4-15 NR-FR1 TDD

n38 -101 Throughput ≥ 95%, 10 MHz Bandwidth with15KHz SCS

NR-FR1
TDD
n79 -101 Throughput ≥ 95%, 10MHz Bandwidth with15KHz SCS
55
Other than 5G NR FR2, the above values are measured in two antennas situation (Ant0+Ant2).
For single primary antenna (without Ant1, Ant2, Ant3), the sensitivity will drop more than
3dBm for each band of LTE.
56
4.5 GNSS Receiver

F03 module integrats Global Navigation Satellite System (GNSS) solution that supports simultaneously
receiving GPS L1, GLONASS, BeiDou and Galileo signals. The GNSS could be worked in standalone
mode and assisted mode, according to the different configurations. In addition, with Integrated LNAs
and pre-SAW filters which allows the F03 module to work well with passive GNSS antennas.
The following table shows the GNSS performance of F03 module.
Table 4-16 GNSS Performance

Condition Test Result
Cold start 38s@-130dBm

TTFF
Hot Start 2s@-130dBm
GPS
Receive Tracking -157 dBm
Sensitivity Acquisition -163 dBm
1. Please note that GPS current is tested with RF disabled.

2. Performance will vary depending on the environment, antenna type and signal
conditions and so on.
3. Assuming 300-sec timeout for cold start sensitivity measurement.
57
4.6 Antenna Design

The antenna design is one of the most important aspect in the full product design as it strongly affects
the product overall performance. Hence, it is strongly recommended to follow the requirements and
the guidelines for a proper design.
4.6.1 Cellular Primary Antenna Requirements
Cellular primary antennas (ant#0 and ant#2) for the F03 module must meet requirements as shown in
the following table.
Table 4-17 Cellular Primary Antenna Requirements

Antenna Parameters Requirements
Depending by frequency band(s) provided by the network operator, the customer
shall use the most suitable antenna for that/those band(s).
Frequency range
The bands supported by the F03 module is provided in Section 4.1.1, RF and
mmWave IF Interface Functionality and Section 4.2, Operating Band.
Efficiency > 30%
Impedance 50 ohm
Input power > 26dBm average power 5G NR/LTE/WCDMA
VSWR recommended ≤ 2:1
VSWR absolute max ≤ 10:1
Cable Insertion Loss < 1dB
4.6.2 Cellular Rx MIMO Antenna Requirements
Cellular Rx MIMO antennas (ant#1 and ant#3) for the F03 module must meet requirements as shown
in the following table.
Table 4-18 Cellular Rx MIMO Antenna Requirements

Depending by frequency band(s) provided by the network operator, the customer
shall use the most suitable antenna for that/those band(s).
Frequency range
The bands supported by the F03 module is provided in Section 4.1.1, RF and
mmWave IF Interface Functionality and Section 4.2, Operating Band.
Efficiency > 30%
Impedance 50 ohm
Cable Insertion Loss < 1dB
58
4.6.3 GPS L1, GLO, BDS and GAL Antenna Requirements
GPS L1, GLO, BDS and GAL antenna (ant#3) for the F03 module must meet requirements as shown in
the following table.
Table 4-19 GPS L1, GLO, BDS and GAL Antenna Requirements
Wide-band GNSS: 1559–1606 MHz recommended
GPS L1: 1574.97~1576.443MHz (centered on 1575.42MHz)
Frequency range GLO: 1597.55~1605.89MHz (centered on 1602.5625MHz)
BDS: 1559.05~1563.14MHz (centered on 1561.098MHz)
GAL: 1563.144~1587.696MHz (centered on 1575.42MHz)
Polarization RHCP or linear
Passive antenna gain > -2dBi
Impedance 50 ohm
Cable Insertion Loss < 0.5dB
59
4.7 Antenna Installation Guidelines

− The antenna(s) used for transmitter must not be co-located or operating in conjunction with any
other antenna or transmitter.
− The antenna must not be installed inside metal cases.
− Install the antenna in a location with access to the network radio signal.
− The antenna must be installed according to the antenna manufacturer’s instructions.
60
5 Structure Specification
5.1 Product Appearance
The product appearance for 5G F03 Module is shown in Figure5-1:
TBD
Figure 5-1 Module Appearance
5.2 Dimension of Structure and Placement Concept

The structural dimension of the 5G F03 Module is shown in Figure 5-2:
Figure 5-2 Dimension of Structure and Placement Concept
61
5.3 F03 Connector

The 5G F03 Module connects to AP via F03 connector, it is recommended to use F03 connector from
FOXCONN company with the model AS0BC2x-S30BB-7H as shown in Figure 5-3. The package of
connector, please refer to the specification.
Figure 5-3 F03 Dimension of Structure
62
5.4 Storage
5.4.1 Storage Life
Storage Conditions (recommended): Temperature is 23 ± 5 ℃, relative humidity is less than RH 60%.

Storage period: Under the recommended storage conditions, the storage life is 12 months.
5.5 Packing
The F03 module uses ESD tray and vacuum bag into boxes. The example process shows in below
picture: (Pictures of materials are only for reference.)
63
64
6 Reliability Test
This chapter is definition reliability test item. Table 6-1 lists the test conditions of the reliability of the
F03 LGA module.
Table 6-1 Test Conditions of the Reliability of the F03 LGA Module
Item Test Condition
According to IEC61000-4-2 standard
Con Air
ESD
±2 kV ±2 kV
±6 kV ±6 kV
Shock Test According to MIL-STD-883, Method 2002.5, Condition B
(Reference test) 30 Half-sine/1,000G/0.5ms
According to IEC60068 standard
1. Temperature: 55°C
High temperature operation
2. Humidity: 50%RH
3. During time: 48hrs
According to IEC60068standard
Low temperature operation 1. Temperature: -20°C
1. Temperature: 55°C
High temperature High humidity
2. Humidity: 90%RH
1. Temperature: 75°C/ -40°C
Thermal shock
2. During time: 30mins
3. Test cycles: 168
High temperature storage 1. Temperature: 85°C
High temperature storage 1. Temperature: -40°C
According to ISTA 2A standard
1. Temperature storage: 70°C, 12 hrs, -20°C 12 hrs
2. High temperature High humidity: 65°C, 90%RH, 24 hrs
3. Drop test
a) 0 - 10kg: 97cm
Package test
b) 10 - 19kg: 81cm
c) 19 - 28kg: 66cm
4. Vibration test
a) Frequency 5~50 Hzs
b) Acceleration 1.44 m/s2
65

F03 Hardware Design Guide: Release Date: July, 2019

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V1.0.0 July 31, 2019 Initial version

TABLE INDEX ............................................................................................................................................. 5

FIGURE INDEX ........................................................................................................................................... 7

1.1 Introduction .................................................................................................................................................. 8

2.1 Introduction ................................................................................................................................................ 13

3 APPLICATION INTERFACE .............................................................................................................. 18

3.1 F03 Interface ............................................................................................................................................... 18

3.4.2.3 USB Interface Layout Guide ................................................................................................. 36

4 RADIO FREQUENCY ........................................................................................................................ 46

4.1 RF and mmWave IF Interface................................................................................................................ 46

5 STRUCTURE SPECIFICATION .......................................................................................................... 61

5.1 Product Appearance ................................................................................................................................ 61

6 RELIABILITY TEST ............................................................................................................................ 65

Table 4-11 WCDMA ............................................................................................................................................................ 54

1.2 Safety Information

Wireless devices may cause interference on sensitive medical equipment, so please be

1.3 Reference Standard

Table 1-1 3GPP Standards

Table 1-2 Non-3GPP Documentation

Document Source Title Version

Document Source Title Version

Document Source Title Version

1.4 Related Documents

F02/F03 AT Command User Guide

Platform QCT SDX55

Physical Dimension: 30x52mm, Thickness=2.2mm(typ.)

1. When temperature goes beyond normal operating temperature range of -10°C~+55°C,

LED control pin

Driver Windows 19H1 and later, Linux kernel v4.4 [3]

Protocol Stack IPV4/IPV6

AT Commands 3GPP TS 27.007 and 27.005

Firmware Update FOTA

Others Feature Support 5G NR NSA and SA

Multiple carrier aggregation

SW driver plan to support Android platform.

2.3 Application Framework

Figure 2-1 Application Framework

2.4 Hardware Block Diagram

Baseband contains the followings:

SDX55: 5G modem for mmWave and Sub-6G

Figure 2-2 Hardware Block Diagram

3.1.1 Pin Map

Figure 3-1 Pin Map

Pin “Notch” represents the gap of the gold fingers.

3.1.2 Pin Definition

Table 3-1 Pin Definition

3.2 Power Supply

Table 3-2 Power Interface

3.2.1 Power Supply

Figure 3-2 Power Supply Design

Table 3-3 Filter Capacitor Design

Figure 3-3 Power Supply Requirement

3.2.2 Logic Level

Table 3-4 1.8V Logic Level Definition

1.8V logic level 1.71 1.8 1.89 V

Table 3-5 3.3V Logic Level Definition

3.3V logic level 3.135 3.3 3.465 V

3.2.3 Power Consumption