FINAL EXAM, June 14th, 2018

Pulse train detector

The circuit detects trains of equally spaced pulses of 1 clock cycle length each, and outputs the
number of pulses for each detected train.

The figure above shows the output of the circuit for a given input.
A valid pulse train is a sequence of consecutive pulses, each pulse of one clock cycle length, and
with pauses of one clock cycle between them.
The first pulse of the train is preceded by either a longer pulse, or a longer pause.
The last pulse of the train is followed by either a longer pulse, or longer pause.
In the above two statements, 'longer' means having 2 clock cycles or more.
It is supposed that the input may change only at the negative edges of the clock.
The output consists of a 4 bit number (len), that shows the length, in number of pulses, of the last
detected train, and a 1 bit output (val) that validates the number and that is asserted for only one
clock cycle after a detected train. A pulse train may be validated no later than the start of the next
valid pulse train.

You are required to design and test the pulse train detector, whose interface is given below: