Learning objectives
By the end of this chapter you should be able to:
• show understanding of the basic Von Neumann model
• show understanding of the roles carried out by registers
• show understanding of the roles carried out by the
Arithmetic and Logic Unit (ALU), Control Unit and system
clock
• show understanding of how data are transferred between
various components of the computer system using the
address bus, data bus and control bus
• show understanding of ho·w the bus width and clock
speed are factors that contribute to the performance of
the computer system
• show understanding of the need for ports
• describe the stages of the fetch-execute cycle
• show understanding of 'register transfer' notation
• describe how interrupts are handled.
Cambridge International AS and A level Computer Science

5.01 The Von Neumann model of a computer system

The simplest form of what might be described as a computer system model or computer
system architecture is usually attri buted to John von Neumann. This recogn ises t he fact that
he was the first to describe the basic principles in a publ ication .

The model has the following basic features:

• There is a processor, a central processing unit.

• The processor has direct access to a memory.
• The memory con ta ins a 'stored program' (wh ich can be replaced by another at any time)
and the data required by the program .
• The stored program consists of in dividua l instructions.
• Th e processor executes instructions sequentially.

5.02 Central processing unit (CPU) architecture

Modern processors are extremely complex; some
of t he complexities w ill be discussed in Chapter (,:'\
~
19 (Sect ions 19.02 and 19.03). In t his chapter the
focus is on the fundamentals of the operation of
an up -to-date version of a simple von Neumann
computer system. r------ ---------------------- $---
Figure 5.01 gives a simplified schematic diagram I MDR
I
of a processor that could be part of this simple +~ ,~
system. The dotted outlin e shows the boundary
of the processor. The logica l arrangemen t of some I PC
I
t
~,
of the processor component s is indicated. The
arrows show possib le directions of flow of da ta.
,,
As th e fo llow ing discussion will show, the data for
some of the arrows is specifica lly an address or an
instruction. However, in general, data might be an
Control
Unit
CIR
I ,~
instruction, an add ress or a value. • >
t Other
registers
Components of the CPU Arithmetic
and
• >
The two major components of the CPU are t he
Logic Unit
arithmetic and logic un it (ALU) (or Arithmetic
Logic Unit) and the control unit. As its name ----------------------------------
implies, the ALU is responsible for any arithmetic Figure 5.01 A schematic diagram of the architecture of a simple CPU
or logic processing that might be needed when a
program is running. The functions of t he control
unit are more diverse. One aspect is controlling the flow of data throughout the processor
and , ind eed, t hroughout the whole co mputer system . Another is ensuring t hat program
instructions are handled correctly. A vital part of the control unit is a clock which is used
by t he unit to synchronise processes. Strictly speaking there are two clocks. The first is an
internal clock w hich controls the cycles of activity within the processor. The other is the
system clock wh ich controls activities outside the processor. The CPU will have a defined
frequency for its clock cycle, which is usually referred to as the clock speed. The frequency
defines the minimum period of time that separates successive activities within t he system.
.- - - - -- - - - - - - ~-,,
;

r :;· _ Chapter 5: Processor Fundamentals

~

I
Extension question 5.01
In an advertisement for a laptop computer, the system is described as 4GB, l TB, 1.7 GHz.

1 Which three components are being referred to here?

2 Have the values quoted been presented correctly? To answer this you need to refer back

I
to the discussion in Chapter l (Section 1.04) about terminology.
3 Calculate the minimum time period that could separate successive activities on this
system .

Registers
The other components of the CPU are the registers. These are sto ra ge component s wh ich,
because of their proximity to the ALU , allow very short access times. Each register has limited
storage capaci t y, typically 16, 32 or 64 bits. A register is either genera l purpose or special
purpose. If there is only o ne general-purpose register it is refe rred to as the accumulator.
For th e rest of this discussion and for the discussion in Chapter 6, the assumption will be that
t he processor does have j ust this one general-purpose register. The Accumulator is used to
store a single va lue at any one time. A va lue is sto red in t he Accumulator that is to be used
by the ALU for the execution of an instructi on . The ALU can then store a different value in the
Accumulator after the execution of the instruction .

•
Accumulator: a general-purpose registe r that stores a value before and after the execution of an
instruction by the ALU

Figure 5.01 shows some of the special -purpose registers as indivi du al components . The box
label led 'Other registers' can be considered to comprise the Accumulator plus the spec ial-
purpose registers not identified individually. The full names of the specia l-purpose registers
included in the simple CPU which we are going to discuss are given in Table 5.01 with a brief
descri pti on of their function .

Register name Abbreviation Register's function

Current instruction Stores the current instruction while it is being
CIR
register decoded and executed
Index registe r IX Stores a value; only used fo r indexed addressing
Memory address Stores the address of a memory location wh ich is
MAR
register about to have a value read from or written to
Memory data register
Stores data that has just been read from memory or
(memory buffer MDR (MBR)
is just about to be written to memory
register)
Stores the address of where th e next instruction is
Program counter PC
to be read from
Status register SR Contains ind ividual bits that are eithe r set or cleared

Table 5.01 Registers in a simple CPU

Two point s are worth making at t his point. The first is that the alternative name for the MOR
emphasises that th is particu lar register mu st act as a buffe r because transfers of data wi thin
the processor take place much more quickly than transfers outside the processor. Th is

f- - -
I - -- -~ - - - - -

Cambridge International AS and A level Computer Science

statement has to be slightly qua lified because the transfer could be to or from cache memory
which wo uld be a fast process but it is otherwise generally applicab le. The mention of cache
memory brings us to the second point which is that all discussion in this chapter and Chapter
6 ignores the fact that cache memory exists. All references are simp ly to memory as in
Table 5.01.

A further point to note here is that the index register (IX) can be abbreviated as IR but in some
sources the current instruction register (CIR) is abbreviated as 'IR', which is an unnecessary
potential cause of confusion. In this book, the index register is always IX and the curren t
instruction register is CIR. Finally, there is also possible confus ion if the abbreviation PC is
used_ This wi ll on ly be used in this book when register transfer notation is being used as you
will see later in the chapter. Everywhere else, a PC is a computer.

The SR is used when an instruction requires arithmetic or logic processing. Each individual
bit in the SR operates as a flag. The bit is set to 1 if a condition is detected. As an example, the
use of the following three flags will be illustrated:

• The carry flag, identified as C, is set to 1 if there is a carry.

• The negative flag, identified as N, is set to 1 if a result is negative.
• The overflow flag, identified as V, is set to 1 if overflow is detected_

WORKED EXAMPLE 5.01

Using the status register during an arithmetic operation

1 Consider the addition of two positive values where the sum of the two produces an
answer that is too large to be correctly identified with the limited number of bits used to
represent the values. For, example if an eight-bit binary integer representation is being
used and an attempt is made to add denary 66 to denary 68 the following happens:

0100 0010
+ 0100 0100

i Flags: N V C
1 1 0
1000 OllO

The value produced as an answer is denary - 122. Two positive numbers have been
added to get a negative number. This impossibility is detected by the combination of
t he negative flag and the overflow fl ag being set to 1. The processor has identified the
problem and can therefore send out an appropriate message.

2 Cons ider using the same eight-bit binary integer representation but this time two
negative numbers (- 66 and -68 in denary) are added:

lOll lllO
+ lOll llOO

i Flags: N V C
0 1 1
(1) Olll 1010

This t ime we get the answer +122. This impossibility is detected by the combination of
the negative flag not being set and both the overflow and the carry flag being set to 1.
 .,
; .~ _c1 r': ~ Chapter 5: Processor Funcl~mental,s ::
'. • ..! }1

I
Extension question 5.02
Carry out a comparable calculation for the addition in binary of-66 to +68 . What do you
think the processor should do with the carry bit?

t
5.03 The system bus
A bus is a parallel transmission component with each separate wire carrying a single bit It
is important not to describe a bus as a sto rage device. A bus does not hold data. Instead it
is a mechanism for data to be t ransferred from one system
component to another.

In the simple computer system described in this chapter

CPU
B
. r· ·. ..r. ·
Input and
Output

l
there wi ll be a system bus that comprises three distinct ' r ' ~

componen ts: the address bus, the data bus and the control ...........
bus. The schematic diagram of the CPU in Figu re 5.01
shows the logica l connection between each bus and a CPU I Control bus I
::i
V)

W' '
component The address bus is connected to the MAR; the .0

data bus to the MOR; and the control bus to the control unit I Address bus I 2
E

The system bus allows data flow between the CPU, the
' 't' 11'
(/)
V)
>,

Data bus
memory, and input or output (1/0) devices as shown in the
schematic diagram in Figure 5.02.
Figure 5.02 A schematic diagram of the system bus

•
The address bus
The sole funct ion of the address bus is to carry an address. This address is loaded on to the
bus from the MAR as and when directed by t he control unit The address specifies a location
in memory wh ich is due to receive data or from which data is to be read. The address bus is a
'one -way street '. It can only be used to send an address to a memory co ntroller. It cannot be
used to carry an address from the memory controller back to the CP U.

Address bus: a component that carries an address to the memory contro ller to identify a location in
memory which is to be read from or written to

I
Th e crucial aspect of the address bus is th e 'bus width', w hic h is th e number of separate wires
t in the bus. Th e number of w ires defines the number of bits in the address's binary code. In
the simple compute r system considered here we wil l assume that the bus width is 16 bits
allowing 65 536 memory locations to be directly addressed. Such a memory size would, of

I co urse, be totally inadequate for a modern computer system. Even doubling t he address bus
width to 32 bits wo uld on ly allow the direct addressing of a little over four billion ad dresses. If
th e memory size is too large special techniques have to be used.

The data bus

The fu nction of t he data bus is to carry data. This might be an instruction , an address or a
value. As can be seen from Figure 5.02, the data bus might be carrying the data from CPU to
memory or from memory to CPU.

However, another option is to carry data to or from an 1/0 device. The diagram does not
make clear whether, for instance, data comi ng from an input device is carried first to the CPU
or directly to the memory. Th ere is a good reason for t his. Some compu ter system s will only
Cambridge International AS and A level Computer Science

allow input to the CPU before the data can be stored in memory. Other systems will allow
direct transfer to memory.

Bus width is again an important factor in considering how the data bus is used. Before
discussing this, it is useful to introduce the concept of a word. A word consists of a number
of bytes and for any system the word length is defined. The significance of the word length is
that it defines a grouping that the system will handle as one unit. The word length might be
stated as a number of bytes or as a number of bits. Typical word lengths are 16, 32 or 64 bits
that is, 2, 4 or 8 bytes respectively. For a given computer system, the bus width is ideally the
same as the word length. If this is not possible the bus width can be half the word length so
that a full word can be transmitted by two consecutive data transfers. For our simple system
we assume a data bus width of 16 bits and a word length of two bytes to match this.

Data bus: a component that carries data to and from the processor
Word: a small number of bytes handled as a unit by the computer system

Extension question 5.03

Can you find out the bus widths used in the computer system you are using?

The control bus

The control bus is another bidirectional bus which transmits a signal from the control unit to
any other system component or transmits a signal to the control un it. There is no need for
extended width so the control bus typically has just eight wires. A major use of the control
bus is to carry timing signals. As described in Section 5.02, the system clock in the control
unit defines the clock cycle for the computer system. The control bus carries timing signals
at time intervals dictated by the clock cycle. This ensures that the time that one component
transmits data is synchronised with the time that another component reads it.

The clock speed is the most important factor governing the processing speed of the system.
However, it is not the only factor. The performance wil l be limited if the bus widths are
insufficient for the whole of a data value to be transferred in one clock cycle. For optimum
performance it is also particularly important that memory access is as efficient as possible.

The schematic diagram in Figure 5.02 slightly misrepresents the situation because it looks as .
if the CPU, the memory and the 1/0 devices have similar access to the data and control buses.
The reality is different. Each 1/0 device is connected to an interface called a port. Each port
is connected to the 1/0 or device controller. This controller handles the interaction between
the CPU and an 1/0 device. A port is described as 'internal' if the connected 1/0 device is an
integral part of the computer system. An external port allows the computer user to connect a
peripheral 1/0 device.

The universal serial bus {USB)

In the early days of the PC, the process of connecting a peripheral was time-consuming and
required technical expertise. The aim of the plug-and -play concept was to remove the need
for technical knowledge so that any computer user could connect a peripheral and start
using it straight away. The plug-and-play concept was only fully real ised by the creation of the
USB (Universal Serial Bus) standard. Nowadays anyone buying a new peripheral device will
expect it to connect to a USB port. There is an alternative technology known as FireWire but
this is not so commonly used in computer systems.
I ,
't ,-, ; · _ Chapter 5: Processor Fundamentals
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Some information about the USB standard:

• A hierarchy of connections is supported.

• The computer is at the root of this hierarchy and can handle 127 attached devices.
Devices can be attached while the computer is switched on and are automatically
configured for use.
• The standard has evolved, with USB 3.0 being the latest version.

Discussion Point:
Carry out an investigation into storage devices that could be connected as a peripheral to a
PC using the USB port.

For two representative devices find out which specific USB technology is being used and
what the potential data transfer speed is. How do these speeds compare with the speed of
access of a hard drive installed inside the computer?

5.04 The fetch-execute cycle

The full name for this is the fetch, decode and execute cycle. This is illustrated by the
flowchart in Figure 5.03.

START

NO
•
Transfer control to
interrupt-handling
program

NO YES

Figure 5.03 Flowchart for the fetch, decode and execute cycle
 - ------ -

Cambridge International AS and A level Computer Science ·(

.-

If we assume that a program is alread y runn ing then the progra m counter already holds the
address of an instruction. In the fetch stage, the fo llowing steps happen:

1 This address in the program counter is transferred within the CPU to the MAR.
2 During the next clock cycle two things happen simultaneously:
the instruction held in the address pointed to by the MAR is fetched into the MDR
• the address stored in the program counter is incremented .
3 The instruction stored in the MDR is transferred within the CPU to the CI R.
For our simp le system the program counter wil l be incremented by 1. However, it shou ld be
noted that the instruction just loaded might be a jump instruction. In this case, the program
counter contents will have to be updated in accordance with the j ump cond ition. This can
only happen after the instruction has been decoded.

In the decode stage, the instruction stored in the CIR is received as input by the ci rcuit ry
within the control un it. Depending on the type of instruction, the contro l unit w ill send
signa ls to the appropriate components so that the execute stage ca n begin. At th is stage, the
ALU wil l be activated if the instruction requires arithmetic or logic processing.

The description of the execute stage is postponed until Chapter 6, in wh ich a simp le
instruction set is introduced and discussed.

5.05 Register transfer notation

Operations involving registers can be described by register transfer notation. The si mplest
form of this can be illustrated by the fo llowing representation of the fetch stage of the fetch -
execute cycle:

MAR +- [PC]
PC +- [PC] + 1; MDR +- [[MAR)]
CIR +- [MDR)

The basic format for an individual data t ransfer is simi lar to that for variable ass ignment. The
first item is the destination of the data . Here the appropriate abbreviation is used to identify
the part icu lar registe r. To the right of the arrow showing the transmission of data is the
definition of this data. In this definition, the square brackets around a register abbreviation
show that t he content of t he register is being moved possibly with some ari t hmetic operation
being appl ied. When two dat a operations are placed on the same line separated by a
sem i- colon this means that the two transfers take place sim ultaneously. The dou ble pair of
brackets around MAR on the second line needs carefu l interpretation. The content of the MAR
is an address; it is the content of that address which is being t ransfe rred to the MDR.

5.06 Interrupt handling

There are many differen t reasons for an interrupt to be generated . Some examp les are:

• a fa tal erro r in a program

• a hardware fault
• a need for 1/ 0 processing to begin
• user interaction
• a t imer signal.
There are a number of different approaches possible for the detailed mechanisms used to
hand le interrupts but the overriding principles are clearly defined . Each different interrupt
(' - - ----- --

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f >, _ Chapter 5: Processor Fundamentals

needs to be hand led approp riately and different interrupt s mi ght possibly have d ifferent
priorities. Therefore, the processor must have a means of identifying the type of interrupt.
One way is to have an interrupt register in the CPU that works like the status register, with
each individual bit operating as a flag for a spec ific type of interru pt.

As t he flowchart in Figure 5.03 shows, t he existence of an interrupt is only detected at the

end of a fetch-execute cycle. This all ows the current program to be interrupted and left in a
defined state which can be returned to later. The first step in hand li ng t he interrupt is to sto re
the conten ts of the program counter and any ot her registers somew here safe in memory.

Following t his, the appropriate interru pt han dler or interrupt se rvice routine (ISR) program
is in itiated by load ing its start address into the program coun ter. When t he ISR program
has been execu ted there needs to be an immediate check to see if further interrupts need
handling. If there are none, the safely stored contents of the registers are restored to t he CP U
and the origina lly runn ing program is resumed.

• The von Neumann architecture for a computer system is based on the stored program concept.

• The CPU contain s a control unit, an arithmetic and logic unit, and registers.

• Registers can be special purpose or general purpose.

• The status register has individual bits acting as condition flags.

• The system bus contains the data, address and control buses.

• A universal serial bus (USB) port can be used to attach peripheral devices.

• Instructions are handled by the fetch-execute cycle.

• Register transfer notation is used to describe data transfers.

• If an interrupt is detected, control passes to an interrupt-handling routine.

Exam-style Questions
1 a A processor has just one general-pu rpose register. Give the name of th is register. [l ]

b The memo ry add ress register (MAR) is a specia l-purpose register. State:

its function

ii t he type of data stored in it

iii the register that supp li es t his data at the sta rt of t he fetc h stage of the fetch-execute cycle. [3]
Cambridge International AS and A level Computer Science

c The current instruction register (CIR) is another special-purpose register. State:

its function

ii the type of data stored in it

iii the register that supplies this data at the end of the fetch stage of the fetch-execute cycle. [3]

d Explain three differences between the memory address register and the memory data register. [5]

2 The system bus comprises three individual buses: the data bus, the address bus and the control bus.

a For each bus give a brief explanation of its use. [6]

b Each bus has a defined bus width.

State what determines the width of a bus . [l]

ii Exp lain which bus will have the least width . [2]

iii Explain the effect of changing the address bus from a 32-bit.bus to a 64-b it bus. [3]

3 The fetch stage of the fetch-decode - execute cycle can be represented by the follow ing statements using registe r
transfer notation:

MAR <-- [PC]

PC <-- [PC] + 1; MDR <-- [ [MARJ]
CIR <-- [MDR]

a Explain the meaning of each statement. The explanation must include definitions of the following items:
MAR, PC,[],+-, MDR, [[]], CIR. (10]

b Explain the use of the address bus and the dat a bus for two of the statements . (4]