oars EE Times - Sectatsoftowel-tanslation revaied = EE im Connecting the Global I Electronics Community AUTOMOTIVE News & Analysis Secrets of level-translation revealed NO RATINGS Prasad Dhond, Applications Specialist, LOGIN TO RATE Texas Instruments 40/27/2004 10:00 PMEDT Posta comment Tweat (0 To se mili Share 1 The need for logic vollage level translation is prevalent on most electronic systems today. For example, an ASIC might be operating with supply-voltage Voc, while an VO device operates with a different supply-voltage Voce. To enable these devices to communicate with each other, a level-translation solution is needed, Input-voltage thresholds and output- voltage levels of electronic devices vary, depending on the device technology and supply voltage used. Figure 1 shows the logic threshold levels for different supply voltages and device technologies. To interface two devices successfully, certain requirements must be met: 1. The Voy (Output High Voltage) of the driver must be greater than the VIH (Input High Voltage) of the receiver. 2. The Vox, (Output Low Voltage) of the driver must be less than the Vi. (Input Low Voltage) of the receiver. 3. The output voltage from the driver must not exceed the VO voltage tolerance of the receiver. There are several methods of achieving level translation and each method has its own merits and demerits. Figure 1, Digital Switching Levels — = wake ice Click to Enlarae Dual-supply level translators These are unidirectional or bidirectional devices with two supply vollage pins: one to interface with the low-voltage side and another to interface with the high-voltage side. Figure 2 shows one implementation of how a logic signal referenced to Vocais level-shifted to a signal referenced to VCCB. If logic high is applied to the input, transistor T9 in the level translating block turns on, and the output is pulled to VCCB through T10. ff logic Lowis applied at the input, transistors T6, T7 and T8 are turned on, and the output is pulled low through T11 eaties.comidocurrent.asp?doc_jd=12311118print=ys 69as3 EE Times - Sectatsoftowel-tanslation revaied Figure 2, How a push-pull level translator works Ver ia This design ensures that there is never a constant path from VCCA or VCCB to ground, which enables very low quiescent current consumption. Transistors T10 and T11 in the output block can be sized to offer the current drive required for the application. Figure 2 shows a uni-directional buffer, For bi-directional level shifting, a similar return path is required. Figure 3 shows an implementation of a dual-supply level-translator that uses a control signal to control the data flow direction. The advantage of this configuration is that the output drivers can be as strong as needed and maximum frequency is restricted only by the output load and switching speed of the output transistors. Consequently, these devices are typically designed to sink/source currents of up to several tens of mA and they support frequencies of up to several hundreds of Mbps. Figure 3. Fully Buffered Voltage Translation f= [== }—9} Glick to Enlarge Another implementation (Figure 4) does not require the direction control signal, but in turn has a restriction on the drive strength of the output transistors. In a DC state, the output drivers can maintain a high or low, but are designed to be weak, so thal they can be overdriven by an external driver when data on the bus starts flowing in the opposite direction. An output one-shot is used to provide high AC drive during output signal transitions. These devices have to be used carefully in applications that might have pulp or pull-down resistors on the /O lines since the resistors could contend with the weak output driver and cause bus contention. ‘Such a weakly buffered voltage translation circuit is an ideal solution for interface of two CMOS devices via a short transmission line (lumped load). If used to drive long trace lengths, transmission line effects will be observed depending on the duration that the one- shot is designed to stay on. F the one-shot is designed to stay on for a longer period of time, then the device can be used to drive longer transmission lines, but has lower maximum frequency capability, On the other hand, the one-shot can stay on for a shorter period of time which allows the device to have a higher maximum frequency capability, but trades off the capability to drive longer trace lengths. The one shot duration also affects the _wunoaimes.comdocurentasp?doc id= 12311118print=\soars EE Times - Sectatsoftowel-tanslation revaied maximum capacitance of the lumped load that can be driven. A very fast one-shot might not allow the AC drive to fully charge (discharge) the output capacitive load. The DC drive continues to charge (discharge) the capacitor but might be too weak to get the signal all the way to the rail before the next transition occurs. Figure 4. Weakly Buffered Voltage Translation Yeon Voce Pass-transistor voltage translation Figure 5 shows the transfer characteristics of an N-channel transistor with a threshold voltage (V7) of approximately 1 V. The output voltage tracks the input voltage til it gets clamped off at (V gare-V1), where Vgare is the gate voltage. This characteristic enables the N-channel transistor to be used in down-translation or voltage clamping applications. Figure 5 shows the transistor clamping off the output voltage at 3.3 V, 2.5 V, 1.8 V, 1.5V and 1.2 V by using a gate voltage 1 V higher than the maximum voltage desired at the output in each case. Sink current must be provided by the external driver. Because of the pass-transistor topology, the signal propagation delay through the transistor is extremely fast. Figure 5, Transfer Characteristics of an N-Channel Transistor For bi-directional voltage translation, pull-up resistors can be used to translate up as shown \eaties.comidocurrent.asp?doc_jd=12311118print=yos 369813 EE Times - Sera ofloe-trarsation rated in Figure 6. The gate bias is set at a maximum of one threshold above Vox desired on the low-voltage side. Data can flowin either direction without guidance from a control signal. This feature is essential in interfaces such as °C and 1-Wire where data is bi-directional and no control signal is available, Integrated circuit designs that use internal pull-up resistors could incorporate a one-shot that provides high AC drive by bypassing the pull-up resistors during the low+to-high transition to speed up the signal edge. Figure 6, Pass Transistor Voltage Translation Mec Voce Open-drain devices Devices with open drain outputs have an N-channel transistor (T1) between the output and GND. These devices can be used in level transtation applications as shown in Figure 7. The output voltage is determined by Vega. Voce can be greater than the input high-level voltage (up-translation) or lower than the input high-level voltage (down-translation). Open- drain devices are useful in translating to and from a variety of supply voltage nodes. However, there are some drawoacks to this method of level translation, When the output of the driver is low, i.e. when T1 is turned on, there will be a constant current flow from Voce to GND through the resistor Rpujjup and transistor T1. This contributes to higher system power consumption. Using a higher value pull up resistor can minimize this current flow. However, a larger resistor slows down the rise time of the output signal because of the higher RC time constant of the resistor Rpullup and the output capacitive load. Receiver ‘Open Drain Driver Glick to Enlarge Over-voltage tolerant devices Some devices have over-voltage tolerant inputs or Os that can tolerate voltage higher than the supply voltage. This capability is achieved by using thicker gate oxides and by blocking any parasitic paths from the input or /O to Veg. Such devices are useful in protecting a low-voltage device from a higher input voltage, For the situation shown in Figure 8, the input signal swings from 0 to 5 V, but since the translation device is operated _wunoaimes.comdocurentasp?doc id= 12311118print=\soats EE Times -Secrat of ewl-tanslaton revealed with Vec=3.3-V, it switches at 3.3-V threshold levels. This results in a difference in the propagation delay between low to high transitions and high to low transitions, causing an output duty cycle shift. Therefore, over-voltage tolerant devices might not be the ideal solution in clocking applications where output duty cycle is critical. Figure 8, 5-V to 3.3-V Translation Using An Over Voltage Tolerant Device Other Level Translation Methods Since 5-V TTL and 3-V LVTTL/LVCMOS switching thresholds are equal (see Figure 1), devices with inputs sized to accept 5-V TTL signals (at Vec=5 V) can be used to translate from 3.3 V to 5 V. This is a simple way of up-translating from 3.3 V LVTTL to 5 V CMOS. However, because the input high signals are not driven all the way to the 5-V rail, the input stages of the receiver device could draw extra static current called the Alog current. So this may not be an ideal solution for applications that require very low power consumption. Cost, power savings and other performance improvements are the driving forces behind migration to advanced process nodes and lower supply voltages. Since it is difficult for an entire system to migrate simultaneously to a lower supply voltage node, invariably, there will be system components operating at different supply voltages. To effectively realize system- level benefits which prompted migration in the first place, the voltage level translation solution must be chosen carefully. The system designer would ideally like the level translator to be transparent to the system, i.e. low cost, low power, fast propagation delay, no direction control, etc. No one solution can meet all these needs, Each level translation solution presents tradeoffs that the user must carefully assess to maximize benefits of voltage migration: Prasad Dhond is an Applications Specialist with TI's Standard Linear and Logic Group in ‘Sherman, TX. He has more than 2 years of experience with logic applications including voltage level translation. He holds a BSEE from the University of Texas at Austin. His email is pdhond@ti.com EMAIL THIS PRINT COMMENT Copyright © 2013 UBM Electronics, AUBM company, All rights reserved. Privacy Policy | Terms of Service _wunoaimes.comdocurentasp?doc id= 12311118print=\s