IMPLEMENTATION OF CALCULATOR USING FPGA

A Mini Project report

submitted in partial fulfilment of the requirement for the degree of

SHORT TERM TRAINING PROGRAMME

in
VLSI Design & FPGA Implementation

UNDER THE SUPERVISION OF

Ms. Vemu Sulochana (Project Engineer)

SUBMITTED BY

SAURABH KUMAR

Session: June – July 2019

Centre for Development of Advanced Computing, Mohali

 Declaration

This is to certify that Report entitled “ Implementation of calculator using FPGA” submitted by us
in partial fulfillment of the requirement for the award of degree M.Tech in VLSI Design, C-DAC,
Mohali under the super vision of Ms. Vemu Sulochana , Project Engineer , ACSD comprises
only our original work and due acknowledgement has been made in the text to all other material
used.

Date : 12/07/2019 Submitted by:

Saurabh Kumar
 Acknowledgement

Before we get into the thick of things, we would like to add a few words of appreciation
for the people who have been a part of this project right from its inception. The writing of
this project has been one of the significant academic challenges that we have faced and
without the support, patience and guidance of the people involved, it would not have been
possible to accomplish this task. It is to them we owe our deepest gratitude.

It gives us immense pleasure in presenting the project report on

“Implementation of calculator using FPGA”.

It has been our privilege to have a project guide who has assisted us from the
commencement of the project. The success of the project is a result of sheer hard work
and determination put in by us and our Project Guide. We, hereby take this opportunity to
add a special note of thanks for Ms.Vemu Sulochana(Project Engineer) who undertook
to act as our mentor despite her many other academic commitments. Without her insight,
support and energy, this project would neither have kick-started, nor
would have reached fruitfulness.
 Abstract

This report describes the project “Implementation of calculator using FPGA”. This
calculator performs six different types of tasks namely- Addition, Subtraction, division,
multiplication, square root of a number and square of a number. This calculator is a 4 bit
calculator. A calculator consists of an input bus and an output bus. The input bus
receives all the data for the calculator, operands and operators are all input through
this one bus. The output bus transmits the result of operation.The basic idea behind the
design is to eliminate tedious computations and algebraic manipulations that
discourages many students and allow them to solve problems and appreciate the power
an value of mathematics in the world today.
S. No. Content Page No.

1. Introduction 1

2. VLSI Design Flow 3

3. Design Simulation and synthesis 4

4. Introduction to FPGA : Spartan 3,3E and 6 6

5. VHDL Code 8

6. Results 23

7. Implementation using FPGA 26

Table of Contents
 INTRODUCTION

VLSI is the field which involves packing more and more logic devices into smaller and
smaller areas. Thanks to VLSI, circuits that would have taken boardfuls of space can now
be put into a small space few millimetres across! This has opened up a big opportunity to
do things that were not possible before. VLSI circuits are everywhere ... your computer,
your car, your brand new state-of the-art digital camera, the cell-phones, and what have
you. All this involves a lot of expertise on many fronts within the same field, which we
will look at in later sections

Need, Scope and use

VHDL is a language for describing digital electronic systems. It arose out of the United
States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in
1980. VHSIC Hardware Description Language (VHDL) was developed, and
subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers
(IEEE) in the US.

Need

VHDL is designed to fill a number of needs in the design process.

1) It allows description of the structure of a design that is how it is decomposed into sub-
designs, and how those sub designs are interconnected.

2) It allows the specification of the function of designs using familiar programming

language forms.

3) As a result, it allows a design to be simulated before being manufactured, so that

designers can quickly compare alternatives and test for correctness without the delay and
expense of hardware prototyping.

1
Scope

VHDL is suited to the specification, design and description of digital electronic hardware.

System level

VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-
software split. Simulation at this level is usually stochastic, and is concerned with
modeling performance, throughput, queuing and statistical distributions. VHDL has been
used in this area with some success, but is best suited to functional and not stochastic
simulation.

Digital

VHDL is suitable for use today in the digital hardware design process, from specification
through high-level functional simulation, manual design and logic synthesis down to
gate-level simulation. VHDL tools usually provide an integrated design environment in
this area.VHDL is not suited for specialized implementation-level design verification
tools such as analog simulation, switch level simulation and worst case timing
simulation. VHDL can be used to simulate gate level fan-out loading effects providing
coding

2
 VLSI Design Flow

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC)by

combining thousands of transistors into a single chip .The VLSI IC circuits design flow is
shown in the Fig.1. The various levels of design are numbered and the blocks show
processes in the design flow. Specifications comes first, they describe abstractly, the
functionality, interface, and the architecture of the digital IC circuit to be designed.
Behavioral description is then created to analyze the design in terms of functionality,
performance, compliance to given standards, and other specifications. RTL description is
done using HDLs. This RTL description is simulated to test functionality. From here
onwards we need the help of EDA tools

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Design Simulation and Design Synthesis

Synthesis

Is the process of translating a design description to another level of abstraction, i.e., from
behavior to structure. We achieved synthesis by using a Synthesis tool like Foundation
Express which outputs a net list. It is similar to the compilation of a high level
programming language like C into assembly code

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Simulation

Simulation is the execution of a model in a software environment. During design

creation/verification, a design is captured in an RTL-level (behavioral) VHDL source
file. After capturing the design, you can perform a behavioral simulation of the VHDL
file to verify that the VHDL code is correct. The code is then synthesized into a gate-
level (structural) VHDL net list. After synthesis, you can perform an optional pre-layout
structural simulation of the design. Finally, an EDIF net list is generated for use in
Designer and a VHDL structural post-layout net list is generated for timing simulation in
a VHDL simulator.

Design Creation/Verification

VHDL Source Entry

Enter your VHDL design source using a text editor or a context-sensitive HDL editor.
Your VHDL design source can contain RTL-level constructs.

Behavioral Simulation

Perform a behavioral simulation of your design before synthesis. Behavioral simulation

verifies the functionality of your VHDL code. Typically, you use zero delays and a
standard VHDL test bench to drive simulation.

Synthesis

After you have created your behavioral VHDL design source, you must synthesize it.
Synthesis transforms the behavioral VHDL file into a gate-level netlist and optimizes the
design for a target technology.

Simulation
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Then simulator will check functionality. It means that design and code should be working
according to truth table or not. Simulation is just testing the system at software level
where as real testing is at hardware level.

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 Introduction to FPGA : SPARTAN 3, SPARTAN 3E, SPARTAN 6

Xilinx

Xilinx Inc. is an American technology company, primarily a supplier of programmable

logic devices. It is known for inventing the field-programmable gate array (FPGA) and as
the first semiconductor company with a fabless manufacturing model.

Founded in Silicon Valley in 1984, the company is headquartered in San Jose, USA, with
additional offices in Longmont, USA; Dublin, Ireland; Singapore; Hyderabad, India;
Beijing, China; Shanghai, China; Brisbane, Australia and Tokyo, Japan.

Major FPGA product families include Virtex (high-performance), Kintex (mid-range)

and Artix (low-cost), and the retired Spartan (low-cost) series. Major computer software
includes Xilinx ISE and Vivado Design Suite.

Spartan family

The Spartan series targets low cost, high-volume applications with a low-power footprint
e.g. displays, set-top boxes, wireless routers and other applications.

The Spartan-6 family is built on a 45-nanometer [nm], 9-metal layer, dual-oxide process
technology. The Spartan-6 was marketed in 2009 as a low-cost option for automotive,
wireless communications, flat-panel display and video surveillance applications.

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Spartan 3E FPGA Family

 Spartan-3:

Introduction The Spartan®-3 family of Field-Programmable Gate Arrays is specifically

designed to meet the needs of high volume, cost-sensitive consumer electronic
applications. The eight-member family offers densities ranging from 50,000 to 5,000,000
system gates. The Spartan-3 family builds on the success of the earlier Spartan-IIE family
by increasing the amount of logic resources, the capacity of internal RAM, the total
number of I/Os, and the overall level of performance as well as by improving clock
management functions. Numerous enhancements derive from the Virtex®-II platform
technology. These Spartan-3 FPGA enhancements, combined with advanced process
technology, deliver more functionality and bandwidth per dollar than was previously
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possible, setting new standards in the programmable logic industry. Because of their
exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer
electronics applications, including broadband access, home networking,
display/projection and digital television equipment. The Spartan-3 family is a superior
alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy
development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA
programmability permits design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.

 Spartan-6:

General Description

The Spartan®-6 family provides leading system integration capabilities with the lowest
total cost for high-volume applications. The thirteen-member family delivers expanded
densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of
previous Spartan families, and faster, more comprehensive connectivity. Built on a
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mature 45 nm low-power copper process technology that delivers the optimal balance of
cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-
register 6-input lookup table (LUT) logic and a rich selection of built-in system-level
blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices,
SDRAM memory controllers, enhanced mixed-mode clock management blocks,
SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI
Express® compatible Endpoint blocks, advanced system-level power management
modes, auto-detect configuration options, and enhanced IP security with AES and Device
DNA protection. These features provide a lowcost programmable alternative to custom
ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution
for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive
embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for
Targeted Design Platforms that deliver integrated software and hardware components that
enable designers to focus on innovation as soon as their development cycle begins.

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 VHDL Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.NUMERIC_STD.ALL;

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 RESULTS
Timing Report:
Clock Information:
Clock Signal Clock buffer (FF name) Load
CLK BUFGP 38
clk251 BUFG 70
Asynchronous Control Signals Information:
Clock Signal Clock buffer (FF name) Load
RST IBUF 72

Timing Summary:
Speed Grade: -4
Minimum period: 10.319ns (Maximum Frequency: 96.909MHz)
Minimum input arrival time before clock: 2.444ns
Maximum output required time after clock: 7.165ns
Maximum combinational path delay: No path found

Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 7.350ns (frequency: 136.054MHz)
Total number of paths / destination ports: 1400 / 77
Delay: 7.350ns (Levels of Logic = 9)
Source: counter_1s_8 (FF)
Destination: delay_count_0 (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Data Path: counter_1s_8 to delay_count_0
Total 7.350ns (3.971ns logic, 3.379ns route)
(54.0% logic, 46.0% route)

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Timing constraint: Default period analysis for Clock 'clk251'
Clock period: 10.319ns (frequency: 96.909MHz)
Total number of paths / destination ports: 6022 / 102
Delay: 10.319ns (Levels of Logic = 13)
Source: vPos_3 (FF)
Destination: RGB_0 (FF)
Source Clock: clk251 rising
Destination Clock: clk251 rising
Data Path: vPos_3 to RGB_0
Total 10.319ns (4.865ns logic, 5.454ns route)
(47.1% logic, 52.9% route)

Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'

Total number of paths / destination ports: 1 / 1
Offset: 2.444ns (Levels of Logic = 2)
Source: sensor (PAD)
Destination: current_state_FSM_FFd2 (FF)
Destination Clock: CLK rising
Data Path: sensor to current_state_FSM_FFd2
Total 2.444ns (1.575ns logic, 0.869ns route)
(64.4% logic, 35.6% route)

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk251'

Total number of paths / destination ports: 5 / 5
Offset: 7.165ns (Levels of Logic = 1)
Source: VSYNC (FF)
Destination: VSYNC (PAD)
Source Clock: clk251 rising
Data Path: VSYNC to VSYNC
Total 7.165ns (6.364ns logic, 0.801ns route)
(88.8% logic, 11.2% route)

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Simulation

14
Implementation using FPGA on VGA

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