A Current-Starved Inverter-Based Differential Amplifier Design for Ultra-Low

Power Applications
William Wilson, Tom Chen, Ryan Selby
Department of Electrical & Computer Engineering
Colorado State University, Fort Collins, CO 80523 USA

Abstract – As silicon feature sizes decrease, more complex circuitry
arrays can now be contrived on a single die. This increase in the number
of on-chip de vices per unit area results in increased power dissipation per
unit area. In order to meet certain power and operating temperature
spe cifications, circuit design necessitates a focus on power efficiency,
which is especially important in systems employing hundreds or
thousands of instances of the same device. In large arrays, a slight
increase in the powe r efficiency of a single component is heightened by
the numbe r of instances of the device in the system. This paper proposes
a fully differential, low-power current-starving inverter-based amplifier
topology designed in a commercial 0.18µm process. This design achieves
46dB DC gain and a 464 kHz unity gain frequency with a power
consumption of only 145.32nW at 700mV power supply voltage for ultra-
low powe r, low bandwidth applications. Higher bandwidth designs are
also proposed, including a 48dB DC gain, 2.4 MHz unity-gain frequency
amplifier operating at 900mV with only 3.74µW power consumption.
INTRODUCTION
Operational amplifiers are essential components in many signal
processing circuit designs. Almost any type of analog circuits,
including most continuous or discrete time amplifiers, analog to
digital converters, sense amplifiers, and many other circuits use some
variety of operational amplifiers as their basic building blocks. These
and various other circuit designs are used in many tasks, including
the amplification of small signals, as well as various types of mixed-
domain processing for complex audio and video signals.[1]
schemes have been improving with the usage of active compensation
networks. [3-13]
Reduced power supply voltage and the increasing demand for low
power consumption make sub-threshold operation and design a more
viable alternative when a reduction in bandwidth is acceptable.
Operation in the sub-threshold region causes the drain current to
increase exponentially with VGS as opposed to quadratically in the
saturation region [14]. The disadvantage with sub-threshold
operation is the reduction in amplifier driving current, and the loss of
ability to quickly drive large capacitive loads.
In this paper, an inverter-based operational amplifier topology
and operation and design principles are discussed and evaluated. We
use two previously used figures of merit to objectively compare
various aspects of the different circuit topologies. We conclude that
the inverter-based differential amplifier topology with current
starving provides one of best circuit topologies for energy efficiency.
PROPOSED DESIGN
A prior attempt at achieving high gain with minimal DC current
usage and minimal area is the use of CM OS inverters in a differential
configuration [15-18].

M any large-scale system-on-chip designs such as imaging and

sensing arrays use complex signal processing chains. These systems
often use mixed-signal chains in sub-µm processes. These reduced
channel length processes have desirable effects on performance and
overall size in digital circuitry; however, reduced channel lengths
have undesirable effects in analog circuit designs. Low power supply
voltages and decreased output impedance, as well as limited gain of
single transistor stages make analog circuit design in sub-µm a
challenging task [2].

Traditional operational amplifier designs most commonly use

transistors in the saturation region, which generally requires at least
one DC bias current. As technology size has decreased, low power,
high gain amplifier design has become more ch allenging for
designers. Since transistor threshold voltage generally doesn’t
decrease as fast as feature size and power supply voltage, many
cascaded or folded designs are not possible with reduced voltage
supply. Given that the reduction in headroom reduces the ability to
cascode devices, low voltage high-gain amplifiers are commonly
built by expanding outward, using two or even three cascaded
amplification stages. These multi-stage cascaded designs require the
designer to take extra measures to ensure amplifier stability, and,
depending on the topology, can be very challenging or complex to
stabilize. M ost stabilization schemes require additional compensation
capacitors and/or nulling resistors, which use additional silicon area,
and can decrease circuit bandwidth; however, these compensation
978-1-4673-4900-0/13/$31.00 ©2013 IEEE
F IGURE 1: INVERTER-BASED O P -AMP
The inverter-based amplifier topology shown in Figure 1 uses
CMOS inverters as the amplifier input. This input stage design has
the advantage of combining the transconductance of the n and p
transistors.
Gm  Gmn  Gmp
This combination of the two transconductances should provide
6dB increase in gain over a traditional common source amplification
stage, with approximately the same DC bias current. When this
architecture is implemented with a standard supply voltage (>2v t),
the overall transconductance can be increased significantly
depending on how transistors in the inverters are sized and the
resulting current through the inverter. High current through the
inverter allows significantly high bandwidths to be achieved.
Another advantage of this topology is an increase in output swing
and linearity when compared to a traditional common source or
cascode amplifier if the respective transconductances of the p and n
type transistors are approximately equal in magnitude. For noise, the
inverter-based topology offers lower equivalent noise resistance
compared to the equivalent common source topology [20]. Assuming
the p and n type transistors are balanced and the equivalent noise
resistances for the n and p type transistors is R Nn, and RNp,
respectively, the equivalent noise resistance for the inverter based
amplifier is FIGURE 3: ACTIVE LOAD WITH POSITIVE FEEDBACK
2
Gmn RNn  Gmp
2
RNp RNn The positive portion of the resistance provided by the diode
RN  
G  Gmp  connected inverters helps stabilize the inherently unstable negative
2
2
mn
impedance of the cross-coupling, as well as providing additional DC
bias stability for both the input and cross-coupled inverter pairs. This
One weakness of the inverter-based amplifier is its limited combination of positive and negative impedances gives the active
CM RR when configured in a differential mode as shown in Figure 1. load circuit an overall output impedance of
This issue will be addressed in the next sub-section. 1
Ro 
g m 2  g m3
Sub-Threshold Operation With Current Starving Tails
Assuming low mismatch between the M 2 and M 3 inverter pairs,
this gives extremely high output impedance. Similar to a folded
When this inverter-based architecture is implemented at a low
cascode, this circuit combines the transconductance of the input pair
supply voltage (<2vt), the inverter transistors will operate in the sub-
with the output impedance of the cross coupling and diode-connected
threshold region. Because of this region of operation, bias currents
inverters. The overall voltage gain of the amplifier’s half-circuit can
and power consumption can be significantly reduced, with the
then be defined as
sacrifice of bandwidth and amplifier driving strength. A tail current
source can be added to better control the current flow through the
inverters, pushing the transistors further into the sub-threshold
region, and further reducing power consumption. The tail can also When sizing the transistors in this design, it is desirable for the
improve the amplifier’s CM RR and provide an additional input that input and tail transistors to have reasonably large lengths (typically
can be used for common-mode feedback, circumventing the issue >1µm) and large W/L ratios (typically >16) to improve output
with the original inverter-based design in [15-18]. In addition, the impedance, and to have an increased transconductance. Large
use of tail separates the need for low power consumption and low lengths, especailly in the cross-coupled inverters help alleviate the
input offset voltage. Inverters can be sized appropriately to control effects of PVT.
offset voltage while the tail controls the overall power consumption
allowed by the inverter.
SIMULATION RESULTS AND DISCUSSIONS
The current starved inverter-based amplifier was designed for
three different supply voltages of 0.7V, 0.9V, and 1.1V, allowing it
to operate at different levels of sub-threshold regions with different
driving strength. With the aim for low-power bioelectronics
applications, the design goal is to achieve the maximum energy
efficiency possible with the performance suitable for driving internal
circuit nodes of no more than 2pF load. Table 1 shows the simulation
results of the inverter-based Op-Amp under three different supply
voltages.

T ABLE 1: SIMULATION RESULTS OF T HREE INVERTER O P -AMP S

Designed Supply 700mV 900mV 1.1V

Voltage
DC Gain 46.22dB 48.36dB 47.9dB
Load 1.8pF 6pF 15pF
GBW 463.9kHz 2.408M Hz 3.94M Hz
FIGURE 2. INVERTER OP -A MP WITH T AILS
Overall DC
207.6nA 4.157µA 20.56µA
Current
The proposed topology shown in Figure 2 employs an active load
Power
consisting of four additional load inverters (M 2, M 3). The innermost 145.32nW 3.741µW 22.616µW
Consumption
pair of these inverters is connected in a cross-coupled configuration,
while the outer pair of inverters is diode-connected as shown in Offset Voltage 2.273mV 2.167mV 2.443mV
Figure 3. The cross coupled pair provides positive feedback and Input Referred
25.524µV 6.428µV 3.5µV
therefore a negative resistance of -2/gm3. The diode connected pair Noise
provides an equal, yet positive resistance of 2/gm2. CM RR 124.397dB 153.055dB 177.897dB
FOM 1 4022 3475 2874
FOM 2 5746 3861 2612
 To more effectively compare energy efficiency of the inverter-
based design with some of the existing published designs, we use
two different Figures of M erit (FOM s) for comparison.
Figure of Merit
When designing with higher supply voltages, designers have the
option of increasing input and tail transistor lengths, keeping the low-
current properties of the topology. Again, this approach can be
advantageous when the application does not require a high
bandwidth amplifier.

The first FOM we use is defined as: Design Comparison

GBW ( MHz )  CL  pF 
FOM1 
I (mA)
This FOM focuses on return-on-driving-current. It does not
directly measure the impact of supply voltage scaling. If comparisons
are made on circuits operating on the same supply voltage, this FOM
gives an accurate comparison. Otherwise, it tends to penalize designs
with lower supply voltages.
To compensate for the impact of supply voltage, the second FOM
is defined as:
GBW ( MHz )  CL  pF 
FOM 2 
P(mW )
The second FOM is similar to the first, except that total power is
used to measure its return on performance and overall driving
strength.
TOPOLOGY SCALABILITY AND FLEXIBILITY
The primary advantage with our proposed topology is the
scalability (overall number in a system) in terms of both power and
area, without a significant compromise in performance.
This topology can be used at higher voltage supplies, and even
outside the sub-threshold region. As supply voltage increases, the
inverter transistors tend to operate less deep into the sub-threshold
region, or if supply voltage is raised significantly high, in the
saturation region. Higher supply voltages, and in turn, higher
currents, tend to have a positive effect on the bandwidth of the
amplifier; however, this positive effect isn’t significant enough to
completely cancel out the effect of the increased overall current on
the circuit’s FOM .
We would like to compare the proposed design in the context of a
wide range of existing designs from simple common source
amplifiers, to telescopic amplifiers, to traditional M iller compensated
amplifiers, and to the more advanced three-stage amplifiers. Simple
or folded cascode operational amplifier designs typically can achieve
a FOM of 200-300[1, 2]; telescopic amplifiers typically have a
higher FOM around 500-700; traditional M iller compensated two-
stage amplifiers achieve a FOM of around 1000. State-of-the-art
three-stage M iller compensated amplifiers can achieve a FOM in the
3000-5000 range, and even over 10,000. [4, 5] As stated previously,
these larger three stage M iller amplifiers require complex
stabilization and compensation schemes, and can be significantly
large on silicon.
Table 2 shows the comparison of the amplifiers in this work to
various types of operational amplifiers. The table includes all
parameters necessary for figure of merit calculation, as well as both
the power and current based figures of merit.
M any of the existing amplifier topologies listed in Table 2 consist
of multiple stages, and employ complex stabilization schemes. These
amplifiers are generally designed to have a high bandwidth and drive
large capacitive loads. Due to its current-starving nature, the inverter-
based amplifiers are more suitable for smaller loads and less
stringent settling time requirements. Therefore, low power bio-
applications will be able to take the full advantage of the design.
Trading for higher power consumption and lower FOM s, the
inverter-based designs can be configured with higher supply voltage
to drive larger loads as shown in Table 2. Even with the lower FOM
associated with the inverter based design at 1.1V supply voltage, its
FOM still surpasses some of the more complex designs.

T ABLE 2: COMP ARISON O F VARIOUS AMP LIFIER DESIGNS

Existing Designs Amplifier Type Process CL(pF) GBW(M Hz) Power(W@VDD) FOM 1 FOM 2
TSEFC[3] 3-Stage M iller Comp. 0.35µm 500 1.4 225@1.5 4666.5 3111
SM CFC[4] 3-Stage M iller Comp. 0.35µm 150 1.6 21@1.5 17143 11430
M NM C[6] M ultipath Nested M iller bipolar 100 100 76000@8 1056 132
Comp.
NGCC[7] M ultistage Nested G m -C 2µm 20 0.61 680@2 36 18
Comp.
NM CFNR[8] Nested M iller Comp. 0.8µm 100 1.8 406@2 886 443
DFCFC[10] 3-Stage w/Active Feedback 0.8µm 100 2.6 420@2 1238 619
Freq. Comp.
AFFC[11] 3-Stage w/Active Feedback 0.6µm 100 5.5 250@1.5 330 220
Freq. Comp.
DLPC[12] Dual Path, Dual-Loop Parallel 0.6µm 120 7 330@1.5 3817.5 2545
Comp.
ACBCF[13] 3-Stage AC Boosting Comp. 0.35µm 500 1.9 324@2 5864 2932
700mV supply, Inverter-Based 0.18µm 1.8 0.4639 0.14532@0.7 4022 5746
Inverter-based
900mV supply, Inverter-Based 0.18µm 6 2.408 3.741@0.9 3475 3861
Inverter-based
1.1V supply, Inverter-Based 0.18µm 15 3.94 22.616@1.1 2874 2612
Inverter-based
 CONCLUSION
In this paper, a fully -differential inverter-based amplifier
topology with the current starving feature has been evaluated. While
the idea of inverter based amplifiers is not conceptually novel, the
idea of better controlling the current through the inverters using the
concept of current starving for low power applications, as well as
better CM RR and common-mode control makes the concept of
inverter-based amplifiers more practical in real applications,
particularly for applications for low power and low supply voltages.
Simple modifications or considerations during the design phase can
considerably increase the circuit’s usability. The concept of self-
cascoded transistors can be applied to the tail transistors to further
increase the benefits of increased impedance, such as additional
current starvation and added common-mode noise and signal
rejection while not giving up too much headroom. The overall size of
the transistors in the input inverter pair can be increased, allowing
this amplifier to be used in applications requiring a low-offset, low-
noise op-amp. Tail transistor width, as well as input inverter pair
width can be increased, allowing higher current flow, making this
topology useable in applications requiring a high bandwidth.
The most advantageous principle of this topology is its simplicity.
As the task of designing low-voltage high gain amplifiers in sub-µm
digital processes is becoming more complicated for designers, this
proves to be a simple circuit to design and optimize. This topology
efficiently provides a significant gain for a single-stage amplifier,
and can be used in many configurations, including both continuous
time and switched-capacitor circuitry.
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