3232 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO.
9, SEPTEMBER 2011
Fig. 2. Average errors per harmonic by experiment compared against simula-
tion results and the theoretical maximum for measurement uncertainty.
C. Discussion
Hardware resources used in the implementation of the DSM block
are pretty modest compared with state-of-the-art technology. In future
research, it would be interesting to investigate what would be the
results of measurement if the sampling frequency of an A/D converter
is drastically increased (e.g., 1 MHz) and if the number of measured
harmonics is increased, although we can assume what the result would
be according to (5). Actual A/D and FPGA chips allow such imple-
mentation, and a theoretically developed formula for an measurement
uncertainty limit indicates the possibility of a significant improvement
of measuring system accuracy and noise rejection.
IV. C ONCLUSION
The research described in this paper has evaluated one implementa-
tion of DSM of nonstationary signals as follows.
1) The simulations and experiments show well agreement with the
developed formula for measurement uncertainty limit.
2) This limit is dependent on the number of samples over a mea-
surement interval, which is determined by the sampling rate
of an A/D converter inside a DSM block, allowing designers
to choose A/D converters with lower resolutions and faster
sampling rates for achieving measurement that is more accurate
and more robust to noise.
R EFERENCES
[1] V. Vujičić, S. Milovancev, M. Pešaljević, D. Pejić, and I. Župunski, “Low
frequency stochastic true RMS instrument,” IEEE Trans. Instrum. Meas.,
vol. 48, no. 2, pp. 467–470, Apr. 1999.
[2] D. Pejic and V. Vujicic, “Accuracy limit of high-precision stochastic Watt-
hour meter,” IEEE Trans. Instrum. Meas., vol. 49, no. 3, pp. 617–620,
Jun. 2000.
[3] V. Vujičić, “Generalized low frequency stochastic true RMS instru-
ment,” IEEE Trans. Instrum. Meas., vol. 50, no. 5, pp. 1089–1092,
Oct. 2001.
[4] B. Santrać, M. A. Sokola, Z. Mitrović, I. Župunski, and V. Vujiˇić, “A
novel method for stochastic measurement of harmonics at low signal-to-
noise ratio,” IEEE Trans. Instrum. Meas., vol. 58, no. 10, pp. 3434–3441,
Oct. 2009.
[5] V. Pjevalica and V. Vujičić, “Further generalization of the low-frequency
true-RMS instrument,” IEEE Trans. Instrum. Meas., vol. 59, no. 3,
pp. 736–744, Mar. 2010.
[6] S. W. Smith, “Chapter 8: The discrete Fourier transform,” in The Scientist
and Engineer’s Guide to Digital Signal Processing, 2nd ed. San Diego,
CA: California Tech. Publ., 1999.
[7] S. M. Kay, Fundamentals of Statistical Signal Processing, Volume I: Es-
timation Theory, 1st ed. Englewood Cliffs, NJ: Prentice-Hall PTR, 1993,
pp. 27–82.
0018-9456/$26.00 © 2011 IEEE
[8] J. D. Bronzino, “Principles of electroencephalography,” in Biomedical
Engineering Handbook, J. D. Bronzino, Ed., 2nd ed. New York: CRC
Press LLC, 2000.
[9] J. G. Webster, Medical Instrumentation Application and Design.
New York: Wiley, 1998.
[10] M. Abeles and M. Goldstein, “Multispike train analysis,” Proc. IEEE,
vol. 65, no. 5, pp. 762–773, May 1977.
CMOS Voltage-to-Frequency Converter
With Temperature Drift Compensation
M. R. Valero, S. Celma, Member, IEEE, B. Calvo, Member, IEEE,
and N. Medrano, Member, IEEE
Abstract—This paper presents a new complementary metal–oxide–
semiconductor (CMOS) differential voltage-to-frequency converter (VFC)
suitable for sensor signal conditioning. Designed in a low-cost 0.18-μm
CMOS process, the proposed VFC consumes less than 0.4 mW at a 1.8-V
supply. For a differential input range of 0–1.2 V, output frequency varies
from 0.1 to 1.1 MHz with a linearity error of less than 0.4%. A new
temperature compensation technique keeps the gain error below 2.4% over
the whole frequency span for a range of −20 ◦ C− + 120 ◦ C.
Index Terms—Analog circuits, complementary metal–oxide–
semiconductor (CMOS) analog integrated circuits, integrated circuits,
signal processing, voltage–frequency conversion.
I. I NTRODUCTION
Analogue-to-digital converters with frequency output (e.g., quasi-
digital converters) are steadily superseding sensor signal digitalization
in smart sensor systems since a frequency signal offers high noise
immunity and can straight interface a microcontroller, which then
performs the digitalization [1].
A major requirement in the implementation of low-cost on-
chip solutions is compatibility with complementary metal–oxide–
semiconductor (CMOS) technology. This has increased the demand for
low-voltage design. Low-power and area consumption architectures
are also becoming almost mandatory, particularly in the market for
portables such as wireless sensor networks (WSNs).
Various voltage-to-frequency converters (VFCs) have been reported
up to date [2], [3]. Some integrated bipolar [4] and most of recently
reported CMOS VFCs are mainly based on an input voltage-to-current
converter followed by a current-to-frequency converter operating in
single-input mode and without temperature compensation [5], [6].
Manuscript received August 23, 2010; revised October 20, 2010; accepted
October 21, 2010. Date of publication April 15, 2011; date of current version
August 10, 2011. This work was supported in part by the Ministry of Science
and Innovation of Spain under Grant RYC-2008-03185, Grant PET2007-0336,
Grant PET2008-0021, and Grant TEC2009-09175; by the General Delegation
of Aragon–La Caixa under Grant GA-LC-039/2008 and Grant GA-LC-033/
2009; by the General Delegation of Aragon under Grant PI 113/09; and by the
Aragon Institute of Engineering Research Fellowship Program. The Associate
Editor coordinating the review process for this paper was Dr. Daryl Beetner.
The authors are with the Electronic Design Group, Department of Electronic
Engineering and Communications, Aragon Institute of Engineering Research,
University of Zaragoza, 50009 Zaragoza, Spain (e-mail: mrvalero@unizar.es;
scelma@unizar.es; becalvo@unizar.es; nmedrano@unizar.es).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2011.2128690
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 9, SEPTEMBER 2011
Fig. 1. Conceptual scheme of the proposed VFC.
However, differential signal processing is preferable when seeking
to overcome external common-mode noise, and temperature compen-
sation is necessary to reduce the strong temperature dependence of
output frequency.
II. CMOS VFC
A. VFC Architecture
In response, this paper presents a differential CMOS VFC suitable
for WSN applications. As shown in Fig. 1, this VFC consists of an
instrumentation amplifier (IA) with gain G, a MOS resistive circuit
(MRC) as a voltage-to-current converter, and an operational amplifier
(opamp)-C integrator driven by a voltage window comparator (VWC)
as a current-to-frequency converter.
The IA is a highly linear CMOS programmable gain amplifier [7].
The opamp is a conventional two-stage scheme with Miller compen-
sation providing a differential gain of 85 dB and a unity-gain frequency
of 113 MHz with a phase margin of 60◦ .
The MRC, formed by four matched p-channel MOS operating simi-
lar to (positive or negative) differential linear resistance, translates the
difference between the input voltages V1 = VCM + Vin /2 and V2 =
VCM − Vin /2 into the linear differential current I1 − I2 given by
W
I1 − I2 = μCox (VG1 − VG2 ) · (V1 − V2 ) (1)
L B. Temperature Drift Compensation
where W/L is the MRC transistor size, VG1 and VG2 are the applied
gate voltages, and μ and Cox have their usual meaning [8].
This current charges and discharges, depending on the sign of the
gate control signal VG = VG1 − VG2 , the integrating capacitor C =
5 pF between the limits VL = 0.8 V and VH = 1.2 V of the VWC.
The VWC consists of two simple differential pairs followed by
digital inverters, which work alternately depending on the state of an
enabled terminal to reduce power consumption.
The output voltages VCL and VCH feed an RS flip-flop, which grants
digital outputs SUP and SDW .
The polarity of the integrating current is controlled through SUP
and SDW , which drive the gates of the differential pair transistors
M1 − M2 , assuming that Vin > 0 during all the conversion cycle.
While SUP = ‘0’/SDW = ‘1’, M1 is “on,” and M2 is “off,” setting
VG1 = IB · RTH = 10 μA · 30 kΩ = 0.3 V and VG2 = 0 V. There-
fore, VG > 0, and the voltage in V0 increases until it reaches VH . The
outputs then flip to SUP = ‘1’/SDW = ‘0’, setting VG1 = 0 V and
VG2 = IB · RTH = 0.3 V, i.e., VG < 0. Now, V0 decreases until it
reaches VL . Then, SUP changes from “1” to “0” (and SDW from “0” to
“1”), which sets VG < 0, and a new cycle starts. In this way, a repeated
3233
Fig. 2. Output frequency f0 versus differential input voltage Vin (for −20 ◦ C,
25 ◦ C, and 120 ◦ C) with and without temperature drift compensation.
TABLE I
C OMPARISON OF CMOS VFCs
charge and discharge loop is built, with the frequency of oscillation f0
given by
GμCox W |VG1 − VG2 | G
fo = (V1 − V2 ) = Vin (2)
2LC(VH − VL ) 2RC(VH − VL )
where R is the absolute value of the differential resistance of the MRC,
which is inversely proportional to the hole mobility μ, i.e., a parameter
that introduces the main temperature dependence on output frequency.
The key idea of the proposed temperature compensation technique is
to introduce the temperature dependence in the gate voltages VG1 and
VG2 , with the intention that VG = VG1 − VG2 will provide the suitable
thermal coefficient TCTH in order to achieve an overall temperature-
independent output frequency.
This is carried out by implementing RTH as the series connection
of the two resistors RA and RB .
If RA and RB possess the different thermal coefficients TCA and
TCB , we can combine them to obtain the equivalent series resis-
tor RTH = RA + RB with the thermal coefficient TCTH = TCA ·
(β/(1 + β)) + TCB · (1/(1 + β)), where β = RA /RB is the rela-
tive size of RA and RB at room temperature [9].
Therefore, with the suitable resistor values of RA and RB , RTH
makes voltage VG = IB · RTH present the adequate thermal coeffi-
cient to compensate for the temperature drift of the whole circuit.
III. E XPERIMENTAL R ESULTS
The VFC has been fabricated in standard 0.18-μm CMOS technol-
ogy with a single supply voltage of 1.8 V. The common-mode voltage
3234 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 9, SEPTEMBER 2011
VCM is set to 1.2 V; thus, the differential input signal range Vin goes
from 0 to 1.2 V.
The biasing and threshold voltages VH and VL are generated from
a bandgap reference. RA is an n-well resistor, whereas RB is a
p-diffusion resistor.
For G = 1, the frequency output goes from 0.1 to 1.1 MHz, with a
linearity error of 0.4%. To validate the feasibility of the temperature
compensation circuit, the frequency output versus differential input
voltage, with and without compensation, for −20 ◦ C, 25 ◦ C, and
120 ◦ C is shown in Fig. 2.
The gain error versus temperature, which is calculated as (fOT −
fO, T 0 )/Δf (where fO, T 0 is the value of the output frequency at room
temperature (i.e., 25 ◦ C), fOT is the output frequency at temperature
T , and Δf is the output frequency span), in the worst case (120 ◦ C) is
reduced from 44% to 2.4%. Power consumption is kept below 0.4 mW
over all the frequency range.
IV. C ONCLUSION
A new compact temperature-compensated CMOS differential VFC
suitable for WSN applications is proposed.
Compared with previous CMOS realizations [5], [6], Table I shows
how this circuit is performance competitive in terms of sensitivity and
linearity, with a very low temperature drift.
Sensitivity and start frequency can be easily changed by adjusting
the gain and the offset of the IA, respectively.
R EFERENCES
[1] G. Meijer, Smart Sensor Systems. Chichester, U.K.: Wiley, 2008.
[2] K. Kondo and K. Watanabe, “An integration type high-speed analog-to-
digital converter,” IEEE Trans. Instrum. Meas., vol. 39, no. 1, pp. 61–65,
Feb. 1990.
[3] F. N. Trofimenkoff and F. Sabouri, “A square-rooting voltage-to-
frequency converter,” IEEE Trans. Instrum. Meas., vol. 46, no. 5,
pp. 1208–1211, Oct. 1997.
[4] D. McDonagh and K. I. Arshak, “Stable differential voltage-to-frequency
converter with low supply voltage and frequency offset control,” IEEE
Trans. Instrum. Meas., vol. 47, no. 5, pp. 1335–1361, Oct. 1998.
[5] C. -C. Wang, T. -J. Lee, C. -C. Li, and R. Hu, “An all-MOS high-
linearity voltage-to-frequency converter chip with 520-kHz/V sensivity,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 744–747,
Aug. 2006.
[6] P. I. Yakimov, E. D. Manolov, and M. H. Hristov, “Design and implemen-
tation of a V/F converter using FPAA,” in Proc. 27th Int. Spring Semin.
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[7] M. T. Sanz, S. Celma, and B. Calvo, “Using MOS current dividers for
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Appl., vol. 36, no. 4, pp. 397–408, Jun. 2008.
[8] Z. Czarnul, “Novel MOS resistive circuit for synthesis of fully integrated
continuous-time filters,” IEEE Trans. Circuits Syst., vol. CAS-33, no. 7,
pp. 718–721, Jul. 1986.
[9] B. R. Gregoire and U.-K. Moon, “Process-independent resistor
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0018-9456/$26.00 © 2011 IEEE
Data Acquisition System Based on Subsampling for Testing
Wideband Multistandard Receivers
J. R. G. Oya, F. Muñoz, A. Torralba, A. Jurado,
A. J. Garrido, and J. Baños
Abstract—In this paper, a data acquisition module meeting the speci-
fications of a wideband multistandard receiver test system is presented.
It provides a high resolution over large bandwidth with only a low-jitter
wideband sample-and-hold and an intermediate frequency analog-to-
digital converter by means of subsampling. Using commercial devices on a
multilayer printed circuit board, experimental results showed more than a
resolution of 8 b for a signal bandwidth of 20 MHz with a center frequency
of up to 4GHz, which is enough to cover the requirements of test systems
for most of present wireless communication standards.
Index Terms—Analog-to-digital converter (ADC), jitter noise,
sample-and-hold (S&H), software-defined radio (SDR), thermal noise.
I. I NTRODUCTION
Due to the widespread acceptance of wireless technologies, there is
a large number of different communication standards, i.e., each one
with a specific set of specifications, such as carrier frequency and
bandwidth. As a consequence, there is a trend to design transceivers
for multiple standards in different frequency bands [1], [2]. A similar
problem arises in the test industry, where preferably low-cost accurate
multistandard receivers are an essential element.
Concerning the topology of a multistandard receiver, the position
of an analog-to-digital converter (ADC) in a front-end chain is crucial
as shifting analog blocks (i.e., filters, mixers, and amplifiers) to the
digital domain increases the flexibility of a receiver. The extreme case
is known as the software-defined radio (SDR) paradigm [3], where
an ADC is placed right behind an antenna to directly digitize radio-
frequency (RF) signals. For present communication standards, this
approach imposes such high requirements on ADCs that it is beyond
the state of the art of present technology [4], where an ADC is limited
to 7–8 b for a sampling rate of 3 GS/s.
Different receiver architectures have been proposed to overcome
this problem, such as direct conversion [5], low intermediate frequency
(IF) [6], and subsampling [7], [8]. In subsampling receivers, an RF
signal is sampled using frequencies lower than the maximum input
frequency but larger than two times the signal bandwidth. One of
the low-frequency replicas of the sampling product, which contains
a baseband signal, is then directly digitized.
Subsampling receivers use a sample-and-hold (S&H) to produce
low-frequency replicas of RF signals based on a passband sampling
Manuscript received November 5, 2010; revised January 10, 2011; accepted
February 10, 2011. Date of publication April 7, 2011; date of current version
August 10, 2011. This work was supported in part by TelMAX Project and
in part by the Ministry of Science and Innovation of Spain Centre for the
Development of Industrial Technology through the CENIT–INGENIO 2010
Program. The Associate Editor coordinating the review process for this paper
was Dr. R. Pintelon.
J. R. G. Oya, F. Muñoz, and A. Torralba are with the Department of
Electronics Engineering, University of Seville, 41092 Seville, Spain (e-mail:
oya@gte.esi.us.es; fmunoz@gte.esi.us.es; torralba@us.es).
A. Jurado, A. J. Garrido, and J. Baños are with the AT4 Wireless, 29590
Málaga, Spain (e-mail: ajdiez@at4wireless.com; ajgarrido@at4wireless.com;
jbanos@at4wireless.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2011.2128710