Analog Integrated Circuits and Signal Processing, 47, 65–71, 2006


c 2006 Springer Science + Business Media, Inc. Manufactured in The Netherlands.

New Σ-Δ Voltage to Frequency Converter Analysis and Applications

MILAN STORK
Department of Applied Electronics, University of West Bohemia, Plzen, Czech Republic
E-mail: stork@kae.zcu.cz

Received October 22, 2002; Revised June 2, 2004; Accepted June 11, 2004

Abstract. Voltage to frequency converter (VFC) is an oscillator whose frequency is linearly proportional to
control voltage. There are two common VFC architectures: the current steering multivibrator and the charge-balance
VFC. For higher linearity, the charge-balancing method is preferred. The charge balanced VFC may be made in
asynchronous or synchronous (clocked) forms. The synchronous charge balanced VFC or “sigma delta” Sigma-Delta
VFC (SVFC) is used when output pulses are synchronized to a clock. The charge balance VFC is more complex, more
demanding in its supply voltage and current requirements, and more accurate. It is capable of 16 to18 bit linearity.
In this paper, the new SVFC (NSVFC) is described. This NSVFC works similarly as conventional SVFC but it has
a pure tone on output (for constant input voltage). Therefore, it is possible to measure the period of NSVFC output
(this does not work for SVFC).

Key Words: voltage to frequency converter, Sigma-Delta converter, phase locked loop, frequency synthesizer

1. Introduction The output frequency f O is given by (1):

In recent years, VFC have become quite popular due

to their low cost and application versatility in vari-
ety of electronic control and measurement systems.
With a good quality VFC, this circuit will match the
performance of many commercial A/D converters. Its
only disadvantage is relatively slow conversion time.
- modulator [1] can be used for synchronous VFC
(SVFC). In SVFC charge balance pulse length is now
defined by two successive edges of the external clock. If
this clock has low jitter the charge will be defined very
accurately. The output pulse will also be synchronous
with the clock. SVFCs of this type are capable of up to
18-bit linearity and they have excellent temperature sta-
bility [2], but is not pure tone for constant input voltage
(output pulses are not equally spaced). Figure 1 shows
the waveforms of commercial - SVFC and NSVFC.
From Fig. 1(c) can be seen that output periods are not
the same, but they have changed between 3 and 4 clock
cycles. This disadvantage was taken away in NSVFC1
and NSVFC2.
2. New Synchronous VFC
In Fig. 2 is NSVFC1 block diagram. Only one-shot is
added and connected to comparator output. Figure 1
shows waveforms of this NSVFC1. Number of pulses
is same for usual - SVFC [2] and NSVFC (NSVFC1
and NSVFC2).
f O = f CLK (1 − Vi /VR )/2 [Hz, V] (1)
where Vi is input voltage, VR is reference voltage and
f CLK is clock frequency. It is important to note, that for
NSVFC1 this equation is limited for Vimin given by (2).
The minimal input voltage value Vimin :
Vimin > 2 f CLK VR tdC (for NSVFC1) [V, Hz, sec] (2)
where tdC is comparator time delay. E.g. for f CLK = 10
kHz, VR = 5 V and tdC = 200 ns, the minimal value
Vimin > 0.02 V.
3. NSVFC Output Frequency Evaluation
The key to - modulator is the integrator. At each
conversion, the integrator keeps a running total of its
previous output and its current input. The output from
the integrator is feed to 1-bit analog/digital converter
(ADC). This is simply a comparator with its reference
input at a level of half the input range, 0 V in this case.
The ADC output feeds a 1-bit digital/analog converter
(DAC) which has output levels equal +VR or −VR . A
summing amplifier completes the loop by summing the
current input signal and the previous sample DAC out-
put. The aim of the feedback loop is to try to maintain
the average output of the integrator at the comparator
66 Stork

Fig. 1. Waveforms of NSVFC. (a) integrator output, (b) one shot

output, (c) D-flip flop output. Vi = 1.8 V, V R = 4 V, period of one
shot is 3.636 Tclk Fig. 4. Detailed waveforms of the integrator, D
flip-flop SVFC and one shot NSVFC outputs, n = 2 in this figure
(nTclk = 2Tclk ).

Fig. 3. NSVFC waveforms and equivalent period time diagram (top)

and detailed waveforms of the integrator, D flip-flop SVFC and one
shot NSVFC outputs, n = 2 in this figure (nTclk = 2Tclk ).

Fig. 2. NSVFC1-New - voltage to frequency converter  (n+1)Tclk

type1. Int.-integrator, Comp.—comparator, Vi —input voltage, V R — VL (k + 1) = VH (k) + C (Vi (t) − VR ) dt
reference voltage, D—flip flop, OS—one shot. Tclk
(7)

reference level, 0 V. Therefore: and for Vi (t) = Vi :


∞ 
∞
VL (k) + VH (k) = 0 (3) VH (k) = VL (k) + C(Vi + VR )Tclk (8)
k=1 k=1
VL (k + 1) = VH (k) + C(Vi − VR )nTclk (9)
where k = 1, 2, . . . ∞, and Vo1 (k) and Vo2 (k) are inte-
grator output voltage in k output frequency period, see Integrator output voltage change is given by:
Fig. 3. The NSVFC and equivalent period time diagram
is also shown in Fig. 3. C(Vi + VR )Tclk = C(Vi − VR )nTclk (10)
Change Va is given by (4):
where n must be an integer for SVFC. For NSVFC
 Tclk output is given by:
Va = C (Vi (t) + VR ) dt (4)
0
C(Vi + VR )Tclk = C(Vi − VR )mTclk (11)
and Vb is given by (5):
 where m is real for NSVFC. From (11) (VR > Vi ):
nTclk
Vb = C (Vi (t) − VR ) dt (5) Vi + VR
0 m= (12)
VR − Vi
where C is the integrator constant. The integrator output
is given by: and for SVFC, n is given by (13):
  
Tclk Vi + VR
VH (k) = VL (k) + C (Vi (t) + VR ) dt (6) n = ceil = ceil(m) (13)
0 VR − Vi
 New - Voltage to Frequency Converter Analysis and Applications 67

where Ceil(·)—Converts a numeric value to an inte-

ger by returning the smallest integer greater than or
equal to its argument. e.g., Ceil(9/3) = 3, Ceil(9.01/3)
= 4.

3.1. Output Frequency Evaluation for Ideal

NSVFC

For this ideal NSVFC it is supposed, that comparator

has a zero time delay and noise value voltage on second
comparator input is zero. Output period for NSVFC can
be determined from Fig. 3.
It is supposed, that VR > Vi , where VR is reference
voltage and Vi is input voltage. The VL (i) and VH (i) are
Fig. 4. Time diagram for real converter—output frequency evalua-
voltage at integrator output. tion.
The negative slope is C(VR − Vi ) while positive slope
is C(VR + Vi ) where C is the integrator time constant.
Moreover
−VL (k)
t1 = (14)
C(VR − Vi )

and time t2 is:

VH (k)
t2 = (15)
C(VR − Vi )

Also VH (k) − VL (k) = C(VR + Vi )Tclk . The period is

T0 = t1 + tclk + t2 , as a result

−VL (k) VH (k) Fig. 5. NSVFC2-Block diagram. Int.—integrator, Comp.—

To = + Tclk + comparator, Vi —input voltage, V R —reference voltage, VPM —input
C(VR − Vi ) C(VR − Vi )
voltage for phase modulation, D—flip flop, OS—one shot, AND,
VR + Vi VR OR—log. function.
= + Tclk = 2Tclk (16)
VR − Vi VR − Vi

The output frequency f 0 is:

condition, output pulse is generated only when voltage
on integrator output is lower then voltage on second
f 0 = f clk (VR − Vi )/2VR (17)
comparator input—leading edge of integrator output).
The additional logic is used for this purpose. The block
where f clk = 1/Tclk diagram of this NSVFC2 is shown in Fig. 5.
From (17) is shown, that ideal NSVFC output fre- Output period T0 from Fig. 4 is given by:
quency is linearly dependent on input voltage ( f clk and
VR are constants).
Te1 = Tclk [n(k) − tz (k) + te (k)] (18)

3.2. Output Frequency Evaluation for Real NSVFC

For Tclk = 1, Vi  VR output period 1 Te1 is given by:
In this part, error caused by comparator delay, com-
parator hysteresis or voltage change on second com-
1
Te1 = ceil (VH (k)/(VR − Vi )) − VH (k)/(VR − Vi )
parator input is described. This error is displayed on +|VL (k)/(VR + Vi )| (19)
Fig. 4 and is sign by X point. The error can arise es-
pecially when input voltage Vi ≈ 0. The error occur In (19) ceil(VH (k)/(VR − Vi )) = 2 and VH (k) ≈ VR
when 2 clock cycles are need for VL (k) to VH (k + 1) and |VL (k)| ≈ VR for Vi ≈ 0. Hence:
transition. In this case, this must be detected and output
pulse is generated, when integrator output voltage on
one comparator input is greater than voltage on second
1
Te1 = 2 − VR /(VR − Vi ) + VR /(VR + Vi )
comparator input (it is important to note, that in ideal ≈ 2(1 − Vi /VR ) (20)
68 Stork

For Tclk = 1, the output period 1 TPM is given by (24):

1
TPM = n(k + 1) − tz (k + 1) + 1 + tzPM (k + 2) (24)

But tzPM (k + 2) is:

tzPM (k + 2) = (VH (k + 2) − VPM )/(VR − Vi ) (25)

where VPM is voltage on second comparator input.

After some mathematics manipulation the 1 TPM is:
1
TPM = (2VR − VPM )/(VR − Vi ) = 2VR /(VR − Vi )
Fig. 6. Time diagram for phase modulation evaluation. −VPM /(VR − Vi ) = 1 To − 1 TPM (26)

hence ϕ is given by (27):

Similarly the output period 1 Te2 is given by:
1
Te2 = 2 − te (k) + VR /(VR − Vi )
= 2 − VR /(VR + Vi ) + VR /(VR + Vi )
≈ 2(1 + Vi /VR )
Equations (20) and (21) for Tclk are simplified to:
Te1 ≈ 2Tclk (1 − Vi /VR )
Te2 ≈ 2Tclk (1 + Vi /VR )
4. Phase Modulation
The NSVFC2 has phase modulation capabilities. When
the modulating voltage VPM is applied to second com-
parator input, see Fig. 5, the output signal is phase mod-
ulated. The VPM < VR must be satisfied for modulation
voltage. The time diagram for phase modulation com-
puting is shown on Fig. 6.
ϕ = π VPM /VR [rad, V] (27)
From (27) is shown, that NSVFC2 phase change is lin-
early dependent on input voltage VPM .
(21)
5. Simulation Results
Simulations were performed to validate the results of
(22) mathematics analysis. These results were obtained pro-
gramming of SVFC and NSVFC equations (Fig. 1). The
(23)
SVFC, NSVFC1 and NSVFC2 has also been simulated
in system level by SIMULINK (MATLAB). The block
diagram of this simulation is shown in Fig. 7. Figure 8
shows the frequency spectrum of the output waveforms.
Figure 9 shows the waveforms with errors, which are
corrected by additional logic used in NSVFC2.
6. Experimental Results
Commercially produced SVFC AD7741 and AD7742
[2] were tested and also NSVFC1 was realized

Fig. 7. NSVFC2 block diagram for simulation.

 New - Voltage to Frequency Converter Analysis and Applications 69

Fig. 10. Experimental NSVFC1 simplified circuit diagram.

Fig. 8. Frequency spectrum of NSVFC.

and tested [4–7]. In Fig. 10, experimentally realized

NSVFC1 simplified circuit diagram is shown [3]. The
voltage/frequency characteristic and frequency spec-
trum was measured. In Fig. 11, graph of measured volt-
age/frequency characteristic of experimental NSVFC1
is shown. In Table 1, some measured values Vi a f o are
displayed. In so far used type of SVFC, since the output
pulses are synchronized to a clock, they are not equally
spaced. This need not affect the user of a SVFC for A/D Fig. 11. Graph of voltage/frequency characteristic of realized ex-
conversion, but it does prevent its use as a precision os- perimental NSVFC1.
cillator. Despite this disadvantage the improvement in
performance makes the SVFC ideal for the majority of
high-resolution VFC applications. In Fig. 14 the oscilloscope photograph of the inte-
In Fig. 12, the frequency spectrum of SVFC is shown grator and one shot output of NSVFC1 is shown during
and in Fig. 13, the spectrum of NSVFC1 is displayed. the error function (missing pulse) for Vi = 0.032 V. In
From Fig. 13 can be seen, that spurious spectral lines NSVFC1 this error is not corrected, but in NSVFC2 is
are rejected. corrected by additional logic.

Fig. 9. Simulated waveforms (with errors). Errors are corrected by logic, added to NSVFC2.
70 Stork

Table 1. Some measured values Vi and f o of realized experimental NSVFC1.

Vi 0.00 0.10 0.50 1.01 1.20 1.41 1.61 2.01 2.51 3.01 V
fo 2.84 2.73 2.53 2.28 2.02 2.84 2.73 2.53 2.28 2.02 kHz

Fig. 15. The block diagram of experimental fractional PLL synthe-

sizer, fr —ref. frequency, f o —output frequency, Vi —control voltage,
GEN—generator, PD—phase detector, LPF—lowpass filter, VCO—
voltage controlled oscillator.

Fig. 12. The frequency spectrum of traditional - V / f converter.

tegral multiples of the reference signal only. Therefore
reference frequency can be higher than the step size and
overall division can be reduced. The main motive for
using fractional PLL architecture is to improve phase
noise; however, increasing reference frequency makes it
possible to improve switching speed as well by increas-
ing loop bandwidth. With NSVFC, fractional frequency
synthesizer can be simply realized [5, 7].
The block diagram of experimental fractional PLL
synthesizer is shown in Fig. 15. If the VCO is locked to
the reference frequency, then:

f d = fr (28)
Fig. 13. The frequency spectrum of new, modified - V / f con-
verter (NSVFC1).
where is fr reference frequency and f d is frequency on
the output of NSVFC. Because is given by (29):

f d = f o (1 − Vi /VR )/2 (29)

where f o is frequency of VCO. After substituting for

f d from (29) into Eq. (28), frequency of VCO is given
by (30):

f o = 2 fr 1/(1 − Vi /VR ) (30)

The VCO frequency f o can be changed according Eq.

Fig. 14. The oscilloscope photograph of the integrator and one shot
output of NSVFC1, Error function of the NSVFC1 is shown (missing
(30) by means of changing Vi .
pulse) for Vi = 0.032 V. The fractional frequency synthesizer using NSVFC
was build. The frequency spectrum was the same as in
Fig. 13.
7. NSVFC as a Building Block for Fractional
Phase Locked Loop Frequency Synthesizer 8. Conclusion

The fractional frequency synthesizer is similar to the A very detailed look at the concept of new type sigma-
divide-by-N phase locked loop (PLL), however, with delta voltage to frequency converter circuit has been
assistance of the NSVFC, the output frequency of the presented in this article. A prototype system was con-
voltage-controlled oscillator (VCO) is not restricted in- structed to verify operation of the converter. Analysis,
 New - Voltage to Frequency Converter Analysis and Applications
simulation and prototype of new type voltage to fre-
quency converter were described. The NSVFC simula-
tion results and measured results were compared. From
analysis, simulation and measured results can be seen
very good agreement from different point of view. It was
pointed out that this new converter has better properties
than other synchronous types of VFC. This main disad-
vantage of SVF described above was removed in new
type of NSVFC (Fig. 2 NSVFC1 and Fig. 5 NSVFC2).
The applications NSVFC for phase modulation and
fractional phase locked loop frequency synthesizer were
also presented. This type of voltage/frequency converter
can be used for high output frequency (similarly as Di-
rect Digital Synthesis or - converter), but it has pulse
output.
Because output pulses are equally spaced in NSVFC
(some spurious spectral lines are rejected), this device
can be used also as fractional divider.
Acknowledgment
This research work has been supported by Depart-
ment of Applied Electronics and Telecommunications,
University of West Bohemia, Plzen, Czech Republic
and partly also by Spezial-Electronic (Maxim IC’s).
References
1. S. Park,“Principles of sigma-delta modulation for analog-to-digital
converters.” Motorola Application Notes APR8, 1999.
2. Single and Multichannel, Synchronous Voltage-to-Frequency
Converters, AD7741, AD7742, Analog Devices 1999.
3. Analog Multiplexers/Switches, Maxim 1995 New Releases Data
Book, vol. IV.
4. M. Stork, Modified - voltage to frequency converter. 4-th in-
ternational conference on advanced A/D and D/A conversion tech-
71
niques and their applications. IMEKO TC-4, Prague, ISBN 80-01-
02540-3, pp. 211–214, 2002.
5. M. Stork, New fractional phase-locked loop frequency synthesizer
using a sigma-delta modulator. 14th international conference on
digital signal processing. DSP 2002, Santorini-Greece, ISBN 0-
7803-7503-3, vol. 1, pp. 367–370, 2002.
6. M. Stork, New - Voltage to Frequency Converter, The 9th IEEE
International Conference on Electronic Circuits and Systems. Pro-
ceedings, Dubrovnik, Croatia, ISBN 0-7803-7596-3, vol. II, pp.
631–634, 2002.
7. M. Stork, Voltage to frequency converter, 12th imeko tc4 interna-
tional symposium, electrical measurements and instrumentation,
zagreb, croatia. ISBN 953-96093-8-0, Proceedings Part 2, pp. 464–
467, 2002.
Milan Stork received the M.Sc. degree in electri-
cal engineering from the Technical University of Plzen,
Czech Republic at the department of electronics in 1974
and Ph.D. degree in automatic control systems at the
Czech Technical University in Prague in 1985. In 1997,
he became as Associate Professor at the Department of
Applied Electronics and Telecommunication, faculty of
electrical engineering on University of West Bohemia
in Plzen, Czech Republic. He has numerous journal
and conference publications. He is member of edito-
rial board magazine ”Physician and Technology”. His
research interest include analog/digital systems, signal
processing and biomedical engineering, especially car-
diopulmonary stress tests systems.