Yamaha Rx-A830 Full

AV RECEIVER
RX-A830 SERVICE MANUAL

Note:
When the DIGITAL P.C.B. or IC82 on DIGITAL (1) P.C.B. is replaced, this unit will display “Internal Error” and will
not operate properly. The model name MUST be written to the backup IC (EEPROM: IC82 on DIGITAL (1) P.C.B.) to
have proper operation. (For detailed procedure, refer to related Service News or Service Bulletin. Or contact your
local Yamaha representative.)
IMPORTANT NOTICE
This manual has been provided for the use of authorized Yamaha Retailers and their service personnel.
It has been assumed that basic service procedures inherent to the industry, and more specifically Yamaha Products, are already known
and understood by the users, and have therefore not been restated.
WARNING: Failure to follow appropriate service and safety procedures when servicing this product may result in personal injury,
destruction of expensive components, and failure of the product to perform as specified. For these reasons, we advise
all Yamaha product owners that any service required should be performed by an authorized Yamaha Retailer or the
appointed service representative.
IMPORTANT: The presentation or sale of this manual to any individual or firm does not constitute authorization, certification or
recognition of any applicable technical capabilities, or establish a principle-agent relationship of any form.
The data provided is believed to be accurate and applicable to the unit(s) indicated on the cover. The research, engineering, and service
departments of Yamaha are continually striving to improve Yamaha products. Modifications are, therefore, inevitable and specifications
are subject to change without notice or obligation to retrofit. Should any discrepancy appear to exist, please contact the distributor's
Service Division.
WARNING: Static discharges can destroy expensive components. Discharge any static electricity your body may have
accumulated by grounding yourself to the ground buss in the unit (heavy gauge black wires connect to this buss).
IMPORTANT: Turn the unit OFF during disassembly and part replacement. Recheck all work before you apply power to the unit.
■ CONTENTS
TO SERVICE PERSONNEL ............................................2 DISPLAY DATA .......................................................66–67
FRONT PANELS .............................................................3 IC DATA ...................................................................68–88
REAR PANELS ...........................................................4–6 PIN CONNECTION DIAGRAMS .............................89–91
REMOTE CONTROL PANELS .......................................7 BLOCK DIAGRAMS ................................................92–95
SPECIFICATIONS ..................................................... 8–12 WIRING DIAGRAMS ...............................................96–97
INTERNAL VIEW .......................................................... 13 PRINTED CIRCUIT BOARDS ............................... 98–113
SERVICE PRECAUTIONS ............................................ 13 SCHEMATIC DIAGRAMS ................................... 115–127
DISASSEMBLY PROCEDURES ............................. 14–17 REPLACEMENT PARTS LIST ............................ 129–143
RX-A830
UPDATING FIRMWARE .......................................... 18–20 REMOTE CONTROL ........................................... 144–146

SELF-DIAGNOSTIC FUNCTION ............................21–64 ADVANCED SETUP ............................................ 147–148
POWER AMPLIFIER ADJUSTMENT ............................65 FIRMWARE UPDATING PROCEDURE .............. 149–154
Copyright (c) Yamaha Corporation All rights reserved.

101269 This manual is copyrighted by Yamaha and may not be copied or
redistributed either in print or electronically without permission.
P.O.Box 1, Hamamatsu, Japan
'13.06
RX-A830
■ TO SERVICE PERSONNEL AC LEAKAGE

1. Critical Components Information WALL EQUIPMENT TESTER OR
Components having special characteristics are marked and OUTLET UNDER TEST EQUIVALENT
must be replaced with parts having specifications equal to those
originally installed.
2. Leakage Current Measurement (For 120V Models Only)
When service has been completed, it is imperative to verify
INSULATING
that all exposed conductive surfaces are properly insulated TABLE
from supply circuits.
• Meter impedance should be equivalent to 1500 ohms shunted • Leakage current must not exceed 0.5mA.
by 0.15 μF. • Be sure to test for leakage with the AC plug in both polarities.
For U model
“CAUTION”
“F3701: FOR CONTINUED PROTECTION AGAINST RISK OF FIRE, REPLACE ONLY WITH SAME TYPE 2A,
250V FUSE.”
“F3702: FOR CONTINUED PROTECTION AGAINST RISK OF FIRE, REPLACE ONLY WITH SAME TYPE 8A,
125V FUSE.”
For C model
CAUTION
F3701: REPLACE WITH SAME TYPE 2A, 250V FUSE.
F3702: REPLACE WITH SAME TYPE 8A, 125V FUSE.
ATTENTION
F3701: UTILISER UN FUSIBLE DE RECHANGE DE MÉME TYPE DE 2A, 250V.
F3702: UTILISER UN FUSIBLE DE RECHANGE DE MÉME TYPE DE 8A, 125V.
WARNING: CHEMICAL CONTENT NOTICE!

This product contains chemicals known to the State of California to cause cancer, or birth defects or other reproductive
harm.
DO NOT PLACE SOLDER, ELECTRICAL/ELECTRONIC OR PLASTIC COMPONENTS IN YOUR MOUTH FOR ANY REASON
WHATSOEVER!
Avoid prolonged, unprotected contact between solder and your skin! When soldering, do not inhale solder fumes or
expose eyes to solder/flux vapor!
If you come in contact with solder or components located inside the enclosure of this product, wash your hands before
handling food.
About lead free solder

All of the P.C.B.s installed in this unit and solder joints are soldered using the lead free solder.
Among some types of lead free solder currently available, it is recommended to use one of the following types for the
RX-A830
repair work.
• Sn + Ag + Cu (tin + silver + copper)
• Sn + Cu (tin + copper)
• Sn + Zn + Bi (tin + zinc + bismuth)
Caution:
As the melting point temperature of the lead free solder is about 30°C to 40°C (50°F to 70°F) higher than that of the lead
solder, be sure to use a soldering iron suitable to each solder.
2
RX-A830
■ FRONT PANELS
U, C, R, T, K, A, L, S models
B, G, F models
RX-A830
3
RX-A830
■ REAR PANELS
U, C models
R, S models
T model
RX-A830
4
RX-A830
K model
A model
B, G, F models
RX-A830
5
RX-A830
L model
RX-A830
6
RX-A830
■ REMOTE CONTROL PANELS

RAV505 RAV506 RAV507
(U, C models) (R, A, L, S models) (T, K, B, G, F models)
RX-A830
7
RX-A830
■ SPECIFICATIONS
■ Audio Section
Rated Output Power (Power Amp. Section) Total Harmonic Distortion (20 Hz to 20 kHz)
(1 kHz, 0.9 % THD) AV5 etc. (PURE DIRECT) to FRONT SP OUT
– 1 channel driven – 50 W/8 ohms ............................................................0.06 % or less
U, C, R, T, K, A, B, G, F, L, S models (8 ohms) PHONO (MM) to AV OUT (R, T, K, A, B, G, F, L, S models)

FRONT L/R ................................................................ 130 W/ch 1 V ............................................................................0.02 % or less
CENTER .......................................................................... 130 W Signal to Noise Ratio (IHF-A Network)
SURROUND L/R ........................................................ 130 W/ch
AV5 etc. (PURE DIRECT) to SP OUT
SURROUND BACK L/R ............................................. 130 W/ch
Input shorted 250 mV ........................................... 100 dB or more
B, G, F models (4 ohms)
PHONO (MM) to AV OUT (R, T, K, A, B, G, F, L, S models)
FRONT L/R ................................................................ 160 W/ch
Input shorted 5 mV ................................................. 81 dB or more
– 2 channels driven simultaneously –
Residual Noise (IHF-A Network)
U, C, R, T, K, A, B, G, F, L, S models (8 ohms)
FRONT L/R to SP OUT ................................................150 μV or less
FRONT L/R .......................................................110 W + 110 W
CENTER .......................................................................... 110 W Channel Separation (1 kHz / 10 kHz)
SURROUND L/R ...............................................110 W + 110 W AV5 etc. (Input 5.1 k-ohms shorted)
SURROUND BACK L/R ....................................110 W + 110 W ...................................................... 60 dB or more / 45 dB or more
(20 Hz to 20 kHz, 0.09 % THD) PHONO (Input shorted) (R, T, K, A, B, G, F, L, S models)
– 2 channels driven simultaneously – ...................................................... 60 dB or more / 55 dB or more
U, C, R, T, K, A, B, G, F, L, S models (8 ohms) Volume Control/Step
FRONT L/R .......................................................100 W + 100 W ......................................... MUTE / -80 dB to +16.5 dB / 0.5 dB step
Maximum Effective Output Power (JEITA) [R, T, L, S models] Tone Control Characteristics
(1 channel driven, 1 kHz, 10 % THD, 8 ohms)
Bass
FRONT L/R ......................................................................... 160 W/ch
Boost/Cut ........................................ ±6 dB / 0.5 dB step, at 50 Hz
CENTER .................................................................................. 160 W
Turnover frequency ............................................................. 350 Hz
SURROUND L/R ................................................................ 160 W/ch
SURROUND BACK L/R ..................................................... 160 W/ch Treble
Boost/Cut .......................................±6 dB / 0.5 dB step, at 20 kHz
Dynamic Power Per Channel (IHF) Turnover frequency ............................................................ 3.5 kHz
FRONT L/R (1 channel driven)
8 / 6 / 4 / 2 ohms ....................................... 140 / 180 / 210 / 250 W Filter Characteristics
FRONT, CENTER, SURROUND, SURROUND BACK small (H.P.F.)
Damping Factor (20 Hz to 20 kHz, 8 ohms)
.................... fc=40/60/80/90/100/110/120/160/200 Hz, 12 dB/oct.
FRONT L/R to SPEAKER-A ............................................ 100 or more
SUBWOOFER small (L.P.F.)
Input Sensitivity/Input Impedance (1 kHz, 100 W/8 ohms) .................... fc=40/60/80/90/100/110/120/160/200 Hz, 24 dB/oct.
AV5 etc. ............................................................ 200 mV / 47 k-ohms
Optical Jack, Coaxial Jack Support Frequencies
PHONO (MM) (R, T, K, A, B, G, F, L, S models) ............................................................................... 32 kHz to 96 kHz
......................................................................... 3.5 mV / 47 k-ohms
Maximum Input Signal (1 kHz) ■ Video Section

AV5 etc. (EFFECT ON)
Video Signal Type
0.5 % THD .............................................................................. 2.3 V
Monitor out
PHONO (MM) (R, T, K, A, B, G, F, L, S models)
U, C, R, K models ................................................................. NTSC
0.1 % THD ............................................................................ 60 mV
T, A, B, G, F, L, S models ......................................................... PAL
Output Level/Output Impedance Video conversion
AV OUT ............................................................ 200 mV / 1.2 k-ohms .......................................................................................NTSC/PAL
PRE OUT ................................................................. 1 V / 1.2 k-ohms Composite Video Signal Level
SUBWOOFER (2 ch stereo and FRONT SP: small) ...............................................................................1 Vp-p / 75 ohms
.............................................................................. 1 V / 1.2 k-ohms
Component Video Signal Level
ZONE2 OUT ..................................................... 200 mV / 1.2 k-ohms
Y .............................................................................1 Vp-p / 75 ohms
RX-A830
Headphone Jack Rated Output/Output Impedance Pb/Pr ...................................................................0.7 Vp-p / 75 ohms

(1 kHz, 50 mV, 8 ohms)
AV5 etc. input ..................................................... 100 mV / 560 ohms Video Maximum Input Level (VIDEO Conversion Off)
................................................................................ 1.5 Vp-p or more
Frequency Response (10 Hz to 100 kHz)
AV5 etc., FRONT ..................................................................0 / -3 dB Video Signal to Noise Ratio
................................................................................... 50 dB or more
RIAA Equalization Deviation [R, T, K, A, B, G, F, L, S models]
PHONO (MM) ................................................................... 0 ±0.5 dB Monitor Out Frequency Response (VIDEO Conversion Off)
Component video signal level .......................5 Hz to 60 MHz, -3 dB
8
RX-A830
■ FM Section
Tuning Range Dimensions (W x H x D)

U, C models ......................................................... 87.5 to 107.9 MHz ............................... 435 x 171 x 369 mm (17-1/8" x 6-3/4" x 14-1/2")
R, L, S models ......................... 87.5 to 108.0 / 87.50 to 108.00 MHz Weight

T, K, A, B, G, F models .................................... 87.50 to 108.00 MHz .............................................................................. 10.5 kg (23.1 lbs.)
50 dB Quieting Sensitivity (IHF) (1 kHz, 100 % MOD.) Finish

Mono ......................................................................... 3 μV (20.8 dBf) T model .............................................................................Gold color
Signal to Noise Ratio (IHF) U, C, R, T, K, A, B, G, F, L, S models .............................. Black color
Mono ........................................................................................71 dB B, G, F, L models ........................................................Titanium color
Stereo ......................................................................................69 dB Accessories
Harmonic Distortion (1 kHz) Remote control ..............................................................................x 1
Mono ........................................................................................ 0.3 % Batteries (R03, AAA, UM-4) ..........................................................x 2
Stereo ...................................................................................... 0.5 % FM antenna (1.4 m) ......................................................................x 1

AM antenna (1.0 m) ......................................................................x 1
Antenna Input
......................................................................... 75 ohms unbalanced YPAO microphone (6.0 m) ............................................................x 1
Antenna isolator (T model) ...........................................................x 1
■ AM Section Conversion plug (T model) ...........................................................x 1

Power cable (2.0 m)
Tuning Range
U, C, R, T, K, A, B, G, F, S models .............................................x 1
U, C models ........................................................... 530 to 1,710 kHz
L model ......................................................................................x 2
R, L, S models ................................ 530 to 1,710 / 531 to 1,611 kHz
T, K, A, B, G, F models .......................................... 531 to 1,611 kHz
* Specifications are subject to change without notice.
Antenna
..................................................................................... Loop antenna U ........................U.S.A. model B .......................British model
C ..................Canadian model G ..................European model
R .....................General model F..................... Russian model
■ General
T..................... Chinese model L..................Singapore model
Power Supply K ...................... Korean model S ................... Brazilian model
A .................Australian model
U, C models ............................................................ AC 120 V, 60 Hz
R, S models .................................AC 110–120/220–240 V, 50/60 Hz
T model ................................................................... AC 220 V, 50 Hz
K model .................................................................. AC 220 V, 60 Hz
A model .................................................................. AC 240 V, 50 Hz
B, G, F models ........................................................ AC 230 V, 50 Hz
Manufactured under license from Dolby Laboratories. Dolby, Pro Logic,
L model ...................................................... AC 220–240 V, 50/60 Hz Surround EX and the double-D symbol are trademarks of Dolby Laboratories.
Power Consumption
U, C models ..............................................................400 W / 500 VA
R, T, L, S models ..................................................................... 270 W DTS-HD, the Symbol, & DTS-HD and the Symbol together are registered
K, A, B, G, F models ............................................................... 300 W trademarks & DTS-HD Master Audio is a trademark of DTS, Inc.
Product includes software. © DTS, Inc. All Rights Reserved.
Standby Power Consumption (reference data)
HDMI control: OFF / Standby through: OFF
U, C models .............................................................0.10 W or less
R, T, K, A, B, G, F, L, S models .................................0.15 W or less AirPlay, the AirPlay logo, iPad, iPhone, iPod, iPod nano, and iPod touch are
trademarks of Apple Inc., registered in the U.S. and other countries.
HDMI control: ON / Standby through: ON
INPUT: HDMI1 (HDMI no signal)
RX-A830
................................................................................3.0 W or less
Network standby: ON
...................................................................................3.0 W or less
Maximum Power Consumption [R, L, S models] MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and
................................................................................................ 590 W Thomson.
9
RX-A830
DLNA™ and DLNA CERTIFIED™ are trademarks or registered trademarks

This receiver supports network connections. of Digital Living Network Alliance. All rights reserved. Unauthorized use is
strictly prohibited.
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are

trademarks or registered trademarks of HDMI Licensing LLC in the United Windows is a registered trademark of Microsoft Corporation in the United
States and other countries. States and other countries.
Internet Explorer, Windows Media Audio and Windows Media Player are
either registered trademarks or trademarks of Microsoft Corporation in the
MHL and the MHL logo are a trademark, registered trademark or service
United States and/or other countries.
mark of MHL, LLC in the United States and/or other countries.
Android is a trademark of Google Inc.

“x.v.Color” is a trademark of Sony Corporation.
“SILENT CINEMA” is a trademark of Yamaha Corporation.
• DIMENSIONS
(7/8")
(2-7/8")
22
Top view ø 60
72
173 (6-3/4")
324 (12-3/4")
369 (14-1/2")
ø 48/18
193 (7-5/8")
222.5 (8-3/4") 212.5 (8-3/8")
50 335 (13-1/4")
59
(2-1/4")
23
(7/8")
(2")
Front view
RX-A830
150 (5-7/8")
171 (6-3/4")
21
(7/8")
435 (17-1/8")
Unit: mm (inch)
10
RX-A830
• SET MENU TABLE

MAIN MENU SUB-MENU PARAMETER VALUE [INITIAL VALUE]
Speaker Auto Measure Optimizes the speaker configuration automatically using YPAO.
Setup Multi Position Yes / No
Result Not Available
Manual Power Amp Assign [Basic] / 7ch +1ZONE / 5ch BI-AMP
Configuration Front Large / [Small]
* “Front” is automatically set to “Large” when “Subwoofer” is set to “None”.
Center Large / [Small] / None
Surround
Surround Back Large x1 / Large x2 / Small x1 / [Small x2] / None
* This setting is not available when “Power Amp Assign” is set to “5ch BI-
AMP”, or when “Surround” is set to “None”.
Front Presence [Use] / None

Subwoofer Use / None
[Normal] / Reverse
Extra Bass [Off] / On
* This setting is not available when “Subwoofer” is set to “None”, or when
“Front” is set to “Small”.
Bass Cross Over 40 / 60 / [80] / 90 / 100 / 110 / 120 / 160 / 200 Hz

Distance Meter / Feet
Front L
Front R
Center
Surround L
Surround R 0.30 to 24.00 m, [3.00 m], 0.05 m step
Surround Back L 1.0 to 80.0 ft, [10.0 ft], 0.2 ft step
Surround Back R
Front Presence L
Front Presence R
Subwoofer
Level Front L
Front R
Center
Surround L
Surround R -10.0 to +10.0 dB, [0.0 dB], 0.5 dB step
Surround Back L
Surround Back R
Front Presence L
Front Presence R
Subwoofer
Parametric EQ Manual / YPAO : Flat / YPAO : Front / YPAO : Natural / Through
* Select “ENTER”
Front L Band ▶ Band: #1 to #7
Front R / Gain ▲ Gain: -20.0 to +6.0 dB, [0.0 dB], 0.5 dB step
Center
Surround L Frequency ▶ Frequency: 31.3 Hz to 16.0 kHz, [62.5 Hz]
Surround R / Gain ▲ Gain: -20.0 to +6.0 dB, [0.0 dB], 0.5 dB step
Surround Back L
Surround Back R Q ▶ Q: 0.500 to 10.080, [1.000]
Front Presence L / Gain ▲ Gain: -20.0 to +6.0 dB, [0.0 dB], 0.5 dB step
Front Presence R
PEQ Data Copy Flat > Manual / Front > Manual / Natural > Manual
* Select “ENTER”
RX-A830
PEQ Data Clear OK / CANCEL * Select “ENTER”

Test Tone [Off] / On
Sound Setup Lipsync Delay Enable HDMI1 / HDMI2 / HDMI3 / HDMI4 /
HDMI5 / HDMI6 / HDMI7 / Disable / [Enable]
AV1 / AV2 / AV3 / AV4 / AV5 / AV6 /
V-AUX / AUDIO1 / AUDIO2
Auto/Manual Select [Auto] / Manual
Adjustment 0 to 500 ms, [0 ms], 1 ms step
11
RX-A830
MAIN MENU SUB-MENU PARAMETER VALUE [INITIAL VALUE]

Sound Setup Dynamic Range [Maximum] / Standard / Minimum/Auto
Max. Volume -30.0 to +15.0 dB, 5.0 dB step / [+16.5 dB (Maximum volume)]
Initial Volume [Off] / On
Select “On” Mute, -80.0 to +16.5 dB, [-40.0 dB], 0.5 dB step
Adaptive DSP Level Off / [On]
Video Setup Video Mode [Direct] / Processing
Select Resolution Through / [Auto] / 480p/576p / 720p / 1080i / 1080p / 4K
“Processing” * Select “ENTER”
Aspect [Through] / 16:9 Normal
HDMI Setup HDMI Control [Off] / On
Select “On” TV Audio Input AV1 / AV2 / AV3 / [AV4] / AV5 / AV6 / AUDIO1 / AUDIO2
ARC Off / [On]
(Audio Return Channel)
Standby Sync Off / On / [Auto]
Audio Output Amp Off / [On]
HDMI OUT 1 [Off] / On
HDMI OUT 2
* This setting is available only when “HDMI Control” is set to “Off”.
Standby Through [Off] / On
* This setting is available only when “HDMI Control” is set to “Off”.
Network IP Address DHCP Off / [On]
Setup Select “Off” IP Address xxx.xxx.xxx. x
Subnet Mask xxx.xxx.xxx. x
Default Gateway xxx.xxx.xxx. x
DNS Server (P) x. x. x. x
Primary
DNS Server (S) x. x. x. x
Secondary
Network Standby [Off] / On
MAC Address Filter [Off] / On
Filter Select “On” MAC Address 1–5 xx : xx : xx : xx : xx : xx
MAC Address 6–10 xx : xx : xx : xx : xx : xx
Network Name Input is possible to 15 characters
Multi Zone Main Zone Set Zone Rename Input is possible to 9 characters
Setup Zone2 Set Max. Volume -30.0 to +15.0 dB, 5.0 dB step / [+16.5 dB (Maximum volume)]
* This setting is available only when “Power Amp Assign” is set to “7ch
+1ZONE”.
Initial Volume [Off] / On

Select “On” Mute, -80.0 to +16.5 dB, [-40.0 dB], 0.5 dB step
* This setting is available only when “Power Amp Assign” is set to “7ch +1ZONE”.
Zone Rename Input is possible to 9 characters
Party Mode Set Target: Zone2 Disable / [Enable]
Function Display Set Dimmer (Front Display) -4 to 0 (higher to brighten), [0], 1 step
Setup Short Message [On] / Off
Wall Paper [Picture1] / Picture2 / Picture3 / Gray
Trigger Output Trigger Mode [Power] / Source / Manual
Select “Source” HDMI1–7, AV1–6, V-AUX, AUDIO1–2, TUNER,
PHONO (R, T, K, A, B, G, F, L, S models),
Rhapsody, Pandora, AirPlay, SERVER, NET RADIO, USB
Low / [High]
Select “Manual” Low / [High]
Target Zone Main / Zone2 / [All]
RX-A830
DC OUT Power Mode [Continuous] / Main Zone Power Sync.

Memory Guard [Off] / On
ECO Setup Auto Power Standby Off / 2 Hours / 4 Hours / 8 Hours / 12 Hours
U, C, R, T, K, A, L, S models: [Off]
B, G, F models: [8 Hours]
ECO Mode [Off] / On
Language [English (English)] / 日本語 (Japanese) / Français (French) /
Setup Deutsch (German) / Español (Spanish) / Русский (Russian) /
Italiano (Italian) / 中文 (Chinese)
12
RX-A830
■ INTERNAL VIEW
Top view
1 OPERATION (3) P.C.B.
1 2 3 4 5 6 7 8 9
2 MAIN (2) P.C.B. (R, S models)
3 DIGITAL (3) P.C.B.
5 DIGITAL (1) P.C.B.
7 AM/FM TUNER
10 MAIN (6) P.C.B.
11 MAIN (4) P.C.B.
12 MAIN (3) P.C.B.
13 MAIN (1) P.C.B.
14 MAIN (5) P.C.B.
15 POWER TRANSFORMER
15 14 13 12 11 10 19 DIGITAL (2) P.C.B.
Front view
16 17
21 20 19 18
■ SERVICE PRECAUTIONS
Safety measures
• Some internal parts in this product contain high voltages and are dangerous.
Be sure to take safety measures during servicing, such as wearing insulating gloves.
• Note that the capacitors indicated below are dangerous even after the power is turned off because an electric charge
RX-A830
remains and a high voltage continues to exist there.

Before starting any repair work, connect a discharging resistor (5 k-ohms/10 W) to the terminals of each capacitor
indicated below to discharge electricity.
The time required for discharging is about 30 seconds per each.
C1084 and C1085 on MAIN (1) P.C.B.
C3706 on OPERATION (3) P.C.B.
For details, refer to “PRINTED CIRCUIT BOARDS”.
13
RX-A830
■ DISASSEMBLY PROCEDURES
(Remove parts in the order as numbered.)
Disconnect the power cable from the AC outlet.
1. Removal of Top Cover

a. Remove 4 screws (①), 5 screws (②) and screw (③). (Fig. 1)
b. Lift the rear of the top cover to remove it. (Fig. 1)
2. Removal of Front Panel Unit and Sub-Chassis Unit

a. Remove knob (INPUT) and knob (VOLUME). (Fig. 1)
b. Remove 6 screws (④) and then remove the front panel unit. (Fig. 1)
c. Remove 2 push rivets and then remove the side plate (L) and side plate (R). (Fig. 1)
d. Remove CB8, CB82, CB308, CB343, CB411, CB412, CB947 and CB952. (Fig. 1)
e. Remove 2 screws (⑤) and then remove the sub-chassis unit. (Fig. 1)
Top cover
②
CB412
CB411
CB947
Side plate (L)
Push rivet OPERATION (5) P.C.B. ①

CB8
CB308
CB82
④
⑤
DIGITAL (1) P.C.B.
CB952
CB343
OPERATION (2) P.C.B.
Knob ④ ⑤ Push rivet

Sub-chassis unit
RX-A830
(INPUT)
Knob
(VOLUME) Side plate (R)
Front panel unit
Fig. 1
14
RX-A830
3. Removal of DIGITAL (1) and (3) P.C.B.s 4. Removal of AMP Unit and Power Transformer
a. Remove screw (⑥) and 10 screws (⑦). (Fig. 3) a. Remove screw (⑨), 2 screws (⑩), 3 screws (⑪) and
b. Remove 3 screws. (⑧). (Fig. 2) 4 screws (⑫). (Fig. 2)
c. Remove CB76, CB78, CB79, CB80, CB942 and CB948. b. Remove 3 screws (⑬). (Fig. 3)
(Fig. 2) c. Remove the AMP unit together with the power
d. Unlock and remove CB946 and CB948. (Fig. 2) transformer. (Fig. 2)
e. Remove 2 jack screws and then remove the DIGITAL
(3) P.C.B. (Fig. 2, 3)
f. Remove the DIGITAL (1) P.C.B. which is connected
directly to the OPERATION (4) P.C.B. with board-to-
board connectors. (Fig. 2) CB76 ⑧
CB942
Remove CB946 and CB948 CB944
DIGITAL (1) P.C.B.
① Unlock the connector
Connected ② Remove the cable
① ①
Power transformer
②
⑫ CB945
⑫ CB79 Board-to-board connectors

Cable CB78
Connect CB946 and CB948 CB80 CB948
① Lock the connector CB946
Connected ② Insert the cable
Jack screw
① ①
⑩
⑨ Board-to-board connectors
②
Cable OPERATION (4) P.C.B.

⑪
⑩
CB381
DIGITAL (3) P.C.B.
AMP unit
OPERATION (2) P.C.B.
⑪
Fig. 2
⑥ ⑦ 2 jack screws
Rear view
RX-A830
⑬
Fig. 3
15
RX-A830
When checking the MAIN (1) P.C.B.:

• Place the P.C.B.s (with rear panel) upright. (Fig. 4)
• Connect the heatsink and rear panel to the chassis with a ground lead or the like. (Fig. 4)
• Reconnect all cables (connectors) that have been disconnected.
• When connecting the flexible flat cable, be careful with polarity.
Rear panel
Power transformer
Ground lead
Chassis
Rubber sheet and the cloth

MAIN (1) P.C.B.
Ground lead
Heatsink
Fig. 4
RX-A830
16
RX-A830
When checking the DIGITAL (1) P.C.B.:

• Put the rubber sheet and cloth over this unit, and place the DIGITAL (1) P.C.B. on them. (Fig. 5)
• Connect ST951 on DIGITAL (1) P.C.B. to the chassis with a ground lead. (Fig. 5)
• Reconnect all cables (connectors) that have been disconnected. Be sure to use the P.C.B. CHECKING JIG (Part No.
ZF454800) to connect between the following connectors.
CB945 on DIGITAL (1) P.C.B. – CB381 on OPERATION (4) P.C.B.
• When connecting the flexible flat cable, be careful with polarity.
DIGITAL (1) P.C.B.
P.C.B. CHECKING JIG

CB948
CB946
CB945 OPERATION (4) P.C.B.
Rubber sheet and cloth
CB381
ST951
CB154
CB155
Ground lead
Chassis
Fig. 5
RX-A830
17
RX-A830
■ UPDATING FIRMWARE
When the following parts are replaced, the firmware must be updated to the latest version.
DIGITAL P.C.B.
FPGA Flash ROM: IC77 on DIGITAL (1) P.C.B.
DSP (TI) Flash ROM: IC923 on DIGITAL (1) P.C.B.
NETWORK Flash ROM: IC953 on DIGITAL (1) P.C.B.
● Confirmation of firmware version and checksum

Before and after updating the firmware, check the firmware version and checksum by using the self-diagnostic
function menu.
Start up the self-diagnostic function and select “S4. ROM VERSION/CHECKSUM” menu.
Using the sub-menu, have the firmware version and checksum displayed, and note them down.
(For details, refer to “SELF-DIAGNOSTIC FUNCTION”)
* When the firmware version is different from written one after updating, perform the updating procedure again from
the beginning again.
● Initializing the back-up IC (EEPROM: IC82 on DIGITAL P.C.B.)
After updating the firmware, the back-up IC MUST be initialized by the following procedure to store the setting
information (soundfield parameters, system memory and tuner presetting, etc.) properly.
Start up the self-diagnostic function and select “S3. FACTORY PRESET” menu.
(For details, refer to “SELF-DIAGNOSTIC FUNCTION”)
Select “PRESET RSRV”, press the “MAIN ZONE ” key to turn off the power once and turn on the power again. Then
the back-up IC is initialized.
● Required Tools
• USB storage device
• Firmware
R0331-xxxx.bin
● Preparation
1. Download the latest firmware from the specified download source to the folder of the PC.
2. Copy the latest firmware from the PC to the root folder of the USB storage device.
Note: When the latest firmware is copied to a sub-folder of the USB storage device, the update will not proceed.
RX-A830
18
RX-A830
● Operation Procedures
1. Insert the USB storage device to the USB jack. (Fig. 1)
2. While pressing the “PURE DIRECT” key, connect the power cable to the AC outlet. (Fig. 1)
"MAIN ZONE " key "PURE DIRECT" key
USB jack
USB storage device
Fig. 1
3. The USB UPDATE mode is activated and “USB UPDATE” is displayed. Writing of the firmware starts automatically.
(Fig. 2)
Writing is started. Writing being executed.
USB UPDATE VERIFYING... Sx-x:xx%
S1: NET (IC951/IC953 on DIGITAL (1) P.C.B.) section

S2: MAIN (IC83 on DIGITAL (1) P.C.B.) section
S3: DSP1 (IC921/IC923 on DIGITAL (1) P.C.B.) section
S4: DSP2 section (Not available)
S5: GUI (IC50/IC77 on DIGITAL (1) P.C.B.) section
Fig. 2
* If “ERROR! xxxx” is displayed during writing of the firmware, refer to “List of Error Messages” to determine the
cause and perform the updating procedure again from the beginning.
4. When writing of the firmware is completed, “UPDATE SUCCESS”, “PLEASE...” and “POWER OFF!” are displayed
repeatedly. (Fig. 3)
Writing is completed.
UPDATE SUCCESS PLEASE... POWER OFF!

RX-A830
Fig. 3
5. Press the “MAIN ZONE ” key to turn off the power. (Fig. 1)
6. Remove the USB storage device from the USB jack. (Fig. 1)
7. Start up the self-diagnostic function and check that the firmware version and checksum are the same as written
ones. (For details, refer to “Confirmation of firmware version and checksum”)
19
RX-A830
List of Error Messages
Display
ERROR! xxxx
Error number
Error Number Error Message Cause
0001 Microprocessor clearing error Microprocessor failure
0002 Microprocessor writing error
0004 Microprocessor checksum error Microprocessor failure / Mismatch of checksum
0008 DSP1 status port error
0010 DSP1 checksum error DSP1 failure /

0020 DSP1 data reception time out Malfunction of communication with microprocessor
0040 DSP1 checksum calculation time out
0080 DSP2 status port error
0100 DSP2 checksum error DSP2 failure /

0200 DSP2 date reception time out Malfunction of communication with microprocessor
0400 DSP2 checksum calculation time out
0800 GUI Flash ROM clearing error

GUI Flash ROM failure /
1000 GUI Flash ROM writing error
Malfunction of communication with microprocessor
2000 GUI Flash ROM checksum error
4000 Destination judging error No destination is written on EEPROM.
* The error number is displayed in the 4-digit hexadecimal notation.
* The error numbers are added when a multiple number of errors occur at the same time.
Example If errors by the error number “0002” and “0008” occur at the same time, the error number will be displayed as “000A”.
RX-A830
20
RX-A830
■ SELF-DIAGNOSTIC FUNCTION
This unit has self-diagnostic functions that are intended for inspection, measurement and location of faulty point.
There are 26 main menu items, each of which has sub-menu items.
Listed in the table below are main menu items and sub-menu items.
Note: Some of the menu items listed below may not apply to the models covered in this service manual.
No. Main menu No. Sub-menu

A: Audio system
A1 DSP AUDIO 1 DSP MARGIN
2 DSP NON MARGIN
3 INVALID ITEM (Not for service)
4 DSP FULL CENTER
5 DSP FULL SURROUND
6 DSP FULL SURROUND BACK
7 DSP FULL SUBWOOFER
A2 DIRECT AUDIO 1 ANALOG DIRECT VH
2 ANALOG DIRECT VL
A3 HDMI AUDIO 1 HDMI AUTO
3 ARC 1
A4 SPEAKERS SET 1 BI-AMP
2 ZONE/TONE=MAX
3 ZONE/TONE=MIN
6 D-PARTY MODE
7 FULL MUTE
A5 MULTI CHANNEL INPUT 1 MULTI CHANNEL INPUT 8 ohms
(Not for service) 2 MULTI CHANNEL INPUT 6 ohms
A6 MIC CHECK 1 MIC ROUTE CHECK
A7 MANUAL TEST 1 TEST ALL
2 TEST FRONT L
3 TEST CENTER
4 TEST FRONT R
5 TEST SURROUND R
6 TEST SURROUND BACK R
RX-A830
7 TEST SURROUND BACK L

8 TEST SURROUND L
9 TEST FRONT PRESENCE L
10 TEST FRONT PRESENCE R
13 TEST LFE 1
21
RX-A830

D: Display system
D1 FL CHECK 1 FL CHECK
2 ALL SEGMENT OFF
3 ALL SEGMENT ON
4 CHECK PATTERN 1
5 CHECK PATTERN 2
Z: Zone system
Z1 ZONE TEST 1 AV1 (Not for service)
2 AV2 (Not for service)
5 AV5
6 AV6
7 AUDIO1
8 AUDIO2
9 V-AUX (Not for service)
10 PHONO (R, T, K, A, B, G, F, L, S models)
U: Universal system
U1 USB 1 USB FRONT 1 TRACK
2 USB FRONT 2 TRACK
3 USB_VBUS HIGH POWER
N: Network system
N1 NETWORK 1 IP ADDRESS CHECK
2 MAC ADDRESS CHECK
3 LINE NOISE 100 MDI (Not for service)
4 LINE NOISE 100 MDIX (Not for service)
5 LINE NOISE 10 MDI (Not for service)
6 LINE NOISE 10 MDIX (Not for service)
7 EXT TEST
8 MAC ADDRESS
C: Communication system
C1 DIGITAL PCB CHECK 1 ALL
2 BUS FLASH ROM
3 BUS FPGA
4 I2C
5 FPGA RAM
6 BUS DIR
7 BUS DSP
8 EEPROM
9 RS-232C LOOPBACK TEST (Not for service)
C2 NETWORK IC CHECK 1 ALL
2 LINK CHECK
RX-A830
3 PHY TEST
4 BUS RAM
5 APL ID CHECK
22
RX-A830

V: Video system
V1 ANALOG VIDEO CHECK 1 ANALOG BYPASS
4 MUTE CHECK
5 TEST PATTERN (Not for service)
6 VIDEO IN
V2 DIGITAL VIDEO CHECK 1 LOOPBACK TEST 1
2 LOOPBACK TEST 2
3 LOOPBACK TEST 3
4 LOOPBACK TEST 4
7 HDMI REPEAT
8 DIGITAL CVBS
10 DIGITAL COMPONENT
11 DIGITAL COMPONENT SC
12 GUI-VIDEO OUT
V3 TEST PATTERN 1 480i
2 480p
3 720p 60Hz
4 1080i 60Hz
5 1080p 60Hz
6 576i
7 576p
8 720p 50Hz
9 1080i 50Hz
10 1080p 50Hz
11 1080p 24Hz
12 1080p 24Hz 3D/FP
13 720p 60Hz 3D/FP
14 720p 50Hz 3D/FP
15 1080i 60Hz 3D/FP
16 1080i 60Hz 3D/SS
17 1080i 50Hz 3D/SS
18 720p 60Hz 3D/TB
19 720p 50Hz 3D/TB
20 1080p 24Hz 3D/TB
21 4k 24Hz
T: Troubleshooting Information
T1 TROUBLE SHOOTING INFORMATION 1 OPERATING TIME
2 POWER-RELAY ON
RX-A830
3 POWER AMP B
4 OUTPUT LEVEL
5 POWER OFF TIME-OUT
T2 USAGE ENVIRONMENT 1 MAIN ZONE HIGHEST VOLUME
2 ZONE 2 HIGHEST VOLUME
4 THM1/THM2 HIGHEST TEMPERATURE
5 THM3/THM4 HIGHEST TEMPERATURE (Not for service)
23
RX-A830

T3 EXTERNAL EVENT 1 HISTORY 1
2 HISTORY 2
3 HISTORY 3
4 HISTORY 4
5 HISTORY 5
6 HISTORY 6
7 HISTORY 7
8 HISTORY 8
T4 INTERNAL INFOMATION 1 DSP INFORMATION
2 BU ERROR (Not for service)
3 NRC (Net Restart Counter) (Not for service)
P: Power and protection system
P1 SYSTEM MONITOR 1 DC
2 PS
3 THM
5 OUTPUT LEVEL
6 LIMITER CONTROL
7 L3 (J model) (Not for service)
8 KEY
9 USB-VBUS (Not for service)
P2 PROTECTION HISTORY 1 HISTORY 1
2 HISTORY 2
3 HISTORY 3
4 HISTORY 4
S: System and version system
S1 FIRMWARE UPDATE 1 FIRMWARE UPDATE (Not for service)
S2 SET INFORMATION 1 MODEL
2 DESTINATION
S3 FACTORY PRESET 1 PRESET INHIBIT/RESERVE
S4 ROM VERSION/CHECKSUM 1 SYSTEM VERSION
2 MICROPROCESSOR VERSION
3 MICROPROCESSOR CHECKSUM
4 FLASH ROM VERSION
5 FLASH ROM CHECKSUM
6 NETWORK MICROPROCESSOR VERSION
7 NETWORK MICROPROCESSOR CHECKSUM
8 DSP1 VERSION
9 DSP1 CHECKSUM
12 GUI VERSION
RX-A830
13 FPGA GUI VERSION

14 FPGA SD VERSION
15 FPGA HD VERSION
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RX-A830
● Starting Self-Diagnostic Function

While pressing the “TONE CONTROL” and “INFO” keys, press the “MAIN ZONE ” key to turn on the power, and release
those 2 keys.
The self-diagnostic function mode is activated.
Keys of this unit
While pressing these keys, turn on the power.
● Starting Self-Diagnostic Function in the protection cancel mode

If the protection function works and causes hindrance to troubleshooting, cancel the protection function by the procedure
below, and it will be possible to enter the self-diagnostic function mode. (The protection functions other than the excess
current detect function will be disabled.)
While pressing the “TONE CONTROL” and “INFO” keys, press the “MAIN ZONE ” key to turn on the power and keep
pressing those 2 keys and “MAIN ZONE ” key for 3 seconds or longer.
The self-diagnostic function mode is activated with the protection functions disabled.
In this mode, the “SLEEP” segment of the FL display flashes to indicate that the mode is self-diagnostic function mode with the
protection functions disabled.
CAUTION!
Using this unit with the protection function disabled may cause further damage to this unit. Use special care for this point
when using this mode.
RX-A830
25
RX-A830
● Canceling Self-Diagnostic Function

1. Before canceling self-diagnostic function, execute setting for “S3. FACTORY PRESET” menu. (Memory initialization
inhibited or Memory initialized).
* In order to keep the user memory preserved, be sure to select PRESET INHIBIT (Memory initialization inhibited).
2. Press the “MAIN ZONE ” key to turn off the power.
● Display provided when Self-Diagnostic Function started

The display is as described below depending on the situation when the power to this unit is turned off.
1. When the power is turned off by usual operation:

“NO PROTECT” is displayed. Then “A1-1. DSP MARGIN” is displayed in a few seconds.
Opening message Main menu display

After a few seconds
A1-1
NO PROTECT DSP MARGIN
2. When the protection function worked to turn off the power:

The information of protection function which worked at that time is displayed. Then “A1-1. DSP MARGIN” is displayed in
a few seconds.
Note: At that time if you restart the self-diagnostic function after turning off the power once, “NO PROTECT” will be
displayed. That is because that situation is equal to “1. When the power is turned off by usual operation:”.
However history of the protection function is stored in memory as backup data. For details, refer to “P2.
PROTECTION HISTORY” menu.
2-1. When there is a history of protection function due to excess current.
I PROTECT
Cause: An excessive current flowed through the power amplifier.

Supplementary information: As over current of the power amplifier is detected, check condition of each power transistor.
Turning on the power without correcting the abnormality will cause the protection function to work immediately and the
power supply will instantly be shut off.
Notes:
• Applying the power to this unit without correcting the abnormality can be dangerous and cause additional
RX-A830
circuit damage. To avoid this, if “I PROTECT” protection function works 1 time, the power will not turn on even
when the “MAIN ZONE ” key is pressed. In order to turn on the power again, start up the self-diagnostic
function.
• The output transistors in each amplifier channel should be checked for damage before applying power to this
unit.
• Amplifier current should be monitored by measuring DC voltage across the emitter resistors for each channel.
26
RX-A830
2-2. When the protection function worked due to abnormal DC output.
H: Displayed when the voltage is HIGHER than upper limit

L: Displayed when the voltage is LOWER than lower limit
DC PRT:xxxH
xxx: A/D conversion value of voltage at the moment when the protection function worked
(Reference voltage: 3.3 V=255)
Cause: DC output of the power amplifier is abnormal.

Supplementary information: The protection function worked due to a DC voltage appearing at the speaker terminal. A
cause could be a defect in the amplifier.
Turning on the power without correcting the abnormality will cause the protection function to work in 5 seconds and the
power supply will be shut off.
2-3. When the protection function worked due to abnormal voltage in the power supply section.

PSxPRT:xxxL
PS1/PS2/PS3
Cause: The voltage in the power supply section is abnormal.

Supplementary information: The protection function worked due to a defect or overload in the power supply.
Notes:
• Applying the power to this unit without correcting the abnormality can be dangerous and cause additional
circuit damage. To avoid this, if “PS” and “DC” protection function works 3 times consecutively, the power will
not turn on even when the “MAIN ZONE ” key is pressed. In order to turn on the power again, start up the self-
diagnostic function.
• The output transistors in each amplifier channel should be checked for damage before applying power to this
unit.
• Amplifier current should be monitored by measuring DC voltage across the emitter resistors for each channel. RX-A830
27
RX-A830
2-4. When the protection function worked due to excessive heatsink temperature.

TMPxPRT:xxxL
TMP1/TMP2 (U, C models)
Cause: The temperature of the heatsink is excessive.

Supplementary information: The protection function worked due to the temperature limit being exceeded. Causes could
be poor ventilation or a defect related to the thermal sensor.
● History of protection function

When the protection function has worked, its history is stored in memory as backup data.
Even if no abnormality is noted while servicing the unit, an abnormality which has occurred previously can be defined
as long as the backup data has been stored.
For details, refer to “P2. PROTECTION HISTORY” menu.
RX-A830
28
RX-A830
● Operation procedure of Main menu and Sub-menu

There are 26 main menu items, each of which has sub-menu items.
Main menu selection

Select the main menu using “SCENE TV” (forward) and “SCENE BD/DVD” (reverse) keys.
Sub-menu selection
Select the sub-menu using “SCENE RADIO” (forward) and “SCENE NET” (reverse) keys.
Keys of this unit
Main menu selection Sub-menu selection
Reverse Forward Reverse Forward
● Functions in Self-Diagnostic Function mode

In addition to the self-diagnostic function menu items, functions listed below are available.
• Power ON/OFF
• Master volume
• Muting
• Input selection
• Zone control
* Functions related to the tuner and the set menu are not available.
● Initial settings when Self-Diagnostic Function started

The following initial settings are used when self-diagnostic function is started.
• Master volume: -20 dB / Zone volume: +2.5dB
• Input: HDMI1 / Zone input: AUDIO1
• Main menu: A1-1. DSP MARGIN
• Speaker setting: LARGE, Bass out to SWFR (All channels)
RX-A830
• HDMI Control: Off

• Zone 2: On
* When self-diagnostic function is canceled, these settings are restored to those before starting self-diagnostic function.
29
RX-A830
● Details of Self-Diagnostic Function menu

A1. DSP AUDIO
This menu is used to check audio signal route via DSP.
A1-1. DSP MARGIN

The audio signal is output including the head margin via DSP.
* When input source is stereo, signal is assigned as below.
Front L: Front L, Center, Surround L, Surround Back L
Front R: Front R, Surround R, Surround Back R
Front L +10 dB: Subwoofer
A1-1
DSP MARGIN
A1-2. DSP NON MARGIN

The SUBWOOFER signal is output including the head margin via DSP.
The audio signal other than SUBWOOFER is output without including the head margin via DSP.
A1-2
DSP NON MARGIN
A1-3. INVALID ITEM

Not for service.
A1-3
INVALID ITEM
A1-4. DSP FULL CENTER

The audio signal is output to only CENTER channel in digital full bit without including the head margin.
A1-4
DSP FULL C
A1-5. DSP FULL SURROUND

RX-A830
The audio signal is output to only SURROUND L/R channels in digital full bit without including the head margin.
A1-5
DSP FULL SUR
30
RX-A830
A1-6. DSP FULL SURROUND BACK

The audio signal is output to only SURROUND BACK L/R channel in digital full bit without including the head
margin.
A1-6
DSP FULL SB
A1-7. DSP FULL SUBWOOFER

The audio signal is output to only SUBWOOFER channel in digital full bit without including the head margin.
A1-7
DSP FULL SW
A2. DIRECT AUDIO

This menu is used to check audio signal route of PURE DIRECT mode.
A2-1. DIRECT VH
The analog input audio signal is output to FRONT L/R in PURE DIRECT mode.
VH: Voltage High, RY101 on MAIN (1) P.C.B.: Off
A2-1
DIRECT :VH
A2-2. DIRECT VL
The analog input audio signal is output to FRONT L/R in PURE DIRECT mode.
VL: Voltage Low, RY101 on MAIN (1) P.C.B.: On
A2-2
DIRECT :VL
RX-A830
31
RX-A830
A3. HDMI AUDIO

This menu is used to check the route of audio signal input to HDMI IN/OUT jack.
* Before check using “A3-3. ARC 1” menu, be sure to connect a TV monitor equipped with Audio Return Channel
function to this unit in advance.
A3-1 A3-1. HDMI AUTO

HDMI AUTO The audio signal input to selected HDMI IN jack is output.
A3-2 A3-2. INVALID ITEM

INVALID ITEM Not for service.
A3-3 A3-3. ARC 1 (Audio Return Channel function)

ARC 1 The audio signal input to HDMI OUT jack is output.


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32
RX-A830
A4. SPEAKERS SET

This menu is used to check the speaker output.
A4-1 A4-1. BI-AMP

BI-AMP The FRONT L/R signal is distributed to SURROUND BACK L/R terminals.
A4-2 A4-2. ZONE/TONE=MAX

ZONE/TONE=MAX The audio signal is output to FRONT L/R, CENTER and SURROUND L/R terminals with the tone control
“BASS +6 dB”, “TREBLE +6 dB”.
A4-3 A4-3. ZONE/TONE=MIN

ZONE/TONE=MIN The audio signal is output to FRONT L/R, CENTER and SURROUND L/R terminals with the tone control
“BASS -6 dB”, “TREBLE -6 dB”.


A4-6 A4-6. D-PARTY MODE

D-PARTY MODE The FRONT L/R signal is distributed to ZONE2 L/R terminals.
ZONE2 volume: -3.5 dB
A4-7 A4-7. FULL MUTE

FULL MUTE The audio signals are muted at all channels.





RX-A830

33
RX-A830
A5. MULTI CHANNEL INPUT

Not for service.
A5-1 A5-2
8ohm MULTI CH 6ohm MULTI CH
A6. MIC CHECK
A6-1. MIC ROUTE CHECK

The audio signal input to the YPAO MIC jack is output to FRONT L and FRONT R channels via A/D-D/A.
A6-1
MIC ROUTE
A7. MANUAL TEST

The test noise generated by built-in noise generator in DSP is output to the channels specified by the sub-menu.
Test noise Test tone

30 Hz to 80 Hz 50 Hz
for SUBWOOFER
pink noise sine wave
500 Hz to 2 kHz 1 kHz
for other than SUBWOOFER
pink noise sine wave
A7-1 A7-1. TEST ALL

TEST ALL The test noise is output to FRONT L/R, CENTER, SURROUND L/R, SURROUND BACK L/R and LFE 1
channels.
A7-2 A7-2. TEST FRONT L

TEST FRNT L The test tone is output to FRONT L channel.
RX-A830
A7-3 A7-3. TEST CENTER

TEST CENTER The test tone is output to CENTER channel.
A7-4 A7-4. TEST FRONT R

TEST FRNT R The test tone is output to FRONT R channel.
34
RX-A830
A7-5 A7-5. TEST SURROUND R

TEST SURR R The test tone is output to SURROUND R channel.
A7-6 A7-6. TEST SURROUND BACK R

TEST SB R The test tone is output to SURROUND BACK R channel.
A7-7 A7-7. TEST SURROUND BACK L

TEST SB L The test tone is output to SURROUND BACK L channel.
A7-8 A7-8. TEST SURROUND L

TEST SURR L The test tone is output to SURROUND L channel.
A7-9 A7-9. TEST FRONT PRESENCE L

TEST FP L The test tone is output to FRONT PRESENCE L channel.
A7-10 A7-10. TEST FRONT PRESENCE R

TEST FP R The test tone is output to FRONT PRESENCE R channel.


A7-13 A7-13. TEST LFE 1 (SUBWOOFER)

TEST LFE 1 The test tone is output to LFE 1 channel.

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35
RX-A830
D1. FL CHECK
This menu is used to check operation of the FL display.
FL display
D1-1. INITIAL DISPLAY
D1-2. ALL SEGMENT OFF
D1-3. ALL SEGMENT ON
* After check, change to next menu at once.
D1-4. CHECK PATTERN 1
Example
Lighting on segments in lattice.
D1-5. CHECK PATTERN 2

Short Normal
Segment conditions of the FL tube is checked by turning ON and OFF all segments.
RX-A830
Next, a short between segments next to each other is checked by turning ON and OFF all segments alternately (in
lattice).
(In the above example, the segments in the second row from the top are shorted.)
36
RX-A830
Z1. ZONE TEST

This menu is used to check audio signal route to ZONE2 OUT jack.
Z1-1 Z1-1. AV1

AV1 Not for service.
Z1-2 Z1-2. AV2

Z1-3 Z1-3. AV3

Z1-4 Z1-4. AV4

Z1-5 Z1-5. AV5

AV5 The audio signal input to AV5 jack is output to ZONE 2 OUT jack.
Z1-6 Z1-6. AV6

AV6 The audio signal input to AV6 jack is output to ZONE 2 OUT jack.
Z1-7 Z1-7. AUDIO1

AUDIO1 The audio signal input to AUDIO1 jack is output to ZONE 2 OUT jack.
Z1-8 Z1-8. AUDIO2

AUDIO2 The audio signal input to AUDIO2 jack is output to ZONE 2 OUT jack.
Z1-9 Z1-9. V-AUX

V-AUX Not for service.
Z1-10 Z1-10. PHONO (R, T, K, A, B, G, F, L, S models)

PHONO The analog audio signal input to PHONO is output to ZONE2 OUT jack.
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37
RX-A830
U1. USB
This menu is used to check the audio signal route from USB storage device.
U1-1. USB FRONT 1 TRACK

The 1st music file stored in the USB storage device connected to the USB jack is reproduced.
* Copy 2 or more music files from PC to the root folder of the USB storage device in advance.
U1-1
USB_F 1 TRACK
U1-2. USB FRONT 2 TRACK

The 2nd music file stored in the USB storage device connected to the USB jack is reproduced.
U1-2
USB_F 2 TRACK
U1-3. USB_VBUS HIGH POWER

The output current (USB_VBUS) of USB jack is output at up to 2.1A/5V.
U1-3
USB_VBUS_HPWR
N1. NETWORK
This menu is used to check functions related to NETWORK.
Connect between LAN port of broadband router and NETWORK jack of this unit with a network cable.
* When the network condition varies while sub-menu is displayed (e.g., the network is deactivated once), the correct
result will not be displayed.
In that case, once turn off the power to this unit, then start up the self-diagnostic function again and select this
menu.
N1-1. IP ADDRESS CHECK

This menu is used to check that IP address can be obtained.
N1-1
IP AD CHK:OK
OK: Connected (IP address obtained)
NG: No traffic / Disconnected
RX-A830
N1-2. MAC ADDRESS CHECK

This menu is used to check that MAC address is written.
N1-2
MAC AD CHK:OK
OK: Normal
NG: Unwritten
38
RX-A830
N1-3. LINE NOISE 100 MDI

Not for service.
N1-3
LN MDI 100
N1-4. LINE NOISE 100 MDIX

Not for service.
N1-4
LN MDIX 100
N1-5. LINE NOISE 10 MDI

Not for service.
N1-5
LN MDI 10
N1-6. LINE NOISE 10 MDIX

Not for service.
N1-6
LN MDIX 10
N1-7. EXT TEST

Transmission/reception of the NETWORK jack is checked.
With the power turned off, short the pins of the NETWORK jack as shown in the figure below.
Start up the self-diagnostic function and select this menu.
Transmission/reception test is executed and its result is displayed.
Note: Be sure to return the shorted pins to their original condition after executing this test.
N1-7
8 7 6 5 4 3 2 1
EXT TEST:OK
OK: Normal
NG: Abnormal
--: Checking
NETWORK jack
RX-A830
N1-8. MAC ADDRESS

Written MAC address is displayed.
N1-8
00A0DExxxxxx
39
RX-A830
C1. DIGITAL P.C.B. CHECK

This menu is used to check the communication and bus line connection between devices on DIGITAL P.C.B.
C1-1. ALL
The synthetic judgment result of sub-menu C1-2 to C1-9 is displayed.
C1-1
ALL:OK Ext.JIG
When test result using the “C1-9. RS-232C LOOPBACK
TEST” menu is NG, the sub-menu C1-9 is NG, “Ext.
JIG” is displayed.
OK: No error detected

NG: An error is detected
--: Checking
C1-2. BUS FLASH ROM

FLASH ROM (IC77)’s reading/writing are checked.
C1-2
BUS_FROM:OK
C1-3. BUS FPGA

Communication and bus line connection between microprocessor (IC83) and FPGA (IC50) are checked.
C1-3
BUS_FPGA:OK
C1-4. I2C
The I2C (Inter integrated circuit) bus line connection is checked.
C1-4
000-00 0 0-0 0 : No error detected
1 : An error is detected
Error detection of VIDEO P.C.B.

Error detection of Video decoder (IC21)
RX-A830
Error detection of Front HDMI equalizer (IC423)

Error detection of HDMI transmitter 2 (IC62)
Error detection of HDMI transmitter 1 (IC61)
Error detection of HDMI receiver (IC3)

Error detection of HDMI switcher 2 (IC2)
Error detection of HDMI switcher 1 (IC1)
40
RX-A830
C1-5. FPGA RAM

SDRAM (IC53)’s reading/writing are checked.
C1-5
FPGA_RAM:OK
C1-6. BUS DIR

Communication and bus line connection between microprocessor (IC83) and DIR (IC924) are checked.
C1-6
DIR BUS:OK
C1-7. BUS DSP

Communication and bus line connection between microprocessor (IC83) and DSP (IC921) are checked.
C1-7
DSP BUS:OK
C1-8. EEPROM
EEPROM (IC82)'s reading is checked.
C1-8
EEPROM:OK
C1-9. RS-232C LOOPBACK TEST

Not for service.
C1-9
232C DATA:NG
C1-10. INVALID ITEM

RX-A830
Not for service.
C1-10
INVALID ITEM
41
RX-A830
C2. NETWORK IC CHECK

This menu is used to check the communication and bus line connection between devices related to network.
C2-1. ALL
The synthetic judgment result of sub-menu C2-2 to C2-5 is displayed.
C2-1
ALL:OK Ext.JIG
When test result using the “C2-2. LINK CHECK” menu is
NG, the sub-menu C2-2 is NG, “Ext. JIG” is displayed.
--: Checking
C2-2. LINK CHECK

LAN cable connection is checked.
Connect between NETWORK jack of this unit and LAN port of broadband router with a network cable.
* When the network condition varies while sub-menu is displayed (e.g., the network is deactivated once), the
correct result will not be displayed. In that case, once turn off the power to this unit, then start up the self-
diagnostic function again and select this menu.
C2-2
LINK CHK:OK
OK: Normal
NG: Disconnected
--: Checking
C2-3. PHY (Ethernet PHYceiver) TEST

Communication and bus line connection between PHY (IC955) and NETWORK microprocessor (IC951) are
checked.
C2-3
PHY TEST:OK
--: Checking
C2-4. BUS RAM

RX-A830
Communication and bus line connection between SDRAM (IC952) and NETWORK microprocessor (IC951) are
checked.
C2-4
RAM BUS:OK
--: Checking
42
RX-A830
C2-5. APL (Apple) ID CHECK

Apple authentication IC (IC956) device ID is checked.
C2-5
APL ID:OK
--: Checking
V1. ANALOG VIDEO CHECK

This menu is used to check the analog video signal route.
V1-1. ANALOG BYPASS

The video signal is converted and output as shown below.
V1-1
ANALOG BYPASS
ANALOG BYPASS
HDMI IN HDMI OUT
DIGITAL DIGITAL
DIGITAL
IC3 IC61
IC50
HDMI HDMI
FPGA
Receiver Transmitter
Component In DIGITAL Component Out

IC21
VIDEO
Decoder
OPERATION
IC341
Video
Selector
Composite In Composite Out
V1-2. INVALID ITEM

Not for service.
V1-2
INVALID ITEM
RX-A830
V1-3. INVALID ITEM

Not for service.
V1-3
INVALID ITEM
43
RX-A830
V1-4. MUTE CHECK

The video signal is muted.
V1-4
MUTE CHECK
MUTE CHECK
HDMI IN HDMI OUT
DIGITAL DIGITAL
DIGITAL
IC3 IC61
IC50
HDMI HDMI
FPGA
Receiver Transmitter
Component In DIGITAL Component Out

IC21
MUTE
VIDEO VDEC_N_RST
Decoder
OPERATION
IC341
Video
Selector
Composite In Composite Out
V1-5. TEST PATTERN

Not for service.
V1-5
TEST PATTERN
V1-6. VIDEO INFORMATION

The information of input analog video signals is displayed.
V1-6
VID IN:480i60
RX-A830
44
RX-A830
V2. DIGITAL VIDEO CHECK

This menu is used to check the digital video signal route.
V2-1. LOOPBACK TEST 1

Execute the test for all HDMI IN jacks by repeating the procedure below.
1. Select sub-menu other than V2-1.
2. Connect between any of the HDMI IN jacks and HDMI OUT 1 jack with an HDMI cable.
3. Select V2-1. The test result is displayed in a few seconds.
V2-1
TEST1:OK
--: Checking
HDMI Cable for Loopback
CB421 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB62 CB61
HDMI IN HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI
Front-HDMI-Board
Front IN7 IN6 IN5 IN4 IN3 IN2 IN1 OUT2 OUT1
IC423 IC62 IC61

HDMI EQUALIZER HDMI HDMI
Sii9587CNUC-3 IC53 TRANSMITTER 2 TRANSMITTER 1
128Mbit Sii9136CTU-3 Sii9136CTU-3
IC2 IC1 SDRAM
HDMI SWITCHER 2 HDMI SWITCHER 1
Sii9589-3CTUC Sii9589-3CTUC
IC50
FPGA
EP4CE15F23C6N
IC3
HDMI RECEIVER
ADV7619KSVZ
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
RX-A830
45
RX-A830

HDMI receiver IC (IC3) is checked.
2. Connect between any of the HDMI IN jacks and HDMI OUT jack with an HDMI cable.
3. Select the input source corresponding to the connected HDMI IN jack by using “INPUT” knob.
Select the input source Result
HDMI1 V-AUX V2-2

TEST2:OK
--: Checking
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
IC50 4K test pattern

FPGA
EP4CE15F23C6N
IC3
HDMI RECEIVER
ADV7619KSVZ
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
RX-A830
46
RX-A830

HDMI transmitter 1 IC (IC61) is checked.
HDMI1 V-AUX V2-3

TEST3:OK
--: Checking
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
IC50 1080@60Hz 12bit

FPGA
EP4CE15F23C6N
IC3
HDMI RECEIVER
ADV7619KSVZ
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
RX-A830
47
RX-A830

HDMI transmitter 2 IC (IC62) is checked.
HDMI1 V-AUX V2-4

TEST4:OK
--: Checking
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
IC50 1080@60Hz 12bit

FPGA
EP4CE15F23C6N
IC3
HDMI RECEIVER
ADV7619KSVZ
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
V2-5. INVALID ITEM

Not for service.
V2-5
INVALID ITEM
RX-A830
V2-6. INVALID ITEM

Not for service.
V2-6
INVALID ITEM
48
RX-A830
V2-7. HDMI REPEAT

The video/audio signals input to HDMI IN jack are output to HDMI OUT jack.
V2-7
HDMI REPEAT **
The Deep Color video signals is input, “30” bit or
“36” bit is displayed.
HDMI output TV
HDMI
HDMI
BD/DVD player
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
IC50
FPGA
EP4CE15F23C6N
IC3
HDMI RECEIVER
ADV7619KSVZ
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
V2-8. DIGITAL CVBS

The video (CVBS) signal is converted and output as shown below.
V2-8 TV
DIGITAL CVBS HDMI
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
RX-A830
IC50
Video output FPGA
VIDEO EP4CE15F23C6N
IC3
HDMI RECEIVER
ADV7619KSVZ
BD/DVD player
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
49
RX-A830
V2-9. INVALID ITEM

Not for service.
V2-9
INVALID ITEM
V2-10. DIGITAL COMPONENT

The component video (Y, Cb, Cr) signal is converted and output as shown below.
V2-10
DIGITAL Cmp
TV
HDMI
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
Component video output
COMPONENT
IC50
FPGA
EP4CE15F23C6N
IC3
HDMI RECEIVER
ADV7619KSVZ
BD/DVD player
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
RX-A830
50
RX-A830
V2-11. DIGITAL COMPONENT SC

The component video (Y, Cb, Cr) signal is converted and output as shown below.
HDMI video output up-scaling: 480i/p, 576i/p only => 1080p
V2-11 TV
DIGITAL Cmp SC HDMI
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
Component output
COMPONENT
IC50
FPGA
EP4CE15F23C6N
IC3
HDMI RECEIVER
ADV7619KSVZ
BD/DVD player
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
V2-12. GUI (Graphical User Interface)-VIDEO OUT

The GUI is output from FPGA (IC50 on DIGITAL P.C.B.).
V2-12 TV
GUI-VIDEO OUT HDMI
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
IC50
FPGA
RX-A830
EP4CE15F23C6N
IC3 GUI
HDMI RECEIVER
ADV7619KSVZ
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
51
RX-A830
V3. TEST PATTERN

The video signal is output to HDMI OUT jack with its resolution converted as shown below.
TV
HDMI
Front-HDMI-Board
IC423 IC62 IC61

IC2 IC1 SDRAM
IC50
FPGA
EP4CE15F23C6N
IC3 GUI
HDMI RECEIVER
ADV7619KSVZ
Y,CbCr IC21
Y,C VIDEO DECODER
CVBS ADV7180BSTZ
V3-1. 480i V3-2. 480p V3-3. 720p 60Hz V3-4. 1080i 60Hz
V3-1 V3-2 V3-3 V3-4
480i 480p 720p 60 1080i 60
V3-5. 1080p 60Hz V3-6. 576i V3-7. 576p V3-8. 720p 50Hz
V3-5 V3-6 V3-7 V3-8
1080p 60 576i 576p 720p 50
V3-9. 1080i 50Hz V3-10. 1080p 50Hz V3-11. 1080p 24Hz V3-12. 1080p 24Hz 3D/FP
V3-9 V3-10 V3-11 V3-12
1080i 50 1080p 50 1080p 24 1080p 24 3D/FP
(FP: Frame Packing)
V3-13. 720p 60Hz 3D/FP V3-14. 720p 50Hz 3D/FP V3-15. 1080i 60Hz 3D/FP V3-16. 1080i 60Hz 3D/SS
V3-13 V3-14 V3-15 V3-16
720p 60 3D/FP 720p 50 3D/FP 1080i 60 3D/FP 1080i 60 3D/SS
(SS: Side-by-Side)
V3-17. 1080i 50Hz 3D/SS V3-18. 720p 60Hz 3D/TB V3-19. 720p 50Hz 3D/TB V3-20. 1080p 24Hz 3D/TB
RX-A830
V3-17 V3-18 V3-19 V3-20

1080i 50 3D/SS 720p 60 3D/TB 720p 50 3D/TB 1080p 24 3D/TB
(TB: Top-and-Bottom)
V3-21. 4k 24Hz
V3-21
4k 24
(4k: Digital cinema 4K, Resolution 3996 × 2160p)
52
RX-A830
T1. TROUBLE SHOOTING INFORMATION

This menu is used to display the operating time and operation frequency of this unit.
* The operating time and operation frequency during the self-diagnostic function mode will not be stored.
T1-1. OPERATING TIME

The operating time of this unit is displayed.
The operating time will be erased by pressing the “STRAIGHT” key.
T1-1
0000D 00H 00M
Minute (0M to 59M)
Hour (0H to 23H)
Day (0D to 9999D)
T1-2. POWER-RELAY ON
The operation frequency of the power relay (RY371) is displayed in hexadecimal notation.
The operation frequency will be erased by pressing the “STRAIGHT” key.
T1-2
PR-ON Num:0000
Operation frequency / 0 to FFFF (up to 65,535 times)
T1-3. POWER AMP B

The operation frequency of the POWER AMP B relay (RY101) is displayed in hexadecimal notation.
The operation frequency will be erased by pressing the “STRAIGHT” key.
T1-3
P-AMP B Num:00
Operation frequency / 0 to FF (up to 255 times)
T1-4. OUTPUT LEVEL

The maximum value of the speaker output level is displayed in hexadecimal notation.
The maximum value will be erased by pressing the “STRAIGHT” key.
T1-4
OUTLVL MAX:00
Maximum value / 0 to FF
T1-5. POWER OFF TIME-OUT

The number of time-out times of each module when the power is turned off will be displayed in hexadecimal
notation.
RX-A830
All the number of time-out times will be erased by pressing the “STRAIGHT” key.
T1-5
TO: 0/ 0/ 0/ 0 0 to FF (up to 255 times)
VIDEO
NET
HDMI
Power relay
53
RX-A830
T2. USAGE ENVIRONMENT

This menu is used to display the maximum level of the MAIN ZONE / ZONE 2 volume and the maximum value of the
detected heatsink temperature when this unit is operated.
* The maximum level of the MAIN ZONE / ZONE 2 volume and the maximum value of the detected heatsink temperature
during the self-diagnostic function mode will not be stored.
T2-1. MAIN ZONE HIGHEST VOLUME

The maximum value of the MAIN ZONE volume level maintained for longer than 1 minute is displayed.
The maximum value of the MAIN ZONE volume level will be erased by pressing the “STRAIGHT” key.
T2-1
MAIN VOL:-----
Maximum value / -80.0 to +16.5 dB
T2-2. ZONE 2 HIGHEST VOLUME

The maximum value of the ZONE 2 volume level maintained for longer than 1 minute is displayed.
The maximum value of the ZONE 2 volume level will be erased by pressing the “STRAIGHT” key.
T2-2
Z2 VOL: -----
Maximum value / -80.0 to +16.5 dB
T2-3. INVALID ITEM

Not for service.
T2-3
INVALID ITEM
T2-4. THM1/THM2 HIGHEST TEMPERATURE

The minimum value of the detected heatsink temperature is displayed in hexadecimal notation.
The minimum value of the detected heat sink temperature will be erased by pressing the “STRAIGHT” key.
Normal value
THM1: 51 to FF
THM2: 51 to FF
T2-4
TMa MIN:6F/68 Heatsink temperature / 0 (High) to FF (Low)
THM2
THM1
RX-A830
T2-5. THM3/THM4 HIGHEST TEMPERATURE

Not for service.
T2-5
TMb MIN:--/--
54
RX-A830
T3. EXTERNAL EVENT

This menu is used to display the history of key operation.
* No matter how many times the same key is pressed, it will be stored only once as its history.
* The key operation during the self-diagnostic function mode will not be stored.
All history of key operation will be erased by pressing the “STRAIGHT” key.
* Numeric values in the figure are given as reference only.
T3-1. HISTORY 1 T3-2. HISTORY 2 T3-3. HISTORY 3 T3-4. HISTORY 4

T3-1 T3-2 T3-3 T3-4
0205-BE-FF-FF 7A -84 7A -AA 7A -9D
T3-5. HISTORY 5 T3-6. HISTORY 6 T3-7. HISTORY 7 T3-8. HISTORY 8

T3-5 T3-6 T3-7 T3-8
7A -AA 7A -DE 7A -9C 7A -9D
RX-A830
55
RX-A830
List of key operation
Display
Key name
Key number AD value 1 AD value 2 AD value 3
0205 B5 – C5 FF FF MAIN ZONE
0208 60 – 76 FF FF ZONE 2
020F FF BA – CD FF MAIN ZONE + STRAIGHT (Advanced setup mode)
0211 xx FF FF HD Radio CDM mode (U model)
0212 xx FF FF HD Radio SPLIT mode (U model)
0300 37 – 4B FF FF SCENE 1 (BD/DVD)
0301 21 – 36 FF FF SCENE 2 (TV)
0302 0C – 20 FF FF SCENE 3 (NET)
0303 00 – 0B FF FF SCENE 4 (RADIO)
0500 FF CE – E1 FF PROGRAM
0501 FF E2 – F5 FF PROGRAM
0530 FF BA – CD FF STRAIGHT
0533 FF 00 – 0B FF PURE DIRECT
0800 C6 – E5 FF FF TONE CONTROL
0A00 FF A6 – B9 FF INFO
0C00 4C – 5F FF FF ZONE CONTROL
2C00 FF 0C – 20 FF TUNING
2C01 FF 21 – 36 FF TUNING
2C02 FF 37 – 4D FF AM
2C03 FF 4E – 62 FF FM
2C04 FF 63 – 78 FF PRESET
2C05 FF 79 – 8F FF PRESET
2C06 FF 90 – A5 FF MEMORY
0101 VOLUME knob (–)
0102 VOLUME knob (+)
0103 INPUT knob (–)
0104 INPUT knob (+)
7A xxxx * For the details of the remote control key display, refer to
7E xxxx “REMOTE CONTROL”.
RX-A830
56
RX-A830
T4. INTERNAL INFORMATION
T4-1. DSP INFORMATION

This menu is used to display the DSP information stored in memory as backup data before rebooting.
The DSP information will be erased by pressing the ‘STRAIGHT “ key.
T4-1
DSP:--/--/-- --: Not stored
Decode format
Channels
Sampling frequency
Sampling frequency Channels Decode format
Display Sampling frequency [kHz] Display Channels Display Decode format

0 32 0 Dual Mono 0 Analog
1 44.1 1 1/0 1 PCM
2 48 2 2/0 2 Dolby Digital
3 64 3 3/0 3 Dolby Digital EX
4 88.2 4 2/1 4 DTS
5 96 5 3/1 5 DTS 9624
6 128 6 2/2 6 DTS ES Matrix
7 176.4 7 3/2 7 DTS ES Discrete
8 192 8 2/3 8 DTS 96 ES Matrix
10 8 9 3/3 9 AAC
11 11 10 2/4 10 DSD
12 12 11 3/4 11 Multi PCM
13 16 12 HD Multi channel 12 Dolby Digital Plus
14 22.05 13 “Unknown” 13 Dolby Digital Plus EX
15 24 14 Dolby True HD
16 “Unknown” 15 Dolby True HD EX
16 DTS Express
17 DTS HD
18 DTS HD Master Audio
19 Digital
20 MP3
21 WMA
22 FLAC
25 “Unknown”
T4-2. BU ERROR
Not for service.
T4-2
BU ERR:-255
T4-3. NRC (Net Restart Counter)

Not for service.
RX-A830
T4-3
NRC: 0
T4-4. INVALID ITEM

Not for service.
T4-4
INVALID ITEM
57
RX-A830
P1. SYSTEM MONITOR

This menu is used to display the A/D conversion value of the microprocessor which detects panel keys and protection
functions by using the sub-menu.
When “P1-8. KEY” sub-menu is selected, keys become inoperable due to detection of the values of all keys.
However, it is possible to advance to the next menu by pressing the “SCENE RADIO” (forward) key or “SCENE NET”
(reverse) key on the remote control.
P1-1. DC
Power amplifier DC (DC voltage) output is detected.
The voltage at 5 pin (DC_PRT) of IC78 is displayed.
Normal value: 32 to 74
* If DC becomes out of the normal value range, the protection function works to turn off the power.
P1-1
DC: 50
P1-2. PS
Power supply voltage (PS) protection detection.
The voltage at 2 pin (PS1_PRT)/1 pin (PS2_PRT)/13 pin (PS3_PRT) of IC78 are displayed.
Voltage detects
PS1: AC12, ACBL
PS2: ±7, 12V, +5A, +5T, -VP, -3.3V
PS3: +5.5
Normal value
PS1: 51 to 179
PS2: 92 to 147 (PURE DIRECT mode: 139 to 193)
PS3: 132 to 168
* If PS1, PS2 or PS3 becomes out of the normal value range, the protection function works to turn off the
power.
P1-2
PS:115/118/154
PS3
PS2
PS1
RX-A830
58
RX-A830
P1-3. THM
Temperature of the heatsink (THM) is detected.
The voltage at 12 pin (THM1) of IC78/1 pin (THM2) of IC76 are displayed.
Normal value
THM1: 42 to 255
THM2: 42 to 255 (U, C models)
* If THM1 or THM2 becomes out of the normal value range, the protection function works to turn off the power.
P1-3
TMa:110 / 103
THM2
THM1
P1-4. INVALID ITEM

Not for service.
P1-4
INVALID ITEM
P1-5. OUTPUT LEVEL

Output level of speaker output is detected.
The voltage at 4 pin (AMP_OLV) of IC78 is displayed.
P1-5
OUTLVL: 255
P1-6. LIMITER CONTROL

Power limiter control is detected.
The voltage at 4 pin (AMP_LMT) of IC83 is displayed.
P1-6
LMTCNT: 255
RX-A830
P1-7. L3 (J model)
Not for service.
P1-7
L3: 0
59
RX-A830
P1-8. KEY
Panel key is detected.
When the A/D conversion value of the panel key becomes out of the specified range, normal operation will not
be available.
In that case, check the constant of voltage dividing resistor, solder condition, etc. Refer to table.
* When “P1-8. KEY” menu is selected, keys become inoperable due to detection of the values of all keys.
However, it is possible to advance to the next menu by pressing the “SCENE RADIO” (forward) key or “SCENE
NET” (reverse) key on the remote control.
P1-8
KY: 255 / 255
KEY2
KEY1
Display KEY1 Display KEY2

RADIO PURE
0 – 11 0 – 11
(SCENE4) DIRECT
NET TUNING
12 – 32 12 – 32
(SCENE3) >>
TV TUNING
33 – 54 33 – 54
(SCENE2) <<
BD/DVD
55 – 75 55 – 77 AM
(SCENE1)
ZONE
76 – 96 78 – 99 FM
CONTROL
PRESET
97 – 119 ZONE2 100 – 121
>
PRESET
120 – 142 – 122 – 144
<
143 – 172 – 145 – 166 MEMORY
MAIN ZONE
173 – 202 167 – 186 INFO
TONE
203 – 235 187 – 205 STRAIGHT
CONTROL
PROGRAM
255 Key off 206 – 226
>
PROGRAM
227 – 246
<
255 Key off
P1-9. USB-VBUS
Not for service.
RX-A830
P1-9
USB-VBUS: 4
60
RX-A830
P2. PROTECTION HISTORY

This menu is used to display the history of protection function.
All history of protection function will be erased by pressing the “STRAIGHT” key.
P2-1 P2-1. History 1

1st:PS2 000L
H: Displayed when the voltage is HIGHER than upper limit.
L: Displayed when the voltage is LOWER than lower limit.
xxx: A/D conversion value of voltage at the moment when the protection function
worked.

2nd:TMP1 000L

3rd:DC 000L

NoPrt
S1. FIRMWARE UPDATE

Not for service.
S1-1
F/W UPDATE?
RX-A830
61
RX-A830
S2. SET INFORMATION

The model name and destination of this unit are displayed.
S2-1. MODEL
The model name of this unit is displayed.
S2-1
MDL:A830 255
Not for service.
Model name
A830 : RX-A830
S2-2. DESTINATION
The destination of this unit is displayed.
S2-2
DEST:U 27
A/D conversion value
Destination
Destination J U C R (R, S) T K A BG (B, G, F) L

A/D conversion value
0 − 12 13 − 39 40 − 67 68 − 92 93 − 115 116 − 140 141 − 169 199 − 221 222 − 244
(3.3 V=255)
S3. FACTORY PRESET

This menu is used to reserve/inhibit initialization of the back-up IC (EEPROM: IC82 on DIGITAL P.C.B.).
S3-1 S3-1. PRESET INHIBIT (Initialization inhibited)

PRESET:INH Initialization of the back-up IC is not executed. Select this sub-menu to protect the values set by the user.
S3-1 S3-1. PRESET RESERVED (Initialization reserved)

PRESET:RSRV Initialization of the back-up IC is reserved. (Actual initialization is executed when the power is turned on
next.) To reset to the original factory settings or to reset the backup IC, select this sub-menu and press
the “MAIN ZONE ” key to turn off the power.
RX-A830
CAUTION: Before setting to the PRESET RESERVED, write down the existing preset memory content of the tuner. (This
is because setting to the PRESET RESERVED will cause the user memory content to be erased.)
62
RX-A830
S4. ROM VERSION/CHECKSUM

The firmware version and checksum values are displayed.
The checksum is obtained by adding the data at every 8-bit and expressing the result as a hexadecimal notation.
S4-1 S4-1. SYSTEM VERSION

SYS-VER. 1.01 The firmware version is displayed.
S4-2 S4-2. MICROPROCESSOR VERSION

VER.00028 The firmware version of MICROPROCESSOR (IC83 on DIGITAL (1) P.C.B.) is displayed.
S4-3 S4-3. MICROPROCESSOR CHECKSUM

SUM.36F8 The checksum value of MICROPROCESSOR (IC83 on DIGITAL (1) P.C.B.) is displayed.
S4-4 S4-4. FLASH ROM VERSION

FR-V.00029 The firmware version of FLASH ROM (IC77 on DIGITAL (1) P.C.B.) is displayed.
S4-5 S4-5. FLASH ROM CHECKSUM

FR-S.1B05 The checksum value of FLASH ROM (IC77 on DIGITAL (1) P.C.B.) is displayed.
S4-6 S4-6. NETWORK MICROPROCESSOR VERSION

S-VER.0028 The firmware version of Network microprocessor (IC951 on DIGITAL (1) P.C.B.) is displayed.
S4-7 S4-7. NETWORK MICROPROCESSOR CHECKSUM

S-SUM.E47680D8 The checksum value of Network microprocessor (IC951 on DIGITAL (1) P.C.B.) is displayed.
S4-8 S4-8. DSP1 VERSION

D1-V. 1.08r2 The firmware version of DSP1 (IC921 on DIGITAL (1) P.C.B.) is displayed.
S4-9 S4-9. DSP1 CHECKSUM

D1-S.FC6FA124 The checksum value of DSP1 (IC921 on DIGITAL (1) P.C.B.) is displayed.
S4-10 S4-10. INVALID ITEM

RX-A830

63
RX-A830
S4-12 S4-12. GUI VERSION

G-V.000000228 The firmware version of GUI data is displayed.
S4-13 S4-13. FPGA GUI VERSION

FPGA-G-V. 25 The firmware version of GUI section in FPGA (IC50 on DIGITAL (1) P.C.B.) is displayed.
S4-14 S4-14. FPGA SD (Standard Definition) VERSION

FPGA-S-V. 24 The firmware version of SD I/P scaler section in FPGA (IC50 on DIGITAL (1) P.C.B.) is displayed.
S4-15 S4-15. FPGA HD (High Definition) VERSION

FPGA-H-V. 11 The firmware version of HD I/P scaler section in FPGA (IC50 on DIGITAL (1) P.C.B.) is displayed.

RX-A830
64
RX-A830
■ POWER AMPLIFIER ADJUSTMENT

1. Right after power is turned on, confirm that the voltage across the terminals of R1152 (SURROUND BACK Rch), R1154
(SURROUND Rch), R1150 (FRONT Rch), R1148 (CENTER), R1149 (FRONT Lch), R1153 (SURROUND Lch) and R1151
(SURROUND BACK Lch) are within the confines of 0.1 mV to 10 mV.
2. If measured voltage exceeds 10 mV, open (cut off) R1104 (SURROUND BACK Rch), R1106 (SURROUND Rch), R1102 (FRONT
Rch), R1100 (CENTER), R1101 (FRONT Lch), R1105 (SURROUND Lch) and R1103 (SURROUND BACK Lch), and then
reconfirm the voltage.
Attention
If the measured voltage exceeds 10 mV after repairing the power amplifier, check other parts again for any possible
defect before cutting the resistor.
3. Confirm that the voltage is within the confines of 0.2 mV to 15 mV after 60 minutes.
0.1 mV – 10 mV
(DC) Open (cut off)
R1104 (SURROUND BACK Rch)

R1106 (SURROUND Rch)
R1102 (FRONT Rch)
R1152 (SURROUND BACK Rch) R1100 (CENTER)
R1154 (SURROUND Rch) R1101 (FRONT Lch)
R1150 (FRONT Rch) R1105 (SURROUND Lch)
R1148 (CENTER) R1103 (SURROUND BACK Lch)
R1149 (FRONT Lch)
R1153 (SURROUND Lch)
R1151 (SURROUND BACK Lch)
Front side
R1154 R1153 R1152 R1151 R1150 R1149 R1148
R1102
R1105 R1104 R1101
R1106 R1103
R1100
RX-A830
MAIN (1) P.C.B.
65
RX-A830
■ DISPLAY DATA
● V3001 : 18-MT-11GNAK (OPERATION P.C.B.)
69 1
PATTERN AREA
● PIN CONNECTION
Pin No. 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
Connection F2 NX NP NP P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31
Pin No. 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Connection P32 P33 P34 P35 P36 NX NX NX NX NX NX NX 18G 17G 16G 15G 14G 13G 12G 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G NP NP NX F1
Note : 1) F1, F2 ..... Filament pin 2) NP ..... No pin 3) NX ..... No extend pin 4) 1G-18G ..... Grid pin
● GRID ASSIGNMENT
18G 17G 16G 17G 15G

S8 S9 S15 S5 S7 S5
1a 2a 1a 2a 1a 2a 1a 2a
S12 S10 S11 S6 S13

1G 2G 3G 4G 5G 6G 7G 8G 9G 10G 11G 12G 13G 14G
a
a S2
1-1 2-1 3-1 4-1 5-1
j
1-2 2-2 3-2 4-2 5-2 S3
f b f b
h k 1-3 2-3 3-3 4-3 5-3 S3
g m S4
S2
r n 1-4 2-4 3-4 4-4 5-4
g
e c e c
p 1-5 2-5 3-5 4-5 5-5
1-6 2-6 3-6 4-6 5-6

RX-A830
d d
(18G–16G) 1-7 2-7 3-7 4-7 5-7

(15G)
S1
(1G–14G)
66
RX-A830
● ANODE CONNECTION
18G 17G 16G 15G 1G-14G
P1 1a 1a 1a S5 1-1
P2 1h 1h 1h S7 2-1
P3 1j 1j 1j 1d 3-1
P4 1k 1k 1k 2d 4-1
P5 1b 1b 1b S2 5-1
P6 1f 1f 1f 1e 1-2
P7 1m 1m 1m 2e 2-2
P8 1g 1g 1g S3 3-2
P9 1c 1c 1c 1c 4-2
P10 1e 1e 1e 2c 5-2
P11 1r 1r 1r S4 1-3
P12 1p 1p 1p 1g 2-3
P13 1n 1n 1n 2g 3-3
P14 1d 1d 1d 1f 4-3
P15 2a 2a 2a 2f 5-3
P16 2h 2h 2h 1b 1-4
P17 2j 2j 2j 2b 2-4
P18 2k 2k 2k 1a 3-4
P19 2b 2b 2b 2a 4-4
P20 2f 2f 2f 5-4
P21 2m 2m 2m 1-5
P22 2g 2g 2g 2-5
P23 2c 2c 2c 3-5
P24 2e 2e 2e 4-5
P25 2r 2r 2r 5-5
P26 2p 2p 2p 1-6
P27 2n 2n 2n 2-6
P28 2d 2d 2d 3-6
P29 S8 4-6
P30 S9 5-6
P31 S6 1-7
P32 S13 2-7

RX-A830
P33 S15 3-7
P34 S12 4-7
P35 S10 5-7
P36 S11 – S1
67
RX-A830
■ IC DATA
IC921: D80YK113CPTP400 (DIGITAL (1) P.C.B.)
DSP (Digital signal processor)
JTAG Interface DSP Subsystem
System Control
C674xTM
DSP MICRO-
PLL/Clock PROCESSOR
Input Generator
Clock(s) w/OSC Memory Protection
I/O Protection AET
General-
Purpose 32 KB 32 KB
Timer L1 Pgm L1 RAM
Power/Sleep
General- Controller
Purpose 256 KB L2 RAM
Timer RTC/ Pin
(Watchdog) 32-KHz Multiplexing 1024 KB L2 ROM
OSC
Switched Control Resource (SCR)
Peripherals
DMA Audio Ports Serial Interface
GPIO
EDMA3 dMAX McASP I2C SPI UART
w/FIFO
Control Timers Shared Memory
128 KB
eHRPWM eCAP eQEP RAM
Connectivity External Memory Interface
USB2.0 MMC/SD EMIFA(8b/16b) EMIFB

OTG Ctlr HPI (8b) NAND/Flash SDRAM Only
PHY 16b SDRAM (16b/32b)
125 AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
130 ACLKR0/ECAP1/APWM1/GP2[15]
126 ACLKX0/ECAP0/APWM0/GP2[12]
123 UART1_TXD/AXR0[10]/GP3[10]
132 AMUTE1/EHRPWMTZ/GP4[14]
129 AHCLKR0/GP2[14]/BOOT[11]
122 UART1_RXD/AXR0[9]/GP3[9]
124 AXR0[11]/AXR2[0]/GP3[11]
127 AFSX0/GP2[13]/BOOT[10]
118 AXR0[6]/ACLKR2/GP3[6]
112 AXR0[1]/ACLKX2/GP3[1]
116 AXR0[4]/AXR2[1]/GP3[4]
115 AXR0[3]/AXR2[2]/GP3[3]
113 AXR0[2]/AXR2[3]/GP3[2]
111 AXR0[0]/AFSR2/GP3[0]
117 AXR0[5]/AFSX2/GP3[5]
105 EMB_A[10]/GP7[12]
EMB_A[11]/GP7[13]
EMB_A[12]/GP3[13]
107 EMB_BA[0]/GP7[1]
106 EMB_BA[1]/GP7[0]
EMB_A[8]/GP7[10]
EMB_A[9]/GP7[11]
103 EMB_A[0]/GP7[2]
102 EMB_A[1]/GP7[3]
101 EMB_A[2]/GP7[4]
100 EMB_A[3]/GP7[5]
EMB_A[4]/GP7[6]
EMB_A[5]/GP7[7]
EMB_A[6]/GP7[8]
EMB_A[7]/GP7[9]
121 AXR0[8]/GP3[8]
120 AXR0[7]/GP3[7]
131 AFSR0/GP3[12]
108 EMB_CS[0]
110 EMB_RAS
128 DVDD
119 DVDD
114 CVDD
109 DVDD
104 CVDD
DVDD
CVDD
DVDD
99
98
97
96
95
94
93
92
91
90
89
RSV2 133 88 EMB_SDCKE

USB0_VDDA12 134 87 DVDD
USB0_VDDA18 135 86 EMB_CLK
NC 136 85 EMB_WE/DQM[1]/GP5[14]
USB0_DP 137 84 EMB_D[8]/GP6[8]
USB0_DM 138 83 EMB_D[9]/GP6[9]
NC 139 82 EMB_D[10]/GP6[10]
USB0_VDDA33 140 81 DVDD
PLL0_VDDA 141 80 EMB_D[11]/GP6[11]
PLL0_VSSA 142 79 EMB_D[12]/GP6[12]
OSCIN 143 78 EMB_D[13]/GP6[13]
OSCVSS 144 77 CVDD
OSCOUT 145 76 EMB_D[14]/GP6[14]
RESET 146 75 DVDD
CVDD 147 74 EMB_D[15]/GP6[15]
RTC_XI 148 73 EMB_D[0]/GP6[0]
RTC_CVDD 149 72 EMB_D[1]/GP6[1]
TRST 150 71 DVDD
DVDD 151 70 EMB_D[2]/GP6[2]
TMS 152 69 CVDD
TDI 153 68 EMB_D[3]/GP6[3]
CVDD 154 67 CVDD
TCK 155 66 EMB_D[4]/GP6[4]
TDO 156 65 DVDD
GP7[14] 157 64 EMB_D[5]/GP6[5]
DVDD 158 63 EMB_D[6]/GP6[6]
CVDD 159 62 EMB_D[7]/GP6[7]
AHCLKX1/EPWMQB/GP3[14] 160 61 CVDD
CVDD 161 60 EMB_WE_DQM[0]/GP5[15]
ACLKX1/EPWMQA/GP3[15] 162 59 EMB_WE
AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10] 163 58 DVDD
DVDD 164 57 EMB_CAS
ACLKR1/ECAP2/APWM2/GP4[12] 165 56 CVDD
AFSR1/GP4[13] 166 55 EMA_WE]/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
CVDD 167 54 EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
AXR1[8]/EPWM1A/GP4[8] 168 53 DVDD
AXR1[7]/EPWM1B/GP4[7] 169 52 EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
AXR1[6]/EPWM2A/GP4[6] 170 51 EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
AXR1[5]/EPWM2B/GP4[5] 171 50 CVDD
RX-A830
DVDD 172 49 EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]

AXR1[4]/EQEP1B/GP4[4] 173 48 EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
AXR1[3]/EQEP1A/GP4[3] 174 47 DVDD
AXR1[2]/GP4[2] 175 46 EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
AXR1[1]/GP4[1] 176 45 EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
EMA_A[3]/GP1[3] 32
DVDD 33
EMA_A[4]/GP1[4] 34
EMA_A[5]/GP1[5] 35
EMA_A[6]/GP1[6] 36
EMA_A[7]/GP1[7] 37
CVDD 38
EMA_A[8]/GP1[8] 39
EMA_A[9]/GP1[9] 40
41
42
43
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44
1
2
3
4
5
6
7
8
9
DVDD
CVDD
DVDD
CVDD
DVDD
EMA_BA[0]/GP1[14]
EMA_BA[1]/UHPI_HHWIL/GP1[13]
EMA_A[10]/GP1[10]
CVDD
EMA_A[0]/GP1[0]
EMA_A[11]/GP1[11]
EMA_A[12]/GP1[12]
DVDD
AXR1[0]/GP4[0]
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
AXR1[10]/GP5[10]
AXR1[11]/GP5[11]
SPI1_ENA/UART2_RXD/GP5[12]
SPI1_SCS[0]/UART2_TXD/GP5[13]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
SPI0_CLK/EQEP1I/GP5[2]BOOT[2]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI1_SOMI[0]/I2C1/SCL/GP5[5]BOOT[5]
SPI1_SIMO[0]/I2C1/SDA/GP5[6]BOOT[6]
SPI1_CLK/EQEP1S/GP5[7]BOOT[7]
SPI0_SOMI[0]/EQEP0I/GP5[0]BOOT[0]
SPI0_SIMO[0]/EQEP0S/GP5[1]BOOT[1]
EMA_WAIT[0]/UHPI_HRDY/GP2[10]
EMA_CS[3]/AMUTE2/GP2[6]
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
EMA_A[1]/MMCSD_CLK/UHPI/HCNTL0/GP1[1]
EMA_A[2]/MMCSD_CMD/UHPI/HCNTL1/GP1[2]
68
RX-A830
Pin TYPE PULL

Function Name Detail of Function
No. (1) (2)
1 AXR1[0]/GP4[0] I/O IPD McASP1 serial data
2 UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/ I IPU BOOT[8]
BOOT[8] I IPU UART0 receive data
I/O IPU I2C0 serial data
I IPU Timer0 lower input
3 UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/ I IPU BOOT[9]
BOOT[9] O IPU UART0 transmit data
I/O IPU I2C0 serial clock
O IPU Timer0 lower output
4 AXR1[10]/GP5[10] I/O IPU McASP1 serial data
5 DVDD (I/O supply) PWR 3.3-V I/O supply voltage pins
7 SPI1_ENA /UART2_RXD/GP5[12] I/O IPU SPI1 enable
I IPU UART2 receive data
8 SPI1_SCS[0] /UART2_TXD/GP5[13] I/O IPU SPI1 chip select
O IPU UART2 transmit data
9 SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4] I/O IPU SPI0 chip select
I IPU eQEP0B quadrature input
I IPU BOOT[4]
O IPU UART0 ready-to-send output
10 CVDD (Core supply) PWR 1.2-V core supply voltage pins
11 SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] I/O IPD SPI0 clock
I IPD eQEP1 index
I IPD BOOT[2]
12 SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3] I/O IPU SPI0 enable
I IPU eQEP0A quadrature input
I IPU BOOT[3]
I IPU UART0 clear-to-send input
13 SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] I/O IPU SPI1 data/slave-out-master-in
I IPU BOOT[5]
I/O IPU I2C1 serial clock
14 SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] I/O IPU SPI1 data/slave-in-master-out
I IPU BOOT[6]
I/O IPU I2C1 serial Data
16 SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] I/O IPD SPI1 clock
I IPD eQEP1 strobe
I IPD BOOT[7]
17 SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] I/O IPD SPI0 data/slave-out-master-in
I IPD eQEP0 index
I IPD BOOT[0]
18 SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] I/O IPD SPI0 data/slave-in-master-out
I IPD eQEP0 strobe
I IPD BOOT[1]
19 EMA_WAIT[0]/ UHPI_HRDY/GP2[10] I IPU EMIFA wait input/interrupt
I/O IPU UHPI ready
21 EMA_CS[3] /AMUTE2/GP2[6] O IPU EMIFA Async chip select
O IPU McASP2 mute output
22 EMA_OE /UHPI_HDS1/AXR0[13]/GP2[7] O IPU EMIFA output enable
RX-A830
I/O IPU UHPI data strobe

23 EMA_CS[2] /UHPI_HCS/GP2[5]/BOOT[15] O IPU EMIFA Async chip select
I IPU BOOT[15]
I/O IPU UHPI chip select
24 EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] I/O IPU McASP0 serial data
DVDD (I/O supply) PWR 3.3-V I/O supply voltage pins
25 EMA_BA[0]/ GP1[14] O IPU EMIFA bank address
26 EMA_BA[1]/ UHPI_HHWIL/GP1[13] O IPU EMIFA bank address
I/O IPU UHPI half-word identification control
69
RX-A830
Pin TYPE PULL

No. (1) (2)
27 EMA_A[10]/ GP1[10] O IPU EMIFA address bus
29 EMA_A[0]/ GP1[0] O IPD EMIFA address bus
30 EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] O IPU EMIFA address bus
I/O IPU UHPI access control
O IPU MMCSD_CLK
31 EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] O IPU EMIFA address bus
I/O IPU UHPI access control
I/O IPU MMCSD_CMD
44 EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/ I/O IPU EMIFA data bus
BOOT[12] I IPU BOOT[12]
I/O IPU UHPI data bus
I/O IPU MMC/SD data
45 EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] I/O IPU EMIFA data bus
I/O IPU MMC/SD data
I/O IPU MMC/SD data
I/O IPU MMC/SD data
I/O IPU MMC/SD data
I/O IPU MMC/SD data
I/O IPU MMC/SD data
54 EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/ I/O IPU EMIFA data bus
BOOT[13] I IPU BOOT[13]
I/O IPU MMC/SD data
RX-A830
55 EMA_WE /UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] O IPU EMIFA SDRAM write enable

I IPU BOOT[14]
I/O IPU UHPI read/write
I/O IPU McASP0 serial data
57 EMB_CAS O IPU EMIFB column address strobe
59 EMB_WE O IPU EMIFB write enable
60 EMB_WE_DQM[0] /GP5[15] O IPU EMIFB write enable/data mask for EMB_D.
70
RX-A830
Pin TYPE PULL

No. (1) (2)
62 EMB_D[7]/GP6[7] I/O IPD EMIFB SDRAM data bus
85 EMB_WE_DQM[1] /GP5[14] O IPU EMIFB write enable/data mask for EMB_D
86 EMB_CLK O IPU EMIF SDRAM clock
88 EMB_SDCKE I/O IPU EMIFB SDRAM clock enable
89 EMB_A[12]/GP3[13] O IPD EMIFB SDRAM row/column address bus
98 EMB_A[4]/GP7[6] O IPD EMIFB SDRAM row/column address
106 EMB_BA[1]/GP7[0] O IPU EMIFB SDRAM bank address
107 EMB_BA[0]/GP7[1] O IPU EMIFB SDRAM bank address
108 EMB_CS[0] O IPU EMIFB SDRAM chip select 0
110 EMB_RAS O IPU EMIFB SDRAM row address strobe
RX-A830
111 AXR0[0]/AFSR2/GP3[0] I/O IPD McASP0 serial data

O IPD McASP2 serial data
112 AXR0[1]/ACLKX2/GP3[1] I/O IPD McASP0 serial data
O IPD McASP2 transmit bit clock
113 AXR0[2]/AXR2[3]/GP3[2] I/O IPD McASP0 serial data
115 AXR0[3]/AXR2[2]/GP3[3] I/O IPD McASP0 serial data
71
RX-A830
Pin TYPE PULL

No. (1) (2)
116 AXR0[4]/ AXR2[1]/GP3[4] I/O IPD McASP0 serial data
117 AXR0[5]/AFSX2/GP3[5] I/O IPD McASP0 serial data
O IPD McASP2 transmit frame sync
118 AXR0[6]/ACLKR2/GP3[6] I/O IPD McASP0 serial data
I/O IPD McASP2 receive bit clock
122 UART1_RXD/AXR0[9]/GP3[9] I IPD UART1 receive data
(3) I/O IPD McASP0 serial data
123 UART1_TXD/AXR0[10]/GP3[10] O IPD UART1 transmit data
(3) I/O IPD McASP0 serial data
124 AXR0[11]/ AXR2[0]/GP3[11] I/O IPD McASP0 serial data
125 AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] I/O IPD McASP0 transmit master clock
O IPD McASP2 transmit master clock
I IPD USB_REFCLKIN. Optional 48 MHz clock input
126 ACLKX0/ECAP0/APWM0/GP2[12] I/O IPD Enhanced capture 0/input or auxiliary PWM 0 output
I/O IPD McASP0 transmit bit clock
127 AFSX0/GP2[13]/BOOT[10] I IPD BOOT[10]
I/O IPD McASP0 transmit frame sync
129 AHCLKR0/GP2[14]/BOOT[11] I IPD BOOT[11]
I/O IPD McASP0 receive master clock
130 ACLKR0/ECAP1/APWM1/GP2[15] I/O IPD Enhanced capture 1/input or auxiliary PWM 1 output
131 AFSR0/GP3[12] I/O IPD McASP0 receive frame sync
132 AMUTE1/EPWMTZ/GP4[14] I/O IPD eHRPWM0 trip zone input
I/O IPD eHRPWM1 trip zone input
I/O IPD eHRPWM2 trip zone input
O IPD McASP1 mute output
133 RSV2 PWR Reserved. For proper device operation, this pin must be tied directly to CVDD
134 USB0_VDDA12 (4) PWR USB0 PHY 1.2-V LDO output for bypass cap
135 USB0_VDDA18 PWR USB0 PHY 1.8-V supply input
136 NC – –
137 USB0_DP A USB0 PHY data plus
138 USB0_DM A USB0 PHY data minus
139 NC – –
140 USB0_VDDA33 PWR USB0 PHY 3.3-V supply
141 PLL0_VDDA PWR PLL analog VDD (1.2-V filtered supply)
142 PLL0_VSSA GND PLL analog VSS (for filter)
143 OSCIN I Oscillator input
144 OSCVSS GND Oscillator ground (for filter only)
145 OSCOUT O Oscillator output
146 RESET I Device reset input
148 RTC_XI I Low-frequency (32-kHz) oscillator receiver for real-time clock
149 RTC_CVDD PWR RTC module core power ( isolated from rest of chip CVDD)
150 TRST I IPD JTAG test reset
RX-A830
152 TMS I IPU JTAG test mode select
153 TDI I IPU JTAG test data input
155 TCK I IPU JTAG test clock
156 TDO O IPD JTAG test data output
157 GP7[14] (5) I/O IPD General-Purpose IO signal
72
RX-A830
Pin TYPE PULL

No. (1) (2)
160 AHCLKX1/EPWM0B/GP3[14] I/O IPD eHRPWM0 B output
I/O IPD McASP1 transmit master clock
162 ACLKX1/EPWM0A/GP3[15] I/O IPD eHRPWM0 A output
I/O IPD McASP1transmit bit clock
163 AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] I/O IPD Sync input to eHRPWM0 module or sync output to external PWM
I/O IPD McASP1 transmit frame sync
165 ACLKR1/ECAP2/APWM2/GP4[12] I/O IPD enhanced capture 2/input or auxiliary PWM 2 output
166 AFSR1/GP4[13] I/O IPD McASP1 receive frame sync
168 AXR1[8]/EPWM1A/GP4[8] I/O IPD eHRPWM1 A (with high-resolution)
I/O IPD McASP1 serial data
169 AXR1[7]/EPWM1B/GP4[7] I/O IPD eHRPWM1 B
170 AXR1[6]/EPWM2A/GP4[6] I/O IPD eHRPWM2 A (with high-resolution)
171 AXR1[5]/EPWM2B/GP4[5] I/O IPD eHRPWM2 B
173 AXR1[4]/EQEP1B/GP4[4] I IPD eQEP1B quadrature input
174 AXR1[3]/EQEP1A/GP4[3] I IPD eQEP1A quadrature input
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted
in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports
high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus
output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) 122, 123 pin: As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if UART1
boot mode is used.
(4) 134 pin: Core power supply LDO output for USB PHY. This pin must be connected via a 0.22-mF capacitor to VSS. When the USB peripheral is not
used, the USB_VDDA12 signal should still be connected via a 1-mF capacitor to VSS.
(5) 157 pin: GP7[14] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
RX-A830
73
RX-A830
IC951: DM860A (DIGITAL (1) P.C.B.)

Network microprocessor
* No replacement part available.
General Purpose
Security Engine Timing Engine
RESET, BOOT_SEL on-chip RAM CLOCKS
Reset, Boot, OTP 2 PLLs, 3 DCOs
64 kBytes
master DMA
AV0 Port slave
4xAudio, 1xVideo 2 Forwarding Units
I2S, I8S, DSD, video 64 Contexts
AV2 Port S ARM 926EJ-S

4xAudio
I2S, I8S, DSD 240 MHz
Y
I-cache 16 kByte
slave master
AV3 Port S D-cache 16 kByte
2xAudio I2S, I8S, DSD,
SPDIF
T
slave Interrupt Controller GPIO
AV4 Port Watchdog, 2 Timer
2xAudio I2S, I8S, DSD, E
SPDIF, ADAT
M RTSP Processor
160 MHz
stereo master
Audio PWM-DAC slave I-cache 16 kByte
TCM 48 kByte
Memory Bus, SD/SRAM and System slave

System Extension Extension Controller Audio Engine
B 160 MHz
master
slave slave I-cache 4 kByte
LCD LCD Controller U
TCM 10 kByte
USB 2.0 slave master Ethernet MAC

USB USB (R/SSS)MII
OTG
10/100 Mbps
PHY 8 kByte RAM
slave slave
UART 2 x UART-1 NAND FLASH NAND
slave slave
SPI SPI SSM Controller SSM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
VDD33 VSS33
A USBDN n.c. n.c. VDD33 RFCLKP RFRXQP RFRXIP HIGHZ SSMD0 SSMD4 SSMCMD RXD1 TDO TDI A0 A1 A
USBC USBC
VDD33 VSS33
B USBDP n.c. n.c. VSS RFCLKN RFRXQN RFRXIN TEST1 SSMD1 SSMD5 TXD1 RXD0 TMS SPICLK SPINCS1 A2 B
USBT USBT
VSS12 NRES12
C USBREXT USBXO USBXI VSS RREF n.c. n.c. SSMCLK SSMD2 SSMD6 TXD0 TCK SPINCS0 A3 A4 A5 C
USB OUT
VDD12 NRES33 NRES33 NRES12

D USBVBUS USBATST VDD33 VDD12 SSMWP SSMCP SSMD3 SSMD7 NRESET SPIDI SPIDO A6 A7 A8 D
USB OUT REF REF
VSS33 USBVB VDD12 VDD12 VDD12 VDD12

E USBID NC VDD33IO VDD33IO VDD33IO VDD33IO A9 A10 A11 A12 E
RTC USDRV CORE CORE CORE CORE
VDD33 VDD33 VDD12

F RTCXIN NC VDD33IO VSS VSS VSS VSS VSS VSS VSS VSS A13_RAS A14_CAS A15_BA0 A16_BA1 F
RTC PLL CORE
VDD12 VSS33 VDD12 A17_DQ A18_DQ

G RTCXOUT NC VDD33IO VSS VSS VSS VSS VSS VSS VSS VSS A19 A20 G
DCO PLL CORE M0 M1
VSS12 VSS12 VDD12 VDD12

H NC VSS VSS VSS VSS VSS VSS VSS VSS VDD33IO A21 A22 A23 NCS3 H
DCO PLL PLL CORE
VDD12
J PDOUT1 VCO1 XTALO NC VSS VSS VSS VSS VSS VSS VSS VSS VDD33IO NCS0 NCS1 NCS2 MEMCKE J
CORE
VDD12
K PDOUT0 VCO0 XTALI AOUTLP VDD33IO VSS VSS VSS VSS VSS VSS VSS VSS MEMCLK NWE NOE NWAIT K
CORE
VDD12
L AV0CLK AOUTLN AOUTRN AOUTRP VDD33IO VSS VSS VSS VSS VSS VSS VSS VSS D3 D2 D1 D0 L
CORE
AV0 AV0 AV0 AV0 VDD12

M VSS VSS VSS VSS VSS VSS VSS VSS VDD33IO D7 D6 D5 D4 M
CTRL0 CTRL1 CTRL2 DATA3 CORE
AV0 AV0 AV0 AV1 VDD12

RX-A830
N VSS VSS VSS VSS VSS VSS VSS VSS VDD33IO D11 D10 D9 D8 N
DATA2 DATA1 DATA0 DATA3 CORE
AV1 AV1 AV1 AV2 VDD12 VDD12 VDD12 VDD12

P VDD33IO VDD33IO VDD33IO VDD33IO FD0 FD1 D13 D12 P
DATA2 DATA1 DATA0 DATA3 CORE CORE CORE CORE
AV2 AV2 AV3 LCD

R AV2CLK AV3CLK LCDD11 LCDD7 LCDD3 VPP MIITXEN MIITXCLK MIIRXER MIICRS FD2 FD3 FD4 D14 R
CTRL1 DATA2 DATA1 CTRL0
AV2 AV2 AV3 AV3 LCD MII

T LCDD14 LCDD10 LCDD6 LCDD2 LCDCLK MIIITXER MIIRXCLK MIICOL FD5 FD6 FD7 D15 T
CTRL0 DATA1 CTRL1 DATA0 CTRL1 RXDV
AV2 AV3 AV4 LCD

U LCDD16 LCDD13 LCDD9 LCDD5 LCDD1 MIITXD0 MIITXD2 MIIRXD0 MIIRXD2 MIIMDIO NFCE0 FCLE NFWE NFRB U
DATA0 CTRL0 DATA1 CTRL2
AV4 LCD MIIPHY

V NC LCDD17 LCDD15 LCDD12 LCDD8 LCDD4 LCDD0 MIITXD1 MIITXD3 MIIRXD1 MIIRXD3 MIIMDC NFWP NFRE FALE V
DATA0 CTRL3 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
74
RX-A830
AV-Port 0
Pin No. Function Name I/O Detail of Function
M4
N1 Audio/video data.
AV0DATA[3:0] I/O
N2 Several formats are supported.
N3
N4 Video data, together with AV0DATA[3:0]:
P1 AV0DATA[3:0] = video[3:0]
AV1DATA[3:0] I/O
P2 AV1DATA[3:0] = video[7:4]
P3
Data clock. Depending on the AV-Port 0 configuration, this clock is a bit- or byte-clock which is used to
L1 AV0CLK I/O
transmit or receive the AV0DATA[*] synchronously.
Configurable sync signal:
M1 AV0CTRL0 I/O • Serial audio formats: LRCK input or output.
• Video formats: PSYNC input or output.
M2 AV0CTRL1 I/O • Serial audio formats: Master clock output.
• Video formats: DVALID input or output.
M3 AV0CTRL2 I/O
• Video formats: FSYNC input or output.
AV-Port 2
P4
R3 Audio data.
AV2DATA[3:0] I/O
T2 Several formats are supported.
U1
Data clock. Depending on the AV-Port 2 configuration this clock is a bit-clock which is used to transmit or
R1 AV2CLK I/O
receive the AV2DATA[*] synchronously.
T1 AV2CTRL0 I/O
Serial audio formats: LRCK input or output.
R2 AV2CTRL1 I/O
Serial audio formats: Master clock output.
AV-Port 3
R5 Audio data.
AV3DATA[1:0] I/O
T4 Several formats are supported.
Data clock. Depending on the AV-Port 3 configuration this clock is a bit-clock which is used to transmit or
R4 AV3CLK I/O
receive the AV3DATA[*] synchronously.
U2 AV3CTRL0 I/O
Serial audio formats: LRCK input or output.
T3 AV3CTRL1 I/O
Serial audio formats: Master clock output.
AV-Port 4
U3 Audio data.
AV4DATA[1:0] I/O
V2 Several formats are supported.
PWM-DAC
K4 AOUTLP O Left channel PWM output (positive).
L2 AOUTLN O Left channel PWM output (negative).
RX-A830
L4 AOUTRP O Right channel PWM output (positive).

L3 AOUTRN O Right channel PWM output (negative).
UART Interface
B14 RXD0 I UART-0 receive signal.
C13 TXD0 O UART-0 transmit signal.
A14 RXD1 I UART-1 receive signal.
B13 TXD1 O UART-1 transmit signal.
75
RX-A830
Serial Peripheral Interface (SPI)

D14 SPIDIN I SPI data receive.
D15 SPIDOUT O SPI data transmit.
B16 SPICLK I/O SPI clock.
Multi-master mode: Chip-select input (used to detect bus conflict).
C15 SPINCS0 I/O Master only mode: Chip-select 1 output.
Slave mode: Chip-select input.
Multi-master mode: Chip-select 2 output.
B17 SPINCS1 I/O Master only mode: Chip-select 2 output.
Slave mode: Not used.
External Memory Interface

T18
R18
P17
P18
N15
N16
N17
N18
D[15:0] I/O Data bus for external memory and peripheral access.
M15
M16
M17
M18
L15
L16
L17
L18
E18
E17
E16
E15
D18
D17
D16 A[12:0] O Address bus for external memory and peripheral access.
C18
C17
C16
B18
A18
A17
SRAM: Address output
F15 A13_RAS O
SDRAM: Row access strobe
F16 A14_CAS O
SDRAM: Column access strobe
F17 A15_BA0 O
SDRAM: Bank select
F18 A16_BA1 O
SDRAM: Bank select
RX-A830

G15 A17_DQM0 O
SDRAM: Data mask
G16 A18_DQM1 O
SDRAM: Data mask
H17
H16
H15 A[23:19] O Address bus for external memory and peripheral access.
G18
G17
76
RX-A830

H18 Chip select signals. The active memory range for NCS[n] (active low) can be configured.
J17 • NCS[0] supports SRAM, can be used for booting.
J16 NCS[3:0] O • NCS[1] supports SDRAM or SRAM.
J15 • NCS[2] supports SRAM.
• NCS[3] supports SRAM.
K17 NOE O Output enable, asserted (low) for read operations.
K16 NWE O Write enable, asserted (low) for write operations.
K18 NWAIT I External wait line. If NWAIT is asserted, memory access will be stalled. Can be configured as either low-
active (default) or high-active.
K15 MEMCLK O SDRAM system clock.
J18 MEMCKE O SDRAM clock enable.
NAND-Flash Interface
T17
T16
T15
R17
FD[7:0] I/O Bi-directional data bus.
R16
R15
P16
P15
V18 FALE O Address latch enable; pull-up/down defines boot mode.
U16 FCLE O Command latch enable; pull-up/down defines boot mode.
U15 NFCE0 O Chip-enable, low-active.
U18 NFRB I Ready/busy. NAND flash is busy when NFRB is low.
V17 NFRE O Read enable, low-active.
U17 NFWE O Write enable, low-active.
V16 NFWP O Write protect, low-active.
Ethernet MAC-Phy Interface (MII)

Pin No. Function Name I/O MII RMII SMII
U14 MIIDIO I/O Management data Management data
V14 MIIMDC O Management clock Management clock
V13 MIIRXD[3] I RxD 3 RxD 1
U13 MIIRXD[2] I RxD 2 RxD 0
V12 MIIRXD[1] I RxD 1 Rx-Sync
U12 MIIRXD[0] I RxD 0 RxD
T12 MIIRXCLK I Receive clock Receive clock
R13 MIIRXER I Receive error Receive error
T14 MIIRXDV I Receive data valid Carrier sense/data valid
V11 MIITXD[3] O TxD 3 TxD 1
U11 MIITXD[2] O TxD 2 TxD 0
V10 MIITXD[1] O TxD 1 Tx-Sync
U10 MIITXD[0] O TxD 0 TxD
R12 MIITXCLK I Transmit clock Transmit clock
T11 MIITXER O Transmit error
RX-A830
R11 MIITXEN O Transmit data enable Transmit data enable

T13 MIICOL I MII ethernet collision
R14 MIICRS I MII carrier sense
V15 MIIPHYCLK O 25.000 MHz clock 50.000 MHz clock 125.000 MHz clock
77
RX-A830
USB 2.0 OTG

B1 USBD+ I/O Positive data line that is connected to the serial USB cable.
A1 USBD– I/O Negative data line that is connected to the serial USB cable.
E2 USBID I USB ID pin of mini-AB receptacle.
C2 USBREXT I External bias resistor (2K7, 1%); connect resistor to VSSUSB.
D2 USBVBUS I VBUS voltage sense.
E3 USBVBUSDRV O Control signal to control VBUS 5V voltage source.
C4 USBXTALI I Oscillator circuit input for a 24.000 MHz crystal (optional).
Without external crystal, pull this pin to GND.
C3 USBXTALO O Oscillator circuit output for a 24.000 MHz crystal (optional).
Without external crystal, leave this pin open.
D3 USBATST – Do not connect.
Power-on Reset Pins

D6 NRES12REF I Voltage reference input. NRES12OUT is release when this input voltage exceeds VTH12.
C5 NRES12OUT O Open-drain reset (active low) for 1.2V core power supply.
D5 NRES33REF I Voltage reference input. NRES33OUT is release when this input voltage exceeds VTH33.
D4 NRES33OUT O Open-drain reset (active low) for 3.3V core power supply
Real-Time Clock (RTC) Pins (RTC is Not Supported)

F2 RTCXIN I No connection. Leave this pin open circuit.
G2 RTCXOUT O No connection. Leave this pin open circuit.
F1 VDD33RTC Power No connection. Leave this pin open circuit.
E1 VSS33RTC Power Ground (0 V) for RTC
LCD Interface
LCD STN monochr. LCD STN color

Pin No. Function Name I/O TFT Mode LCD STN monochr. LCD STN color
(double) (bias)
V3 LCDD[17] O RED5
U4 LCDD[16] O RED4
V4 LCDD[15] O RED3
T5 LCDD[14] O RED2
U5 LCDD[13] O RED1
V5 LCDD[12] O (RED0)
R6 LCDD[11] O GREEN5
T6 LCDD[10] O GREEN4
U6 LCDD[9] O GREEN3
V6 LCDD[8] O GREEN2
R7 LCDD[7] O GREEN1 DATAHIGH3 DATA7 DATA7
T7 LCDD[6] O GREEN0 DATAHIGH2 DATA6 DATA6
U7 LCDD[5] O BLUE5 DATAHIGH1 DATA5 DATA5
V7 LCDD[4] O BLUE4 DATAHIGH0 DATA4 DATA4
R8 LCDD[3] O BLUE3 DATA3 DATALOW3 DATA3 DATA3
T8 LCDD[2] O BLUE2 DATA2 DATALOW2 DATA2 DATA2
RX-A830
U8 LCDD[1] O BLUE1 DATA1 DATALOW1 DATA1 DATA1

V8 LCDD[0] O (BLUE0) DATA0 DATALOW0 DATA0 DATA0
T10 LCDCLK O Byte clock CL2 CL2 CL2 CL2
V9 LCDCTRL[3] O Display off Display off Display off Display off Display off
U9 LCDCTRL[2] O Vsync FLM FLM FLM FLM
T9 LCDCTRL[1] O HSync CL1 CL1 CL1 CL1
R9 LCDCTRL[0] O DVALID M/Bias
78
RX-A830
SSM Interface
D12
C12
B12
A12
SSMD[7:0] I/O Data lines.
D11
C11
B11
A11
C10 SSMCLK O Clock output.
A13 SSMCMD O Command output.
D10 SSMCP I Card power input (high = off).
D9 SSMWP I Write protect input (low = protect).
External PLL Pins

J2 External oscillator inputs, typically coming from an external VCO. Together with the external loop-filter and
VCO[1:0] I
K2 the internal clock dividers, each PDOUT/VCO pair can form a complete PLL.
J1 Phase discriminator outputs. These signals are charge-pump type outputs.
PDOUT[1:0] O
K1 Each of them can be used to feed the loop-filter of a PLL structure.
Global Pins
Reset (active low). When asserted, the chip is placed in the reset state and the peripheral pins are
configured as inputs. After deassertion of NRESET, the chip is clocked by XTALI and starts booting from the
D13 NRESET I port configured by the FCLE, FALE pins.
The NRESET signal must be asserted after power-up.
K3 XTALI I Oscillator circuit input. Internal system clock will be derived from XTALI (internal clock multiplier).
J3 XTALO O Oscillator circuit output.
C7 RREF I Reference current. Connect a 3.0 k-ohms ±1% resistor to GND.
B10 TEST1 I Reserved. Connect to VDD for normal operation.
A10 HIGHZ I Reserved. Connect to VDD for normal operation.
E4
F4
G4
H4
J4
V1
n.c. – Pins must be left unconnected (18x).
A4
A5
B4
B5
C8
C9
JTAG Interface
B15 TMS I JTAG mode select.
C14 TCK I JTAG clock.
A16 TDI I JTAG serial data input.
RX-A830
A15 TDO O JTAG serial data output.
79
RX-A830
Power Supply Pins

Pin No. Function Name Detail of Function Pin No. Function Name Detail of Function
A6 K13
E8 L6
E9 L7
E12 L8
E13 L9
F5 L10
G5 L11
H14 L12
J14 L13
VDD33 I/O power supply (+3.3 V).
K5 M6
L5 M7
M14 M8
N14 M9
P6 M10 VSS Ground (0 V).
P7 M11
P10 M12
P11 M13
D7 N6
F6 N7
F7 N8
F8 N9
F9 N10
F10 N11
F11 N12
F12 N13
F13 B6
G6 C6
G7 R10 VPP
G8 A2
VDD33USB
G9 B2 Power supply (+3.3 V) for USB interface.
G10 A3 Ground (0 V).
VSS33USB
G11 B3
G12 F3 VDD33PLL Power supply (+3.3V) for PLL.
G13 G3 VSS33PLL Ground (0 V).
H6 E6
H7 E7
H8 E10
H9 VSS Ground (0 V). E11
H10 F14
H11 G14
H12 H5
H13 J5
J6 K14 VDD12 Power supply (+1.2V).
J7 L14
J8 M5
J9 N5
J10 P8
J11 P9
J12 P12
J13 P13
RX-A830
K6 D8
K7 D1 VDD12USB Power supply (+1.2V) for USB interface.
K8 C1 VSS12USB Ground (0 V).
K9 H3 VDD12PLL Power supply (+1.2V) for PLL.
K10 H2 VSS12PLL Ground (0 V).
K11 G1 VDD12DCO Power supply (+1.2V) for DCO.
K12 H1 VSS12DCO Ground (0 V).
80
RX-A830
IC83: R5F6416MADFE (DIGITAL (1) P.C.B.)

Microprocessor
* No replacement part available.
8 8 8 8 8 8 8 8
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7
Port P8
Peripheral functions
7
Timer: A/D converter: Clock generator:
Timer A16 bits × 5 timers 10 bits × 1 circuit 4 circuits
Timer B16 bits × 6 timers Standard: 10 inputs - XIN-XOUT
Maximum: 34 inputs - XCIN-XCOUT
P8_5
Three-phase motor - On-chip oscillator
controller - PLL frequency synthesizer
D/A converter:
Serial interface: 8 bits × 2 channels
Watchdog timer:
11 channels
Port P9
X-Y converter: 15 bits
16 bits × 16 bits
8
Multi-master I2C-bus DMAC
interface: CRC calculator (CCITT)
1 channel X16 + X12 + X5 + 1 DMAC II
Port P10
Intelligent I/O R32C/100 Series Microprocessor Core Memory
8
Time Measurement: 16
R2R0 ROM
Wave generation: 24 R2R0
R3R1 FLG
Serial interface: R3R1 INTB
Port P11
R6R4
- Variable-length R6R4
R7R5 ISP RAM
R7R5
A0 USP
synchronous serial I/O A0 PC
8
- IEBus A1
A1
A2 SVF
A2 SVP Multiplier
A3
A3
FB VCT
Port P12
FB
SB
SB Floating-point unit
8
Port P19 Port P18 Port P17 Port P16 Port P15 Port P14 P14_1 Port P13
8 8 8 8 8 5 8
96 RXD10
95 TXD10
97 CLK10
112 P12_2
111 P12_3
110 P12_4
106 P16_0
98 P16_4
92 P11_5
90 P11_6
104 RXD9
114 TXD6
103 TXD9
113 CLK6
105 CLK9
131 D[10]
130 D[11]
129 D[12]
128 D[13]
127 D[14]
126 D[15]
108 A[10]
107 A[11]
102 A[12]
101 A[13]
100 A[14]
99 A[15]
94 A[16]
93 A[17]
91 A[18]
89 A[19]
115 VCC
117 VSS
132 D[9]
125 A[0]
124 A[1]
123 A[2]
122 A[3]
121 A[4]
120 A[5]
119 A[6]
118 A[7]
116 A[8]
109 A[9]
D[8] 133 88 A[20]

D[7] 134 87 A[21]
D[6] 135 86 A[22]
D[5] 136 85 CS0
D[4] 137 84 P19_2
P19_1 138 83 P17_0
P11_4 139 82 P17_1
P19_0 140 81 P17_2
P11_3 141 80 P17_3
P11_2 142 79 P19_3
P11_1 143 78 P12_5
P11_0 144 77 P12_6
P18_7 145 76 P12_7
P18_6 146 75 WR/P5_0
P18_5 147 74 NC(BC1)
P18_4 148 73 RD
P18_3 149 72 NC(BCLK)
P18_2 150 71 P13_0
D[3] 151 70 P13_1
D[2] 152 69 VCC
D[1] 153 68 P13_2
D[0] 154 67 VSS
P15_7 155 IC83 66 P13_3
P15_6 156 65 CS1
P15_5 157
R5F6416MADFE 64 P5_5
P15_4 158 63 CS2
P15_3 159 62 CS3
P15_2 160 61 P19_4
IIO0_1 161 60 ISTXD2
VSS 162 59 ISRXD2
P15_0 163 58 ISCLK2
VCC 164 57 P13_7
P10_7 165 56 P19_5
AN_6 166 55 P6_0
AN_5 167 54 CLK0
RX-A830
P10_4 168 53 RXD0

P10_3 169 52 TXD0
AN_2 170 51 P6_4
AN_1 171 50 CLK1
AVSS 172 49 P11_7
P10_0 173 48 RXD1
VREF 174 47 P14_7
AVCC 175 46 TXD1
SCL4/RXD4 176 45 SDA2
P19_6 10
INT7 11
INT6 12
P14_3 13
VDC0 14
P14_1 15
VDC1 16
NSD 17
CNVSS 18
P8_7 19
P8_6 20
RESET 21
XOUT 22
VSS 23
XIN 24
VCC 25
NMI 26
INT2 27
INT1 28
INT0 29
TA4IN 30
SCL5 31
P18_1 32
P18_0 33
TA3IN 34
SDA5 35
TA2IN 36
P7_4 37
P17_7 38
P17_6 39
P17_5 40
P17_4 41
TA2IN 42
P7_2 43
SCL2 44
SDA4/TXD4 1
P9_5 2
P9_4 3
DA0 4
SDA3 5
SCL3 6
P9_0 7
P19_7 8
INT8 9
81
RX-A830
I/O
Pin
Port Name Function Name Related Power Supply Detail of Function
No.
OFF ON
TUN_SDA PRY O I/O Tuner I2C data
1 SRXD4/SDA4/TXD4/ANEX1/P9_6
HDR_MOSI PRY O O HD radio transmission data
2 CLK4/ANEX0/P9_5 VOL1_SCK PRY/DSP_PON O O VOL1 (R2A15220FP #1) communication clock
N_CTS4/N_N_RTS4/N_SS4/TB4IN/
3 VOL_MOSI PRY/DSP_PON O O VOL1 communication data
DA1/P9_4
N_CTS3/N_N_RTS3/N_SS3/TB3IN/
4 AMP_LMT PRY I O Limiter control
DA0/P9_3
IEOUT/ISTXD2/OUTC2_0/SRXD3/
5 HDMI_SDA HDMI_PON O I/O HDMI 400k I2C data
SDA3/TXD3/TB2IN/P9_2
IEIN/ISRXD2/STXD3/SCL3/RXD3/
6 HDMI_SCL HDMI_PON O O HDMI 400k I2C clock
TB1IN/P9_1
7 CLK3/TB0IN/P9_0 SPRY_5CH PRY O O SP relay 5CH (L, C, R, SRL, SRR)
8 P19_7 PA_B_RY PRY O O Power amplifier B power supply control
9 N_INT8/P14_6 HAU_INT HDMI_PON O I Mute signal from HDMI, RX1 and RX2
10 P19_6 HRX1_MT HDMI_PON O I Mute signal from HDMI RX1 (for HAU_N_INT distinction)
11 N_INT7/P14_5 HTX1_N_INT HDMI_PON O I HDMI TX CEC interrupt
12 N_INT6/P14_4 PWR_DET AC I I AC power detect
13 P14_3 FLD_N_CS FLD_PON O O FLD chip select
14 VDC0 VDC0 ---
15 P14_1 (for exclusive use of the input) I_PRT PRY I I Current protection
16 VDC1 VDC1 ---
17 NSD NSD Debugger
18 CNVSS DBG_CNVSS ---
19 XCIN/P8_7 MIC_N_DET DSP_PON O I Microphone detection
20 XCOUT/P8_6 PD_LED PRY O O Pure direct LED
21 RESET MCPU_N_RST ---
22 XOUT XOUT ---
23 VSS VSS ---
24 XIN XIN ---
25 VCC VCC ---
26 NMI/P8_5 NMI ---
27 N_INT2/P8_4 WAKEUP_INT AC O I Power switch, MISO interrupt of RS-232C (sleep return)
28 N_INT1/P8_3 REM_IN2 AC O I Remote control pulse input 2
29 N_INT0/P8_2 REM_IN1 AC O I Remote control pulse input 1
UD0B/UD1B/IIO1_5/N_RTS5/N_CTS5/ TUN_N_INT PRY O I Interrupt from tuner
30
N_SS5/U/TA4IN/P8_1 --- AC O O No used
UD0A/UD1A/RXD5/SCL5/STXD5/U/
31 --- AC O O No used
TA4OUT/P8_0
32 P18_1 HSW2_N_INT HDMI_PON O I Sii9589 (2) interrupt
33 P18_0 HSW1_N_INT HDMI_PON O I Sii9589 (1) interrupt
34 UD0B/UD1B/IIO1_4/CLK5/TA3IN/P7_7 FHDMI_N_INT HDMI_PON O I Front HDMI interrupt
UD0A/UD1A/IIO1_3/N_RTS8/N_CTS8/
TXD5/SDA5/SRXD5/TA3OUT/P7_6
36 IIO1_2/RXD8/W/TA2IN/P7_5 DAU_N_INT DSP_PON O I Interrupt from DIR1, DIR2 and DSP
37 IIO1_1/CLK8/W/TA2OUT/P7_4 --- AC O O No used
38 P17_7 --- AC O O No used
40 P17_5 VOL_RA AC I I Volume A
41 P17_4 VOL_RB AC I I Volume B
RX-A830
IIO1_0/TXD8/N_SS2/N_RTS2/N_CTS2/
42 HRX_N_INT HDMI_PON O I HDMI RX (ADV7619) interrupt
V/TA1IN/P7_3
43 CLK2/V/TA1OUT/P7_2 NCPU_SPI_REQ NCPU_PON O I BridgeCO request
MSCL/IEIN/ISRXD2/OUTC2_2/IIO1_7/
44 DV_SCL HDMI_PON O O D-VIDEO/A-VIDEO/F-HDMI 400k I2C clock
STXD2/SCL2/RXD2/TA0IN/TB5IN/P7_1
TA0OUT/TXD2/SDA2/SRXD2/IIO1_6/
45 DV_SDA HDMI_PON O I/O D-VIDEO/A-VIDEO/F-HDMI 400k I2C data
OUTC2_0/ISTXD2/IEOUT/MSDA/P7_0
46 TXD1/SDA1/SRXD1/P6_7 232C_DBG_MOSI AC O O RS-232C transmission data / Debug / E8a
47 P14_7 DSP_PON DSP_PON O O DSP power supply
82
RX-A830
I/O
Pin
No.
OFF ON
48 RXD1/SCL1/STXD1/P6_6 232C_DBG_MISO AC O I RS-232C reception data / Debug / E8a
50 CLK1/P6_5 DBG_SCK AC O I E8a
N_CTS1/N_RTS1/N_SS1/OUTC2_1/
51 DBG_BUSY AC O O E8a
ISCLK2/P6_4
52 TXD0/SDA0/SRXD0/P6_3 DSP_MOSI DSP_PON O O DSP/DIR/DAC transmission data
53 TB2IN/RXD0/SCL0/STXD0/P6_2 DSP_MISO DSP_PON I I DSP/DIR/DAC reception data
54 TB1IN/CLK0/P6_1 DSP_SCK DSP_PON O O DSP/DIR/DAC communication clock
55 TB0IN/N_CTS0/N_RTS0/N_SS0/P6_0 NCPU_SPI_RDY NCPU_PON O I BridgeCO data ready
57 D31/OUTC2_7/P13_7 DSP1_N_RST DSP_PON O O DSP1 reset
58 D30/OUTC2_1/ISCLK2/P13_6 --- Serial spare
59 D29/OUTC2_2/ISRXD2/IEIN/P13_5 --- Serial spare
60 D28/OUTC2_0/ISTXD2/IEOUT/P13_4 --- Serial spare
61 P19_4 EEP_N_CS AC O O EEPROM chip select
62 RDY/CS3/N_CTS7/N_RTS7/P5_7 FPGA_N_CS HDMI_PON O B External bus FPGA chip select
63 ALE/CS2/RXD7/P5_6 DFF2_N_CS AC O B External bus DFF2 chip select
64 HOLD/CLK7/P5_5 DBG_EPM AC I I E8a
65 HLDA/CS1/TXD7/P5_4 DFF1_N_CS AC O B External bus DFF1 chip select
66 D27/OUTC2_3/P13_3 --- AC O O No used
67 VSS VSS ---
68 D26/OUTC2_6/P13_2 DSP1_N_SPIRDY DSP_PON O I DSP1 SPI ready
69 VCC VCC ---
70 D25/OUTC2_5/P13_1 --- AC O O No used
71 D24/OUTC2_4/P13_0 DSP1_N_CS DSP_PON O O DSP1 chip select
72 CLKOUT/BCLK/P5_3 NC(BCLK) AC O B External bus
73 RD/P5_2 MCBUS_N_RD AC O B External bus
74 WR1/BC1/P5_1 NC(BC1) AC O B External bus
MCBUS_N_WR HDMI_PON I B External bus
75 WR0/WR/P5_0
DBG_N_CE AC I I E8a
76 D23/P12_7 MT_DA DSP_PON O O Mute digital audio
77 D22/P12_6 DIR1_N_CS DSP_PON O O DIR1 chip select
78 D21/P12_5 DIR_N_RST DSP_PON O O DIR reset
80 P17_3 DIR1_N_INT DSP_PON O I Interrupt from DIR1 (for DAU_N_INT distinction)
82 P17_1 NCPU_PON NCPU_PON O O NET / USB power supply
83 P17_0 NCPU_VBUSDRV NCPU_PON O I USB VBUS drive
84 P19_2 USB_VBUS_PON NCPU_PON O O USB VBUS power supply control
85 CS0/A23/TXD6/SDA6/SRXD6/P4_7 FLASH_N_CS AC O O External bus flash ROM chip select
86 CS1/A22/RXD6/SCL6/STXD6/P4_6 A[22] AC O B External bus
87 CS2/A21/CLK6/P4_5 A[21] AC O B External bus
CS3/A20/N_CTS6/N_RTS6/N_SS6/
88 A[20] AC O B External bus
P4_4
A19/TXD3/SDA3/SRXD3/OUTC2_0/
ISTXD2/IEOUT/P4_3
90 P11_6 HTX2_AUSEL DSP_PON O O HDMI TX2 sound select (main/zone ADC)
A18/RXD3/SCL3/STXD3/ISRXD2/IEIN/
P4_2
RX-A830
92 P11_5 DFF_FROM_N_RST AC O O Reset of DFF and external ROM

93 A17/CLK3/P4_1 A[17] AC O B External bus
94 A16/N_CTS3/N_RTS3/N_SS3/P4_0 A[16] AC O B External bus
95 P16_7/TXD10 EX_MOSI AC O O FL/EEPROM transmission data
96 P16_6/RXD10 EEP_MISO AC O I EEPROM reception data
97 P16_5/CLK10 EX_SCK AC O O FL/EEPROM communication clock
98 P16_4/N_CTS10/N_RTS10 NCPU_AMUTE NCPU_PON O I Mute signal from BridgeCO
99 A15/[A15/D15]/TA4IN/U/P3_7 A[15] AC O B External bus
100 A14/[A14/D14]/TA4OUT/U/P3_6 A[14] AC O B External bus
83
RX-A830
I/O
Pin
No.
OFF ON
101 A13/[A13/D13]/TA2IN/W/P3_5 A[13] AC O B External bus
102 A12/[A12/D12]/TA2OUT/W/P3_4 A[12] AC O B External bus
103 P16_3/TXD9 NCPU_SPI_MOSI NCPU_PON O O Data (master out slave in)
104 P16_2/RXD9 NCPU_SPI_MISO NCPU_PON O I Data (master in slave out)
105 P16_1/CLK9 NCPU_SPI_SCK NCPU_PON O O Clock (master out slave in)
106 P16_0/N_CTS9/N_RTS9 NCPU_N_RST NCPU_PON O O Network microprocessor reset
107 A11/[A11/D11]/TA1IN/V/P3_3 A[11] AC O B External bus
108 A10/[A10/D10]/TA1OUT/V/P3_2 A[10] AC O B External bus
109 A9/[A9/D9]/TA3OUT/UD0B/UD1B/P3_1 A[9] AC O B External bus
110 D20/P12_4 AD_SEL_A +3.3S_PON O O AD select A
111 D19/N_CTS6/N_RTS6/N_SS6/P12_3 AD_SEL_B +3.3S_PON O O AD select B
112 D18/RXD6/SCL6/STXD6/P12_2 AD_SEL_C +3.3S_PON O O AD select C
113 D17/CLK6/P12_1 FPGA_SCK HDMI_PON O O FPGA clock (at Boot)
114 D16/TXD6/SDA6/SRXD6/P12_0 FPGA_MOSI HDMI_PON O O FPGA transmission data (at Boot)
115 VCC VCC ---
116 A8/[A8/D8]/TA0OUT/UD0A/UD1A/P3_0 A[8] AC O B External bus
117 VSS VSS ---
118 A7/[A7/D7]/AN2_7/P2_7/TXD10 A[7] AC O B External bus
119 A6/[A6/D6]/AN2_6/P2_6/RXD10 A[6] AC O B External bus
120 A5/[A5/D5]/AN2_5/P2_5/CLK10 A[5] AC O B External bus
A4/[A4/D4]/AN2_4/P2_4/N_CTS10/N_
RTS10
122 A3/[A3/D3]/AN2_3/P2_3/TXD9 A[3] AC O B External bus
123 A2/[A2/D2]/AN2_2/P2_2/RXD9 A[2] AC O B External bus
A1/[A1/D1]/BC2/[BC2/D1]/AN2_1/P2_1/
CLK9
A0/[A0/D0]/BC0/[BC0/D0]/AN2_0/P2_0/
N_CTS9/N_RTS9
126 D15/N_INT5/IIO0_7/IIO1_7/P1_7 D[15] AC I B External bus
129 D12/IIO0_4/IIO1_4/P1_4 D[12] AC I B External bus
133 IIO0_0/IIO1_0/D8/P1_0 D[8] AC I B External bus
134 AN0_7/D7/P0_7 D[7] AC I B External bus
138 P19_1 FPGA_N_CFG HDMI_PON O O FPGA nCONF
139 WR3/BC3/P11_4 FPGA_N_STA HDMI_PON I I FPGA nSTATUS
140 P19_0 FPGA_CDONE HDMI_PON I I FPGA CONF DONE
IIO1_3/N_RTS8/N_CTS8/WR2/CS3/
141 DIAG_CHECK AC O O Diag inspection result output / OK=High, NG=Low
P11_3
142 IIO1_2/RXD8/CS2/P11_2 NDAC_N_MT DSP_PON O O Net zone DAC mute
143 IIO1_1/CLK8/CS1/P11_1 SPRY_Z2&FP PRY O O SP relay zone 2 and front presence
144 IIO1_0/TXD8/CS0/P11_0 NCPU_SPI_N_CS NCPU_PON O O Network microprocessor SPI chip select
145 P18_7 HPRY PRY O O HP relay
RX-A830
146 P18_6 MT_N_Z2 +3.3S_PON O O Mute zone2 (line out)

147 P18_5 SPRY_SB&BA PRY O O SP relay surround back and Bi-Amp
148 P18_4 MT_N_5CH +3.3S_PON O O Mute 5ch (L, C, R, SRL, SRR preout/main in)
149 P18_3 MT_N_SW +3.3S_PON O O Mute subwoofer (Preout)
150 P18_2 MT_N_SB +3.3S_PON O O Mute SB/BA/Z2/FP (Preout/Main in)
84
RX-A830
I/O
Pin
No.
OFF ON
IIO0_7/N_RTS6/N_CTS6/N_SS6/
155 SVID_DET VID_PON I I S-video detect
AN15_7/P15_7
156 IIO0_6/CLK6/AN15_6/P15_6 HP_N_DET DSP_PON O I Headphone detection
IIO0_5/RXD6/SCL6/STXD6/AN15_5/
P15_5
IIO0_4/TXD6/SDA6/SRXD6/AN15_4/
158 DC_TRG1 PRY O O Control out 1
P15_4
IIO0_3/N_RTS7/N_CTS7/AN15_3/
159 DSP1_N_INT DSP_PON O I Interrupt from DSP1 (for DAU_N_INT distinction)
P15_3
160 IIO0_2/RXD7/AN15_2/P15_2 UART spare AC O O No used, spare for UART
161 IIO0_1/CLK7/AN15_1/P15_1 --- AC O O No used
162 VSS VSS ---
163 IIO0_0/TXD7/AN15_0/P15_0 UART spare AC O O No used, spare for UART
164 VCC VCC ---
165 KI3/AN_7/P10_7 +3.3S_PON +3.3S_PON O O +3.3S power supply
166 KI2/AN_6/P10_6 AD2_COM +3.3S_PON O I AD selector 2 COM input
167 KI1/AN_5/P10_5 AD1_COM +3.3S_PON O I AD selector 1 COM input
168 KI0/AN_4/P10_4 HSW_2CHIP AC I I HDMI SW number distinction
169 AN_3/P10_3 --- AC O O No used
170 AN_2/P10_2 KY_AD2 AC O I Key 2
171 AN_1/P10_1 KY_AD1 AC O I Key 1
172 AVSS AVSS ---
TUN_N_RST PRY O O Tuner reset
173 AN_0/P10_0
HDR_N_RST PRY O O HD radio reset
174 VREF VREF ---
175 AVCC AVCC ---
TUN_SCL PRY O O Tuner I2C clock
176 STXD4/SCL4/RXD4/ADTRG/P9_7
HDR_MISO PRY O I HD radio reception data
Key detection for A/D port

Key input (A/D) pull-up resistance 10 k-ohms
0Ω + 1.0 kΩ + 1.0 kΩ + 1.5 kΩ + 1.5 kΩ + 2.2 kΩ 22 kΩ 33 kΩ
Detected voltage value

0 – 0.15 V 0.15 – 0.42 V 0.43 – 0.70 V 0.71 – 0.97 V 0.98 – 1.24 V 1.25 – 1.53 V 2.23 – 2.62 V 2.63 – 3.04 V
at 171 pin
A/D value
0 – 11 12 – 32 33 – 54 55 – 75 76 – 96 97 – 119 182 – 197 198 – 209
(3.3 V=255)
RADIO NET TV BD/DVD ZONE MAIN ZONE TONE

KEY1 ZONE2
(SCENE4) (SCENE3) (SCENE2) (SCENE1) CONTROL (power) CONTROL
0Ω + 1.0 kΩ + 1.0 kΩ + 1.5 kΩ + 1.8 kΩ + 2.2 kΩ + 3.3 kΩ + 4.7 kΩ + 6.8 kΩ + 10 kΩ + 22 kΩ + 68 kΩ

0 – 0.15 V 0.16 – 0.42 V 0.43 – 0.70 V 0.71 – 0.99 V 1.00 – 1.27 V 1.28 – 1.56 V 1.57 – 1.86 V 1.87 – 2.14 V 2.15 – 2.39 V 2.40 – 2.65 V 2.66 – 2.91 V 2.92 – 3.17 V
at 170 pin
A/D value
0 – 11 12 – 32 33 – 54 55 – 77 78 – 99 100 – 121 122 – 144 145 – 166 167 – 186 187 – 205 206 – 226 227 – 246
(3.3 V=255)
PURE TUNING TUNING PRESET PRESET PROGRAM PROGRAM

KEY2 AM FM MEMORY INFO STRAIGHT
DIRECT >> << > < > <
Destination detection for A/D port

Pull-up resistance 10 k-ohms
R753
0Ω 1.2 kΩ 2.7 kΩ 4.7 kΩ 6.8 kΩ 10 kΩ 15 kΩ 47 kΩ 100 kΩ
on DIGITAL P.C.B.
RX-A830

0 – 0.16 V 0.17 – 0.51 V 0.52 – 0.87 V 0.88 – 1.92 V 1.93 – 1.49 V 1.50 – 1.81 V 1.82 – 2.35 V 2.36 – 2.86 V 2.87 – 3.15 V
at 111 pin
A/D value
0 – 12 13 – 39 40 – 67 68 – 92 93 – 115 116 – 140 141 – 169 199 – 221 222 – 244
(3.3 V=255)
Destination J U C R, S T K A B, G, F L
85
RX-A830
• Microprocessor extended port

IC76, 78: SN74LV4051APWR (DIGITAL (1) P.C.B.)
8-channel analog multiplexers/demultiplexers
Y4 1 16 VCC
Y6 2 15 Y2
COM 3 14 3
Y1 COM
Y7 4 13 Y0
Y5 5 12 13
Y3 Y0
INH 6 11 A
GND 7 10 B 14
11 Y1
GND 8 9 C A
15
Y2
12
10 Y3
B
INPUTS ON
1
INH C B A CHANNEL Y4
L L L L Y0
5
L L L H Y1 9 Y5
C
L L H L Y2
L L H H Y3 2
Y6
L H L L Y4
L H L H Y5 4
6 Y7
L H H L Y6 INH
L H H H Y7
H X X X None
IC76
I/O
Pin
No.
OFF ON
1 Y4 THM2 +3.3S_PON I I Temperature detection 2
2 Y6 (Spare) +3.3S_PON I I ---
4 Y7 (Spare) +3.3S_PON I I ---
5 Y5 DEST +3.3S_PON I I Destination distinction
12 Y3 MODEL +3.3S_PON I I Model distinction
13 Y0 MHL_VBUS_PRT +3.3S_PON I I MHL overcurrent detection (spare)
14 Y1 USB_VBUS_PRT +3.3S_PON I I Front USB overcurrent detection
15 Y2 (Spare) +3.3S_PON I I ---
IC78
I/O
Pin
No.
OFF ON
1 Y4 PS2_PRT +3.3S_PON I I Power supply protection 2
2 Y6 PS1_PRT +3.3S_PON I I Power supply protection 1
RX-A830
4 Y7 AMP_OLV PRY I I Amplifier output level detection

5 Y5 DC_PRT PRY I I DC protection
12 Y3 THM1 +3.3S_PON I I Temperature detection 1
13 Y0 PS3_PRT AC I I Power supply protection 3
14 Y1 L3_DET VID_PON I I D terminal L3 detection
15 Y2 MODE +3.3S_PON I I Special mode distinction
86
RX-A830
IC79, 81: TC74VHC273FT (EL,K) (DIGITAL (1) P.C.B.)

Octal D-type flip-flop with clear
CLR 1 20 VCC
Q1 2 19 Q8 D1 D2 D3 D4 D5 D6 D7 D8
1 3 4 7 8 13 14 17 18
D1 3 18 D8 CLR
D R D R D R D R D R D R D R D R
D2 4 17 D7
Q2 5 16 Q7
Q3 6 15 Q6 CK Q CK Q CK Q CK Q CK Q CK Q CK Q CK Q
11
CK
D3 7 14 D6
D4 8 13 D5
2 5 6 9 12 15 16 19
Q4 9 12 Q5
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
GND 10 11 CK
Inputs Output
Function
CLR D CK Q
L X X L Clear
H L L −
H H H −
H X Qn No Change
IC79
I/O
Pin R32C external
Function Name Related Power Supply Detail of Function
No. bus data
OFF ON
2 D[8] HDMI_PON HDMI_PON O O HDMI power supply (Necessary for DSP, A-VIDEO drive)
5 D[9] HRTX_N_RST HDMI_PON O O HDMI receiver/transmitter reset
6 D[10] MHLVB_PON HDMI_PON O O MHL VBUS power supply control
H: feeding permission, L: feeding prohibition
9 D[11] FLD_PON FLD_PON O O FL driver +3.3V power supply control
12 D[12] FLD_N_RST FLD_PON O O FLD reset
15 D[13] HTX_AUSEL HDMI_PON O O HDMI transmitter sound select
16 D[14] HAU_N_OE HDMI_PON O O HDMI to DIR sound output enable
19 D[15] STBY_LED AC O O Standby LED control
IC81
I/O
Pin R32C external
Function Name Related Power Supply Detail of Function
No. bus data
OFF ON
2 D[0] HSW_N_RST HDMI_PON O O HDMI switcher reset (L period: more than 5ms)
RX-A830
5 D[1] VDEC_N_RST HDMI_PON O O Video decoder reset

6 D[2] WIFI_PON WIFI_PON O O WiFi adaptor power supply control
9 D[3] --- AC O O No used
12 D[4] FHDMI_N_RST HDMI_PON O O Front HDMI reset
15 D[5] VID_PON VID_PON O O Video power supply
16 D[6] +3.3D_PON +3.3D_PON O O OR of HDMI_PON, DSP_PON, NET_USB_PON
19 D[7] PRY PRY O O Power relay
87
RX-A830
IC61: Sii9136CTU-3 (DIGITAL (1) P.C.B.)

HDMI transmitter
CEC
40 CEC
Interface
CSDA 44 I2C Slave DDC Master 41 DSDA
CSCK 45 Interface Configuration
I2C Interface 42 DSCL
Logic and
CI2CA 43 Registers
46 INT
RESET 47 Hot Plug Detect Hot-Plug
76 HPD
Receiver Sense Detector
and Interrupt Logic 26,39,49,77
GPIO GPIO[3:0]
IDCK 22
2-4,6-11,13-15,17-20,
D[35:0] 78-87,89,90,92-99 Video Data Input
HSYNC 24 and
23 Conversion 52 EXT_SWING
VSYNC
DE 25 54,55
HDCP HDCP TXC 0
ROM TMDS 57,58
SPDIF_IN 29 Encryption TX0 0
Transmitter 59,60
MCLK 36 Engine TX1 0
62,63
SCK 35 Audio Data XOR TX2 0
WS 34 Capture Framer Mask
SD[3:0] 30-33
27,28
SL[3],DR[3]
I/O
Pin
No.
OFF ON
26 GPIO0 NC HDMI_PON --- O Unconnected: output low setting
77 GPIO1 NC HDMI_PON --- O Unconnected: output low setting
39 GPIO2 CEC_EN HDMI_PON --- O CEC function of HDMI TX1 / effective/invalidity (spare)
49 GPIO3 5HT*_PON HDMI_PON --- O HDMI out * 5VPWR output control
RX-A830
88
RX-A830
■ PIN CONNECTION DIAGRAMS

• ICs
A3V56S30FTP-G6 ADV7180BSTZ ADV7619KSVZ BD00GA3WEFJ-E2 BD7541G-TR BD7542F-E2

BD9328FJ
54 28 48 33 96 65 BD9329AEFJ-E2
97 64
49 32
4
5
8 4 3 8 4
64 17
1 1 1
1 27 1 16 128 33
1 32
D80YK113CPTP400 DM860A-AQE EN29LV640AB-90TIP

132 89
133 88
18 1
A
1 48
V 18
A 1
24 25
176 45 V
1 44
EP4CE15F23C6N 22 1 KIA7912PI LAN8700C-AEZG-TR LM19CIZ/LF

A
27 19
28 27
28 18
36 19
AB 22
1 18
A 1 GND 10 +VS
9 10 36
OUT VOUT
IN GND
AB 1 9
M12L64164A-5TG M66003-0131FP-R MFI337S3959 MX29GL256FLT2I-90Q NCP380HMUAJAATBG

54 28 48 33 1 56
49 32 4 1 3
5 6
8
3
4 1 6 4
64 17 1
1 27 1 16
28 29
NJM2068MD-TE2 NJM4565M (TE1) NJM7812FA NJW1329FH3 NT5SV8M16HS-6K
39 27 54 28
8 4
40 26
1
NJM41033V (TE2)
8 4
1 3: IN
7 1: OUT 52 14
14 2: COM
1 13 1 27
1
PCM5101PWR PCM9211PTR R2A15220FP R5F6416MADFE R1163N501B-TR-FE

132 89 R1172N301D-TR-F
RX-A830
133 88
4
36 25 5
80 51 3
37 24
1
81 50
R1171S501B-E2-FE
10
20 100 31
48 13 6
1 176 45
1 12 1 30 3
1
1 44
89
RX-A830
R1172H121D-T1-F R1EX25512ATA00A SiI9136CTU-3 SII9587CNUC-3 STR-Y6753

R1172H501D-T1-F SII9589-3CTUC 67 66
RP170H331B-T1-FE 75 51
1 88 45
76 50 1 44
3 8
4
5
1 22 23 66 45
4
67 44
RP130Q121D-TR-F
RP130Q181D-TR-F 1 7
RP130Q251D-TR-FE 3
RP130Q331D-TR-F 4 100 26
2
RP130Q501D-TR-F 88 23
1
1 25 1 22
SN74LV4051APWR SN74LVC1G17DCKR TC74LCX245FT TC74VHC157FT TC74VHC273FT (EL,K)
4 10
8 5 8 20 10
16 3 20 16
1 1 1 1 1
TC74VHCU04FT TC7SET08FU TC7WH126FU TL431ACLPR TRS3221ECPWR W25Q80BVSSIG

TC7SH08FU
TC7SH32FU
TC7SH86FU
4
7 5 8
14 3 8 1: CATHODE 8 4
4 16
1 2: ANODE 1
1 1 1 23 1
3: REF
RX-A830
90
RX-A830
• Diodes
1SS355VMTE-17 DBL155G P6KE200A RB051L-40 RB162L-40 RB501V-40

1SS400TE61 RB521S-30
Anode Anode Anode
Anode + Anode
–
AC
Cathode AC Cathode Cathode Cathode Cathode
RBQ30T65A RS103-B-D-V50 RS603M-B-C-J80 TFZGTR6.8B UDZV4.3B UF1K

TFZGTR13B UDZV5.1B Anode
TFZGTR24B UDZV7.5B
UDZV24B
UDZV36B Cathode
Anode Anode US1002FL Anode

1 2 3 –
1: Anode AC –
1 AC AC
2: Cathode AC
2
3 3: Anode + +
Cathode Cathode Cathode
• Transistors
2N5401C-AT/P 2N5551C-AT 2SA1576UBTLR 2SA1695 O,P,Y 2SA1708 2SA1770S/T-AN 2SA949 2SC3906K

2SC4468 O,P,Y 2SC2229
C
C
E
B E
B E
E B C C E B
C E B C
B C B
B CE E
2SC4081 T106 2SC4081UBTLR 2SC4115S 2SC4614S/T-AN 2SC5964-TD-E 2SD2704 K DTA044EUBTL

DTC014EUBTL
DTC044EUBTL
3
1: IN
2 2: GND
3: OUT
1
C C
C
E E
DTC023JUBTL
E B
B C 3
B E B
E 1: IN
CB
E 2 2: GND
C 3: OUT
B 1
HN4B01JE INA6002AC1-TH12-1W KTA1046-Y-U/PFY KTC3875S MCH6336-TL-E RAL035P01 μPA672T-T1-A

INC6002AC1-T112-1W KTA1837-U/P 4 4 4
4
6 6 6
5 3
3 3
3 1 1 1
1 C
C 1. Drain 1. Source 1 (S1)
1. DRAIN
1. BASE 1 (B1) E 2. Drain 2. Gate 1 (G1)
2. DRAIN
2. EMITTER (E) 3. Gate 3. Drain 2 (D2)
3. GATE
3. BASE 2 (B2) E B 4. Source
4. SOURCE 4. Source 2 (S2)
4. COLLECTOR 2 (C2) B 5. Drain 5. Gate 2 (G2)
5. DRAIN
5. COLLECTOR 1 (G2) 6. Drain 6. Drain 1 (D1)
BC 6. DRAIN
E
91
A B C D E F G H I J
RX-A830
1 ■ BLOCK DIAGRAMS
AUDIO Section Block Diagram
DAC ×4
PCM5101PWR
IC482
SCK
LRCK DA_L/R
BCK
DATA1
AV4_D
AV4 RXIN0 SCKO
IC483
AV3_D
RXIN1
HDIG_DSD0A IC922 SCK
AV3 RXIN2 IC923
LRCK
DA_C/SW
HDMI_AUD_RTN NOR Flash SDRAM
RXIN3
8Mbit 64Mbit BCK
AV2 IC924 W25Q80BVSSIG M12L64164A-5TG2 DATA2
DIR
AV1 PCM9211PTR
2 IC484
SCK
LRCK DA_SR/SL
BCK
AHCLKX0
AV2_D DATA3
MPIO_A0 BCK ACLKR1 ACLKX0
AV1_D
MPIO_A1 LRCK AFSR1 AFSX0
IC485
NCPU_SPDIF NCPU_SPDIF
IC955 IC951 MPIO_A3
DOUT AXR1[1] AXR0[5]
SCK DA_SBL/SBR
Ethernet Network HPSD1_DSD1A AXR1[2]
LRCK
NETWORK PHY Microprocessor
NCPU_MCK
MPIO_C0
AXR0[6]
BCK
NCPU_BCK HPSD2_DSD1B AXR0[3]
MPIO_C1 AXR1[3]
LAN8700 BridgeCo NCPU_WCK HPSD3_DSD2A
DATA4
MPIO_C2 AXR1[4] AXR0[4]
DM860A NCPU_SDO HWCK_DSD2B
USB (Front) MPIO_C3 AXR1[5]
HDIG_DSD0A AXR1[0]
AXR0[8]
IC481 ADL/R
IC921
VIN L/R A/D
HDMI 1 NET_DAC DSP
PCM5101PWR D80YK113CPTP400
DIGITAL IN / OUT HDMI 2
IC1
RT_MCLK HMCK MPIO_B0
RT_SCK/DCLK HBCK_DCLK
HDMI Switcher MPIO_B1
HDMI 3 IC3 IC65
RT_WS/D2B HWCK_DSD2B
SII9589-3CTUC HDMI Receiver BUFFER MPIO_B2
3 HDMI 4 ADV7619KSVZ RT_SD0/D0B
RT_SD1/D1A
TC74LCX245 HPSD0_DSD0B
HPSD1_DSD1A
MPIO_B3
RT_SD2/D1B HPSD2_DSD1B
HDMI 5 RT_SD3/D2A HPSD3_DSD2A
RT_SPDIF/D0A HDIG_DSD0A
HDMI 6
IC2
HDMI Switcher
HDMI 7 SII9589-3CTUC
AUP_MCK
HDMI IN (Front)
AUP_BCK
AUP_WCK
HDMI_AUD_RTN IC61 AUP_SDO
HDMI Transmitter IC64

HDMI OUT 1 ARC Buffer
SII9136CTU-3
TC74VHC157FT
IC62
HDMI OUT 2 HDMI Transmitter
SII9136CTU-3
4
DIGITAL • See page 115–122 →
SCHEMATIC DIAGRAM
• See page 123–125 →

OPERATION
SCHEMATIC DIAGRAM
DA_SBL/SBR
(Party mode)
MAIN
DA_SL/SR
DA_FL/FR
DA_FL/FR
NET/USB
(no use)
DA_SW
ADL/R
Z3L/R
DA_C
tip
• See page 126, 127 → ring

PHONES
shell
AV5 SCHEMATIC DIAGRAM
INL9/INR9
INL8/INR8
ADCL/ADCR
SUBL2/SUBR2
SRCIN/SLCIN
SWIN1
SBLIN1/SBRIN1
SLIN1/SRIN1
CIN1
FLIN1/FRIN1
AV6
FLOUT/FROUT
FRONT L/R
Muting
FL/FR
AUDIO 1 AV-5 INL4/INR4 ADL/R FLPreOUT/FRPreOUT
AV-6 INL3/INR3 FL/FR Tone Center Mix

CENTER
5 AUDIO 2 DA_FL/FR Control
LFE Mix
C
AUDIO1 INL2/INR2
INL1/INR1
MAIN SL/SR SURROUND L/R
AUDIO2 DA_C
SPEAKERS
Muting
C C
MASTERVOLUME
COUT
INL12/INR12
AUX SUB
ZONE 2
SBL/SBR SURROUND BACK L/R
INL5/INR5 SL/SR
ZONE 3
R, T, K, A, B, G, F, L, S models SLOUT/SROUT
Muting
SL/SR
DA_SL/SR
INL10/INR10 SLPreOUT/SRPreOUT
PHONO
ZONE 2
INL11/INR11 SBL/SBR SBLOUT/SBROUT
ZONE2/PRESENCE
Muting
ZONE 3 SBL/SBR
DA_SBL/SBR SBLPreOUT/SBRPreOUT
ANALOG IN / OUT
SBLCIN/SBRCIN
RECL1/RECR1
RECL2/RECR2
SUBL1/SUBR1
AM/FM TUNER DA_SW SW SW SWOUT
tip
DATA CLOCK IC153 R2A15220FP
YPAO ring
MUTE_SB
MUTE_C
MUTE_S
MUTE_F
MIC
Z2L/R
shell
IC303
NJM4565M
6
OPERATION
• See page 123–125 → FRONT L/R
SCHEMATIC DIAGRAM SURROUND L/R
SURROUND BACK L/R

CENTER
AV OUT
PRE OUT
AUDIO OUT Muting SUBWOOFER 1
DIGITAL
VOL_MOSI
MUTE_5ch
MUTE_SB
VOL_SCK
• See page 115–122 →

ZONE 2 Muting
SCHEMATIC DIAGRAM Muting SUBWOOFER 2
7 IC83
System Microprocessor
MUTE_ZONE 2 R5F6416MADFE MUTE_SW
92
A B C D E F G H I J
RX-A830
DIGITAL P.C.B. Section Block Diagram
• See page 116 → DIGITAL (3)

HDMI (Front) DIGITAL (2)
SCHEMATIC DIAGRAM • See page 116 →
RS-232C
SCHEMATIC DIAGRAM
USB
IC423 (Front)
HDMI Equalizer
SiI9587CNUC-3 IC32
HDMI IN 232C
2 TRS3221
DC OUT
NETWORK
IN7 IN6 IN5 IN4 IN3 IN2 IN1 OUT2 OUT1 (USB Rear)
CEC
RS232C
DV_SCL/SDA
IC62 IC61 TX/RX

HDMI HDMI
IC2 IC1
Transmitter Transmitter
HDMI Switcher HDMI Switcher HDMI_SCL/SDA HDMI_SCL/SDA
SiI9136CTU-3 SiI9136CTU-3
HDMI_SCL/SDA
SiI9589-3 HDMI_SCL/SDA
SiI9589-3
Audio Upconv I2S IC955

Ethernet PHYceiver USB_DP/DM
3 LAN8700C-AEZG-TR
HDMI I2S SD0 HDMI I2S SD1–SD3

HDMI DSD/SPDIF
RMII 50MHz
IC3
HDMI Receiver HDMI Audio HDMI Audio
XL951 IC953
HDMI_SCL/SDA
ADV7619KSVZ 24MHz NOR Flash
IC53 I2C_SCL/SDA 256Mbit
XL51 K3 J3
27MHz
SDRAM MX29GL256FLT2I
128Mbit IC956
115 116 48bit
NT5SV8M16HS-6K iPod 16bit
XL1 Authentication IC
28.63636MHz 16bit IC951
MFI337S3959 Network Microprocessor
BridgeCo
48bit 36bit DM860A
IC50
4 FPGA
EP4CE15F23C6N
35 16bit
ADCVBS
AIN1
8bit 8bit 36bit
AIN2
IC21 IC952
Video Decoder SDRAM
Video Input ADPb 47
AIN3
ADV7180BSTZ NCPU SPI Net/USB I2S 256Mbit
AIN4
48 54 A3V56S30FTP-G6
ADPr
AIN5 DV_SCL/SDA IC65 IC64
FPGA_N_CS
ADY 49 16bit Buffer ARC IC954
AIN6
TC74LCX245FT Buffer
21 22 IC77 TC74VHC157FT
XL21 Flash ROM 16bit
28.63636MHz 64Mbit
XM29LV640EBTI-70G
FLASH_N_CS FPGA SPI
IC481
Net/USB I2S
DAC USB_L / R Zone2
5 IC79 PCM5101PWR Analog Audio
D-FF1 16bit NCPU SPI
TC74VHC273FT
2pcs Net/USB I2S
IC81
DFF1_N_CS
HDMI_ARC
Audio Upconv I2S SD4

HDMI_SPDIF
HDMI I2S SD0 MPIO_B

HDMI_SPDIF
MPIO_C
DV_SCL/SDA HDMI_ARC
16bit
37 AV1_D
IC924
EBIU SPI6 UART8 SPI9 35 AV2_D
HDMI I2S SD0–SD3 DIR
HDMI DSD DIR I2S
A Video I2C2
MAIN PCM9211PTR 32 AV3_D SPDIF Input
Output
5,6 3 AV4_D
6 HDMI_SCL/SDA I2C3 IC83 IC921
AM/FM Tuner I2C4 System Microprocessor DSP SPI DSP
R32C/116A 47,48 AD_L / R
I2C5
R5F6416MADFE
SPI0 D80YK113CPTP400 DSP SPI ADC Analog Input
FL display Buffer SPI10
16bit
39 40
IC76 XL921
IC82 166
Analog Mux AN6
RAM: 96K Byte 24.576MHz
DSP I2S SD0–SD3
EEPROM SN74LV4051APWR IC482
FL / FR
ROM: 1M Byte 16bit
512kbit DAC SRL / SRR
R1EX25512ATA00A IC78
167 IC922 IC923 PCM5101PWR SBL / SBR
Analog Mux AN5
Clock:50MHz SDRAM Serial Flash 143 145
C / SW
MAIN Zone
SN74LV4051APWR AN4
64Mbit 8Mbit XL922
AN3
W25Q80BVSSIG 20MHz IC484
170 M12L64164A-5TG2
KY_AD2 AN2 IC485
171
KY_AD1 AN1 IC483
• See page 115–122 → 22 24
7 DIGITAL (1)
SCHEMATIC DIAGRAM XL75
8MHz CERALOCK
93
A B C D E F G H I J
RX-A830
VIDEO Section Block Diagram
CEC
V-AUX
IN7
IC423 IC2
HDMI Equalizer HDMI Switcher
SiI9587CNUC-3 SII9589-3CTUC
2
IN6
IN5
IC3
HDMI Receiver
V-AUX ADV7619KSVZ
HRX_CLK LLC
HRX_HS HSYNC
IN4
AD_CVBS HRX_VS VSYNC
AIN1 HRX_DE DE
HRX_D[0:48] Q[0:48]
AIN3
3 AIN2 IC21 IC50
AD_Pr VIDEO Decoder FPGA IC1
IN3
AIN5 ADV7180BSTZ EP4CE15F23C6N HDMI Switcher HDMI
SII9589-3CTUC
AD_Pb
AIN4 P[8:15] VDEC_Y[2:10]
Field/DE VDEC_DE
HTX_D[0:35]
AD_Y LLC VDEC_CLK
HTX_CLK
AIN6
HTX_DE
HTX_HS
HS VDEC_HS
HTX_VS
IN2
VS VDEC_VS
IC345
NJM41033V
IC61
IN1
HDMI Transmitter
4 SII9136CTU-3
Q[0:35]
DE
VSYNC
HSYNC
IDCK
OUT1
IC341
NJW1329FH2
IC62 HDMI OUT
AV5 HDMI Transmitter
SII9136CTU-3
OUT2
VIN1 Q[0:35]
AV6
VIN2 DE
VIDEO VIN3 VSYNC
5 VIN4 VOUT1
HSYNC
6dB 75Ω IDCK
AV4 VIN5

VIN6
VIN7
AV3 SCHEMATIC DIAGRAM
VOUT2
6dB 75Ω
AD_CVBS
75Ω MONITOR OUT
YIN1
VIDEO
YIN2 YOUT
6dB 75Ω
YIN3 AV OUT
6
AD_Y
PBIN1
PBIN2 PBOUT AD_Pb COMPONENT
AV2 PBIN3 6dB 75Ω VIDEO MONITOR OUT
AD_Pr
COMPONENT
PRIN1
VIDEO
PRIN2 PROUT
6dB 75Ω
PRIN3
AV1
• See page 123–125 →

7 OPERATION
SCHEMATIC DIAGRAM
94
A B C D E F G H I J
RX-A830
Power Supply Section Block Diagram
Speaker Impedance relay

Power
Transformer +B
Power Amplifier
IC944 +5.6V IC4
BD9328EFJ +1.8D BD9329EFJ
In Out +1.8D In Out +1.2DH
FUSE +5.6V +1.8D HDMI Switcher/Transmitter
+1.8D +1.2DH
+ - FPGA
Adj
Adj
+3.3D_PON HDMI_PON
IC929
2 -B
Power Amplifier
R1172H121D-T1-F
In Out
+1.2DSP1
IC60
DSP
+1.2DSP1 R1163N501B-TR-FE
In Out +5HT1
Gnd
DSP_PON +5HT HDMI1 OUT +5Power
Gnd
5HT1_PON
IC63
RAL035P01 +1.8H HDMI Receiver R1163N501B-TR-FE
VIDEO Decoder In Out +5HT2 HDMI2 OUT +5Power
+5HT
IC103
Gnd
NJM7812FA 5HT2_PON
In Out +12V
Operational Amplifier
+12V HDMI_PON
R +7A
Volume IC IC8
Gnd
RP130Q501D-TR
In Out +5H
+5H
HDMI Receiver
IC57 Front HDMI IN Equalizer
Gnd
RP130Q121D-TR-F HDMI_PON
In Out +1.2FPLL
+1.2FPLL FPGA PLL
IC413
Gnd
NCP380
Gnd
R -7A R1171S501B-E2-FE
3 In -12V Out -12V
Volume IC HDMI_PON In
MHLVB
Out MHLVB
MHL
Operational Amplifier
Gnd
KIA7912PI HDMI_PON
IC104 MHLVB_PON snd CD_SENSE
IC931
RP130Q501D-TR
RAL035P01 (+1.8HL) In Out +5DSP
KTA1046 Trigger out Optical/Coaxial IN
+5DSP
Trigger out
Gnd
DSP_PON
IC421 IC930
+ - DC_TRG
HDMI_PON R1172H121D-T1-F RP130Q331D-TR-F
In Out +3.3DR1
In Out +1.2HF +3.3DR1 DIR
Front HDMI IN Equalizer
MAIN • See page 126–127 → +1.2HF
Gnd
DSP_PON
Gnd
SCHEMATIC DIAGRAM IC85
RP130Q331D-TR-F
In Out +3.3M
Microprocessor
+3.3M
IC943
Gnd
BD9329EFJ
4 PL1
In
+3.3D
Out +3.3D
+3.3D
IC382 IC84
AC IN
Adj
RP170H331B-T1-FE RP130Q331D-TR-F
+3.3S
In Out +3.3A DAC In Out
Microprocessor
+3.3S
+3.3A
RAL035P01 +3.3DSP DSP
Gnd
Gnd
DC-DC Converter
IC343 +3.3D_PON +3.3S_PON
for DAC Tuner
BD00GA3WEFJ-E2
In Out +5A (4.7V)
MCH6336 +5A DIR ADC
Gnd
AC-DC Converter DSP_PON
40W (5.6V/7.2A)
In Out +5T
AM/FM Tuner
+5T
R
Gnd
- + R
IC344
DAC_PON BD00GA3WEFJ-E2 RAL035P01 +3.3N
IC940
DCDC_PON (DSP_PON) R1172H501D-T1-F
NETWORK
In Out +5VBus
+3.3RAM +5WiFi
DC-DC Converter IC342 WiFi Adaptor power
Gnd
PRY
5 for Video RP170H331B-T1-FE
In Out +3.3V
NCPU_PON NCPU_PON
Video
+3.3V
MCH6336
VIDEO_PON
Gnd
IC56
R1172N301D-TR-F IC942
R BD7541 In Out +3.0FPGA
BD9328EFJ
+3.0FPGA FPGA In Out +1.2N
R +1.2N NETWORK
Gnd
HDMI_PON
Adj
-3.3V
Video
IC55
2N5401C NCPU_PON
DCDC_PON (DSP_PON) RP130Q251D-TR-FE
In Out +2.5FPGA
+2.5FPGA
FPGA
Gnd
HDMI_PON
RAL035P01 RAL035P01 +5USB
DC-DC Converter USB
for FL
2N5401C RAL035P01 +3.3HL +3.3HF
-VP FHDMI
MCH6336
IC946
6 VFD
RP130Q331D-TR-F ..
USB_VBIS_PON
In Out
R F1 HDMI_PON +3.3
BD7542F
Gnd
R F2
RAL035P01 +3.3H HDMI Transmitter/Receiver/Switcher

FPGA
VIDEO Decoder
IC302
RP130Q331D-TR-F
In Out +3.3FLD IC6
+3.3V
VFD HDMI_PON RP130Q181D-TR-F
In Out +1.8HRPLL
HDMI Receiver PLL
Gnd
FLD_PON +1.8HRPLL
Gnd
HDMI_PON
• See page 123–125 → IC27

OPERATION
RP130Q181D-TR-F
In Out +1.8DPLL
7 SCHEMATIC DIAGRAM +1.8DPLL VIDEO Decoder PLL
SCHEMATIC DIAGRAM
Gnd
+1.8H
95
A B C D E F G H I J
RX-A830
1 ■ WIRING DIAGRAMS
• OVERALL ASSEMBLY
Top view
OPERATION (8) DIGITAL (3) Side view
AM/FM
MAIN (2) OPERATION (9)
TUNER
Power cable R, S models
80 mm
(3-1/8")
to OPERATION (4)
to OPERATION (3) CB945
2 (CB381) CB381 OPERATION (4)
Cord Stopper (CB371) DIGITAL (1)
to OPERATION (2)
CB76
to OPERATION (3) (CB344) OPERATION (2)
(W3703)
PN941 CB946
OPERATION (3) to OPERATION (3) to MAIN (1)
CB942 W113
(W3704) CB952 (W113)
T model CB412
CB944 CB411
to MAIN (1)
PN102 W114
CB76 PN948 PN942 PN946 CB948 (W114)
CB8 CB79 CB78 CB80 CB82

PN941
to OPERATION (3)
(CB374) CB942 CB947 Bend the cables
MAIN (1) (W106)
CB944
3 POWER PN944
MAIN (1) PN943
TRANSFORMER PN105
W112
K, B, G, F models
MAIN (5)
MAIN (3)
MAIN (6)
CB76 W4202 MAIN (4)
to OPERATION (3)
(CB374) to DIGITAL (1) (CB411)
PN301 PN106
PN941
CB942 CB302 CB422
PN109 to OPERATION (1)
CB944 (W3005)(W3006) to DIGITAL (2) (W4201)(W4202) View A
4 W4201
to DIGITAL (1) (CB412)
CB303 CB306
AMP UNIT DIGITAL (2)
Place wires as per drawing

W4202 not to touch with heatsink.
W4201
5 DIGITAL (2)
Tighen up and cut

not to toutch with heatsink.
Front panel (View A)
Flexible flat cable 20 mm

OPERATION (7) DIGITAL (2) (3/4")
OPERATION (6)
to OPERATION (1)
W4201 (CB305)
Letter side
to OPERATION (2)
Letter side
(CB343)
6 W4202 CB301 CB303
W3002B
Flexible flat cable 25 mm
OPERATION (10) (1")
to DIGITAL (1)
to OPERATION (2) (CB82)
CB305
CB308 (CB343)
CB306 to OPERATION (1) 20 mm
OPERATION (1) Letter side (3/4")
CB304 (CB304)
W3002A to DIGITAL (1)
(CB82)
Blank side
OPERATION (5) 140 mm (5-1/2")

to DIGITAL (1)
to DIGITAL (1) (CB8) to DIGITAL (1) Letter side
7 (CB947) (CB952) (CB411) (CB412)
96
A B C D E F G H I J
RX-A830
• AMP UNIT
T model
Top view
OPERATION (8) AM/FM
CB374 TUNER OPERATION (9)
PN102
2 PN109 W3704
to DIGITAL (1)
(CB944)
PN371 W103B
CB391 CB361 W104B OPERATION (2)
W3707
CB344
W3703 to OPERATION (8) CB384
CB374 to DIGITAL (1) W105 (CB391) W105
K, B, G, F models to DIGITAL (1) W107
(CB942) CB103 (CB76)
W106 W110
CB342
PN102 CB101
CB374 CB102 CB346
CB343
PN102
PN109 CB347
OPERATION (2)
PN109
3 W108
PN341 W101A
W109
to DIGITAL (1)
OPERATION (3) W101C
PN108 (CB78)(CB80)
MAIN (1) PN101 W104A
to MAIN (1)
(W106) W103A MAIN (1)
to DIGITAL (1) to DIGITAL (1)

POWER (CB947)(CB952) (CB79)
TRANSFORMER from W106
to OPERATION (7) W101D W101B
(CB308) W112
4 to OPERATION (1)
(CB303)
OPERATION (7)
MAIN (5)
PN301
CB302 MAIN (3)

to OPERATION (1)
(W3005)(W3006) MAIN (4)
5
AMP UNIT
97
A B C D E F G H I J
RX-A830
1 ■ PRINTED CIRCUIT BOARDS

Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location Ref no. Location
IC76 E5 IC82 G4 IC92 G5 IC481 I5 IC921 H5 IC929 G4 IC943 D5 IC951 I4 Q11 D4 Q250 C3 Q763 G6 Q4104 E5 Q9402 E5
IC77 F4 IC83 F5 IC93 G5 IC482 I4 IC922 H5 IC930 H5 IC944 D4 IC952 H3 Q12 D4 Q251 C3 Q765 F6 Q4105 E4 Q9404 D5
DIGITAL (1) (Side A) IC78 F5 IC84 G6 IC411 E5 IC483 I5 IC924 H5 IC931 I3 IC946 D6 IC953 H4 Q17 D4 Q252 C3 Q4101 E5 Q4106 E4 Q9405 D5
IC79 E4 IC85 F6 IC412 E5 IC484 I5 IC926 H5 IC940 I3 IC947 E6 IC955 I3 Q21 D4 Q253 C3 Q4102 E4 Q4107 E5 Q9406 D5
IC81 E5 IC91 G5 IC413 E5 IC485 I5 IC927 H4 IC942 C5 IC949 G5 IC956 I3 Q22 E5 Q762 E5 Q4103 E5 Q9401 E5 Q9408 E5
No replacement part available. No replacement part available.
HDMI 1
NETWORK DC OUT
2 HDMI 7 HDMI 6 HDMI 5 HDMI 4 HDMI 3 HDMI 2 (BD/DVD) HDMI OUT 2 HDMI OUT 1
(NET)
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB62 CB61
CB940
5 4
DIGITAL (3) CB951
IC63
(W31) 1 3 OPERATION (4)
IC9 5 (CB381)
1
3 1
4 5
DGND 25 1
75 51
3 4 1
76 5
232C_MOSI IC56 50 IC60 RM-
CB75
26
IC940
100 4 3 7
232C_MISO 5 1 1 RM+
+3.3M 25 1 IC62
27
1 3 4 RMS_OUT
26 100 IC66 DGND
IC2
8 14 36 28
AV4_D
26 IC952 1 27 DGND
AV3_D
CB945
3
IC955
50 51 100
OPERATION (2) 75 76 IC1 1 25
76
75 51
50
DGND
(CB344) 28 54 9 10
18
19 AV2_D
50 75 76 +5DSP
51 IC61
AV1_D
4 1
ADPr IC956
2 3
IC931
DC_TRG
1 2
VE IC27 56 26 1 4 +5AE
ADPb 26 5 +5A
+3.3V ADY 4 3 100 +3.3A
VE 1 25
ADCVBS 17 128 97
VE VID_PON
IC50
33 32
CB76
16 1 96
IC953
8 1
L3_DET
PS2_PRT
IC951
VID_SCL IC21 IC3
VID_SDA IC64
TUN_N_INT 9 16
TU_N_RST 48 1 10 1
TU_SCL
TU_SDA
49 64 MAIN (1)
DCDC_PON 32 65
33 64 1 28 (CB154)
IC65
11 20
4 DAFR
AGND
25 24
IC8
3 4
8 5
DAFL
CB952
+5.5V IC4 8 5 IC77 AGND
2 1
+5.5V IC944 DAC
OPERATION (3) 4 3
(For factory)
IC929
CB942
1 4
CB953 AGND
(W3703) DGND 1 4 5
1
11
10
DASW
48
DGND 20 11 1
CB946
AGND
IC482
4
IC82
5
IC79 8 1 3 1 DASR
1
20 AGND
IC927
132 89
1 8 4 5
CB943 DASL
IC93
8 IC943 5 1 10 133 88 176 133 24 13
8 5 10
+3.3M IC942 4 5 1
132 3 1
25 12
11 AGND
CB412
IC924
DGND
IC926
IC483
4 3 DASBR
CB944
1 4
ACPWR_DET
IC413
OPERATION (3) MCPU_N_RST (for service) 1 4

6 1
4 5 36 1
20 1
AGND
(W3704) 20 11 37 48 DASBL
PRY 10
IC83 5 4 5 4
DEST IC411 IC412 3 IC81 11
IC921
CB411
6 4
IC484
4
1 3
5 1
31 3
IC94
1
IC92
1 10 1
20
5 No replacement part available. 11
10
USBR
IC485
176 45
8 1
8 1
1 44 44
89
USBE
45 88 2 3
IC75 IC930 20
1 USBL
• Semiconductor Location 1
CB948
4 3
DGND IC76 3 1 4 AGND
IC949
5 1 10
DIGITAL (2) 9 16
IC78
54 28
11 ADR
Ref no. Location Ref no. Location +1.8HL AGND
IC481
16 4 5
(W4201) 9 CB84
+3.3HL ADL
D38 E5 D9502 I4 IC922 20 1
D602 G3 IC1 D3
4 1 (Writing port)
DGND IC947 MAIN (1)
D602 H3 IC3 E4 MHLVB IC946
4 1 5 8 2 3 1 27 (CB155)
IC85 2 3
3 2 1 4
D604 G2 IC4 C4 1 4
IC84
D605 G2 IC8 C4 DIGITAL (2) CB82
CB79 CB80
(W4202)
D606 G2 IC21 C4 CB947 CB8
6
+5USB
+5USB
GND
GND
D607 H2 IC27 C3 CB81
HP_N_DET
SPRY_Z2
SPRY_SB
HPRY
SPRY_5CH
MUTE_SW
MUTE_Z2
MUTE_5CH
MUTE_SB
THM3_PRT
D608 H2 IC50 F4
FLD_N_RST
FLD_SCK
MIC_N_DET
RM-
ISEL_RA
PS2_PRT
PSW_DET
KY_AD2
VDL_RB
FLD_PON
STBY_LED
+5.5
DGND
THM2
THM1
DGND
+3.3S
DCDC_PON
R_200_DET
SP_IMP
PS2_PRT
PS1_PRT
AMP_LMT
AMP_OLV
I_PRT
DC_PRT
VOL_SCK
MG
VOL_MOSI
D609 H2 IC56 F4 OPERATION (1)
(W3005)
D4103 D5 IC60 H3
VBUS
D-
D+
GND
FG
DGND
Data2+
Data2-
Shield2
Data1+
Data1-
Shield1
Data0+
Data0-
Shield0
DataC+
DataC-
ShieldC
CEC
PD
CD_SENSE
FR_N_INT
+5H
TPWR
FR_N_RST
FR_SCL
FR_SDA
D4105 D5 IC61 G3
FLD_N_CS
FLD_MOSI
REM_IN1
RM+
ISEL_RB
DGND
KY_AD1
VDL_RA
PD_LED
+3.3M
+5.5
DGND
IC62 G3 MAIN (3)
D9401 C5 (W112)
D9402 G5 IC62 G2 MAIN (1) (W109) MAIN (1) (W108) OPERATION (1)
DIGITAL (2)
D9403 G5 IC64 G4 (CB422)
(W3006)
D9404 G5 IC65 G4 No replacement part available.

D9405 G5 IC66 H3
OPERATION (1)
D9501 I4 IC75 F5 (CB304)
7
98
A B C D E F G H I J
RX-A830
DIGITAL (1) (Side B)
No replacement part available.

2 • Semiconductor Location
Ref no. Location
D750 D6
D9406 B5
D9407 B5
IC6 F3
IC53 D4
IC55 E3
4
3
1
IC55
2
IC57 E3
54 28 4 1
4 1
IC57
IC6
3 2 IC80 D5
3 2
3 IC954 IC87 D5
27
IC923 D5
1
IC954 C3
Q18 G4
Q750 E5
28 27
Q751 E5
Q752 E5
Q753 E5
Q754 E6
IC53
Q755 E5
Q756 C6
4
54 1 Q757 D6
Q758 C6
Q759 D6
Q760 C6
Q761 E5
Q9201 F4
8 5 4 IC803 Q9202 F4
IC923 5 1
1 4
4 3
5 1
99
A B C D E F G H I J
RX-A830
2 DIGITAL (2) (Side A) DIGITAL (3) (Side A)
VIDEO AUX
HDMI/
MHL
CB421
3
RS-232C

CB33
16 1
17 64
IC423 W31
3 1
16
32 49 1
4 IC421
IC32
33 48
4 5
8 9
W4202
CB422
MHLVB
DGND
DGND
232C_MOSI
232C_MISO
+3.3M
W4201
+3.3HL
+1.8HL
DGND
FR_SDA
FR_SCL
FR_N_RST
TPWR
+5H
FR_N_INT
CD_SENSE
PD
CEC
ShieldC
DataC-
DataC+
Shield0
Data0-
Data0+
Shield1
Data1-
Data1+
Shield2
Data2-
Data2+
DGND
DIGITAL (1)
DIGITAL (1) (CB411)
(CB412) DIGITAL (1)
5 (CB75)
DIGITAL (1)
(CB8)
• Semiconductor Location
Ref no. Location
D4201 C3
D4205 C3
IC32 H4
6 IC32 B4
IC423 C4
100
A B C D E F G H I J
RX-A830
2 DIGITAL (2) (Side B) DIGITAL (3) (Side B)
4 3
IC424
5 1
Ref no. Location
D4202 D3
D4203 D3
D4204 D3
IC424 C4
101
A B C D E F G H I J
RX-A830
OPERATION (10)
OPERATION (1) (Side A) (W3002B)
ISEL_RB
DGND
ISEL_RA
+3.3M
DIGITAL (1)
(CB82)
2 FLD_N_RST
FLD_N_CS
FLD_SCK
FLD_MOSI
MIC_N_DET
REM_IN
RM- PURE DIRECT
RM+
ISEL_RA
CB304
ISEL_RB indicator
PRV2
PSW_DET
DGND Remote control
KEY1 sensor
W3002A
KEY2
VDL_RA OPERATION (5)
VDL_RB
PD_LED (CB308)
FL_PON
+3.3M
STBY_LED
+5.6
+5.6 MASW
DGND
DGND
CB306
DGND
DGND
PURE DIRECT +3.3M
STBY_LED
3 VAUX
VAUXE
-12V
CB305
OPERATION (2) E
TUNING
(CB343) +12V
MIC AM FM PRESET MEMORY INFO ZONE CONTROL ZONE 2
AUXL
AUXE
AUXR
SCENE
RADIO BD/
NET TV
DVD W3005
4
FG
MIC_N_DET
CB303
GND
GND
VBus
VBus
-12V W3006
E
MIC
+12V DIGITAL (1)
(CB947)
CB307
VOLUME
PROGRAM
STRAIGHT TONE
CONTROL USB jack
FG
GND
+Data
-Data
VBus
VIDEO AUX
DIGITAL (1)
R AUDIO L VIDEO (CB952)
5
Ref no. Location
OPERATION (6) (Side A) D3012 E3
D3018 C2
Q3014 C2
6
FG
MIC_N_DET
CB301
-12V
E
MIC
+12V
YPAO MIC
JK301
102
A B C D E F G H I J
RX-A830
OPERATION (1) (Side B)
2
49 48
64 IC301 33
1 32
4 3
16 17
1 2
IC302
3
Ref no. Location Ref no. Location
OPERATION (6) (Side B) D3001
D3003
D7
D7
D3027
IC301
F5
E2
D3006 D7 IC302 C3
D3009 C3 IC303 D7
6 D3010 D2 Q3001 F2
D3011 D2 Q3002 F2
D3013 C2 Q3003 F2
D3014 C2 Q3004 F2
D3015 C2 Q3006 C3
D3016 C2 Q3008 C3
8 5 D3017 C2 Q3011 C2
IC303
D3022 F5 Q3012 C2
1 4 D3023 F5 Q3013 B3
D3025 F5
103
A B C D E F G H I J
RX-A830
OPERATION (2) (Side A) OPERATION (9) (Side A)
2
VE
AV3_V
VE
AV4_V
VE
Lch
Rch
SCL
RST
-
OPERATION (1)
(CB305)
+5T
GND
GPIO2
SDA
VAUXE
AUXE
MICE
+12V
VIDEO
AM/FM TUNER
AUXR
VAUX
AV3
AUXL
AV4
-12V
MIC
(TV)
MAIN (1)
(W107)
CB347
+5.6 CB343
DGND
CB361
CB342
VE
VE
VE
4
AV3_V
AV4_V
CB346
DCDC_PON
TUN_SDA
TUN_SCL
TUN_N_RST
TUN_N_INT
VID_SDA
VID_SCL
CB344
PS2_PRT
L3_DET
VID_PON
VE
AD_V
VE
AD_Y
+3.3V AUXR
AD_Pb E
VE
AD_Pr AUXL
5 +12V
MIC
DIGITAL (1) -12V
(CB76) NC
CB345
NC • Semiconductor Location
PS2_PRT
DCDC_PON
Ref no. Location
+5AE Q3413 E4
+5A
TUR
TUE
TUL
OPERATION (4)
6 (CB383)
Pr/Pb/Y Pr Pb Y
COMPONENT
VIDEO AV6 AV5 AV2/AV1
VIDEO
7
MONITOR COMPONENT
AV OUT VIDEO
OUT VIDEO
104
A B C D E F G H I J
RX-A830
OPERATION (2) (Side B) OPERATION (9) (Side B)
3
8 5
3 1
IC346
IC343
14 8
1 4 4 5
3 1 IC345
IC342
8 5
IC344 4 5 1 7
1 4
40 39 • Semiconductor Location
5 52
IC341
27 D3403 F5 IC342 E4
1 26 D3404 B4 IC343 D3
D3406 D3 IC344 D4
13 14 D3407 D3 IC345 E3
D3408 D4 IC346 D3
D3409 D4 Q3401 F5
D3412 E4 Q3402 B3
D3413 E4 Q3404 F5
D3414 C3 Q3405 B3
D3415 C3 Q3407 F4
D3416 C3 Q3408 E4
6
D3417 C4 Q3409 C3
D3420 E4 Q3410 C3
D3421 E4 Q3420 D5
IC341 D5
105
A B C D E F G H I J
RX-A830
OPERATION (3) (Side A) Ref no. Location
OPERATION (4) (Side A)
D3701 C4
D3704 E4 OPERATION (2) DIGITAL (1)
D3716 D4 (CB345) (CB945)
IC372 D3
IC373 E3 AUXR +3.3A
E +5A
2 IC374 D6 AUXL +5AE
+12V DC_TRG
IC375 C4 AV1_D
MIC
Q3801 J4 -12V +5DSP
NC AV2_D
Q3802 J4 NC DGND
PS2_PRT AV3_D
Q3803 J4 MAIN (1) DGND
DCDC_PON
Q3804 J4 +5AE (W110) AV4_D
+5A DGND
TUR RMS_OUT
TUE E RM+
5 k-ohms RM-
TUL +18V
10 W
3 MAIN (1)
(CB153)
CB384
IC372
K A R TUL
IC373 TUR
TUE
MIC
CB382
E
AUXL
AUXR
CB381
IC375
CB383
E
E
1 7 +12V
-12V
JK383 JK382 JK381
OUT IN
5
OPTICAL COAXIAL OPTICAL
CB374 AV 1 AV2 AV3 AV4 REMOTE TRIGGER
W3703
OUT
POWER TRANSFORMER
GND
GND
5.6V
5.6V
CB371 IC374
W3707
U, C, R, K, A, B, G, F, L, S models
DIGITAL (1)
(CB942)
W3704 Safety measures

DEST
PRY
CPU_N_RST
ACPWR_DET
DGND
+3.3M
• Some internal parts in this product contain high voltages and are dangerous. Be sure to take safety measures during servicing, such
GND
5.6V
as wearing insulating gloves.

AC IN MAIN (1) • Note that the capacitors indicated below are dangerous even after the power is turned off because an electric charge remains and a
(CB102) high voltage continues to exist there. Before starting any repair work, connect a discharging resistor (5 k-ohms/10 W) to the terminals
of each capacitor indicated below to discharge electricity. The time required for discharging is about 30 seconds per each.
DIGITAL (1) C3706 on OPERATION (3) P.C.B.
(CB944)
106
A B C D E F G H I J
RX-A830
4 3
IC382
5
1
4
1 14
IC381
8
7
D3702 C4 D3713 C5
D3703 C5 D3714 C6
D3705 C3 D3715 C6
D3706 A4 D3801 I4
D3707 D6 D3802 I4
D3708 D6 IC381 H4
6 D3709 D6 IC382 H4
D3710 D6 Q3701 D6
D3711 D6 Q3702 D6
D3712 C6 Q3703 D6
107
A B C D E F G H I J
RX-A830

PHONES
SILENT CINEMA
Standby indicator
MAIN ZONE
CB308 JK302
CB302
3
MASW
DGND
DGND
+3.3M
STBY_LED
HPR
HPE
HPL
HP_N_DET
OPERATION (1) Ref no. Location
(CB306)
D3021 D2
MAIN (1)
(W106)
4
SPEAKERS
ZONE2/
F.PRESENCE
R L
+/- +/-
OPERATION (1)
(W3002A)
ISEL_RB
ISEL_RA
DGND
+3.3M
5
W3002B
INPUT
CB391
EX_R
EX_L
EX_RE
EX_LE
7 MAIN (1)
(W105)
108
A B C D E F G H I J
RX-A830
Ref no. Location
D3002 G2
D3004 G2
Q3015 C3
3
4
109
A B C D E F G H I J
RX-A830
1 Ref no. Location Ref no. Location
SPEAKERS D1040 H4 Q1019 C5
18V
E
GND
5.5V
MAIN (1) (Side A) OPERATION (4) FRONT CENTER SURROUND SURROUND BACK / D1051 F3 Q1020 C5
OPERATION (2) BI-AMP IC103 F4 Q1021 C5
(CB384) (CB347)
R, T, K, A, B, G, F, L, S models IC104 F4 Q1022 H6
R L R L R L
PHONO AUDIO1 AUDIO2 AV5 AV6 AV ZONE OUT PRE OUT Q1015 E5 Q1023 G6
OUT ZONE 2 CENTER/ Q1016 E5 Q1024 F6
FRONT SURROUND SUR.BACK SUBWOOFER
Q1017 D5 Q1025 E6
L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R 1/2
Q1018 D5 Q1026 D6
Q1027 C6
2 Q1028 B6
Q1029 H5
EX_LE
EX_RE
ES_L
EX_R
OPERATION (8)
OPERATION (4) W102B (CB391)
(CB382) BL
HPR
W103B E
-12V HPL
+12V W104B HP_N_DET
E
CB153
AUXE
AUXR
AUXL
MICE OPERATION (7)
MIC (CB302)
TUE W105
3 TUR
TUL
W106
CB102
W110
GND OPERATION (3)
5.5V (W3707)
CB103
CB101
W107
AC12
E POWER
BL W102A AC12
DAFR TRANSFORMER
AGND
DAFL
AGND
DAC
AGND
CB154
DASW
DIGITAL (1) AGND
(CB946) DASR
AGND IC104
COM IN OUT
DASL
4
E
E
AC_BL
AC_BL
AC_BH
AC_BH
IN COM OUT
AGND
DASBR
AGND IC103
DASBL
POWER
W108
TRANSFORMER
W112A
USBR RE
THM3_PRT
MUTE_SB
MUTE_5CH
MUTE_N_Z2
MUTE_N_SW
SPRY_5CH
HPRY
SPRY_SB
SPRY_Z2
HP_N_DET
W112C
USBE W109
USBL
CB155
AGND BE
ADR
AGND 5 k-ohms
ADL
10 W DIGITAL (1)
DIGITAL (1) (CB80)
(CB948)
W104A
5 W103A
AMP_OLV
AMP_LMT
VOL_MOSI
MG
VOL_SCK
DC_PRT
I_PRT
PS1_PRT
PS2_PRT
SP_IMP
R_200_DET
-
5 k-ohms
10 W
DIGITAL (1)
(CB78)
Ref no. Location Ref no. Location Ref no. Location

RE Q1030 G5 Q1045 F6 Q1055A C6
W101B BE
Q1031 F5 Q1046 E6 Q1055C D6
Q1032 E5 Q1047 D6 Q1056A B6
6 W101D
Q1033 E5 Q1048 C6 Q1056C C6
Q1034 D5 Q1049 B6 Q1067 H5
Q1035 C5 Q1050A G6 Q1068 G5
Q1036 H6 Q1050C H6 Q1069 H5
Q1037 G6 Q1051A G6 Q1070 H5
Q1038 F6 Q1051C G6 Q1071 H5
Q1039 E6 Q1052A F6 Q1072 B5
Safety measures Q1040 E6 Q1052C F6
• Some internal parts in this product contain high voltages and are dangerous. Be sure to take safety measures during servicing, such
as wearing insulating gloves. Q1041 D6 Q1053A E6
• Note that the capacitors indicated below are dangerous even after the power is turned off because an electric charge remains and a Q1042 C6 Q1053C E6
7 high voltage continues to exist there. Before starting any repair work, connect a discharging resistor (5 k-ohms/10 W) to the terminals Q1043 G6 Q1054A D6
of each capacitor indicated below to discharge electricity. The time required for discharging is about 30 seconds per each.
C1084, C1085 on MAIN (1) P.C.B.
Q1044 F6 Q1054C D6
110
A B C D E F G H I J
RX-A830
MAIN (1) (Side B)
D1001 D5 IC154 E3
R, S models
D1002 D4 IC156 B2
R, T, K, A, B, G, F, L, S models
D1003 G5 Q1001 E4
2
D1004 G5 Q1002 E4
D1005 G5 Q1003 D4
D1006 G5 Q1004 D4
4 1
D1007 F5 Q1005 D4
IC156 D1008 F5 Q1006 D4
5 8
D1009 E5 Q1007 C4
4 1
D1010 E5 Q1008 C4
IC154
D1011 D5 Q1009 C4
5 8
51 50
D1012 D5 Q1010 C4
D1013 C5 Q1011 B4
3 31
30
D1014 C5 Q1012 B4
3
15
80
D1015 B5 Q1013 B4
IC
81
D1016 C5 Q1014 B4
100 1
D1017 G6 Q1057 G5
D1018 G6 Q1058 F6
D1019 F6 Q1059 E6
D1020 E4 Q1060 D5
D1021 D6 Q1061 C5
D1022 C6 Q1062 C5
D1023 B6 Q1063 B6
D1024 G5 Q1064 E5
4
D1025 F5 Q1065 F5
D1026 E5 Q1073 H4
D1027 D5 Q1074 F3
D1028 D5 Q1075 F3
D1029 C6 Q1076 H3
D1030 B5 Q1077 H3
D1031 F5 Q1078 G3
D1032 D5 Q1079 G3
D1033 D5 Q1500 D2
D1034 D5 Q1501 D4
5 D1035 F5 Q1502 D4
D1036 D5 Q1503 D2
D1037 F5 Q1504 E4
D1038 G5 Q1507 E3
D1039 G5 Q1509 E6
D1042 B5 Q1511 D2
D1043 F4 Q1512 D3
D1044 F3 Q1513 D2
D1045 F3 Q1514 D3
D1046 H3 Q1519 E2
6 D1047 H3 Q1520 C4
D1048 G3 Q1521 C4
D1049 G3 Q1522 E2
D1050 H4 Q1523 E2
D1501 D3 Q1524 B4
D1502 D3 Q1525 B4
D1503 B3 Q1526 E2
D1504 B3 Q1527 E4
IC153 C3
111
A B C D E F G H I J
RX-A830
MAIN (2) (Side A) MAIN (3) (Side A) MAIN (4) (Side A)

R, S models
POWER
TRANSFORMER VOLTAGE
SELECTOR
110–120V 220–240V U, C models
OR
RE
YE
VI
IC101
IC102
CB111
W112
+3.3S
DGND
THM1_PRT
THM2_PRT
3
DIGITAL (1)
(CB79)
Ref no. Location
IC101 E2
IC102 F2
MAIN (5) (Side A) MAIN (6) (Side A)
112
A B C D E F G H I J
RX-A830
MAIN (2) (Side B) MAIN (3) (Side B) MAIN (4) (Side B)

R, S models
MAIN (5) (Side B) MAIN (6) (Side B)
113
RX-A830
MEMO MEMO
114
A B C D E F G H I J K L M N
RX-A830
SCHEMATIC DIAGRAMS
Page 116 L8
DIGITAL 1/8
to DIGITAL (2)_CB422
1
HDMI 7 HDMI 6 to DIGITAL(2) HDMI 5 HDMI 4 HDMI 3 HDMI 2 HDMI 1
002.sht (BD/DVD)
(Front HDMI)
CB7
HDMI IN-7 CB6
HDMI IN-6 CB8
CB5
HDMI IN-5 CB4
HDMI IN-4 CB3
HDMI IN-3 CB2
HDMI IN-2 CB1
HDMI IN-1
52793-2270 WD29580
DC1R019JAXR190 WW27170 DC1R019JAXR190 WW27170 DC1R019JAXR190 WW27170 DC1R019JAXR190 WW27170 DC1R019JAXR190 WW27170 DC1R019JAXR190 WW27170 DC1R019JAXR190 WW27170
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
5
4
3
2
1
24
DGND
Data2+
Data2-
E X C 2 4 C H 5 0 0 US h i e l d 2
4 Data1+
Data1-
E X C 2 4 C H 5 0 0 US h i e l d 1
4 Data0+
Data0-
4 DataC+
CEC
E X C 2 4 C H 5 0 0 US h i e l d 0
DataC-
E X C 2 4 C H 5 0 0 US h i e l d C
PD
CD_SENSE
FR_N_INT
+5H
TPWR
FR_N_RST
FR_SCL
23
FR_SDA
FG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FG FG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FG FG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FG FG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FG FG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FG FG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FG FG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FG
Data2+
Shield2
Data2-
Data1+
Shield1
Data1-
Data0+
Shield0
Data0-
DataC+
ShieldC
DataC-
CEC
Reserved
SCL
SDA
GND
+5VPower
HPD
Data2+
Shield2
Data2-
Data1+
Shield1
Data1-
Data0+
Shield0
Data0-
DataC+
ShieldC
DataC-
CEC
Reserved
SCL
SDA
GND
HPD
+5VPower
Data2+
Shield2
Data2-
Data1+
Shield1
Data1-
Data0+
Shield0
Data0-
DataC+
ShieldC
DataC-
CEC
Reserved
SCL
SDA
GND
+5VPower
HPD
Data2+
Shield2
Data2-
Data1+
Shield1
Data1-
Data0+
Shield0
Data0-
DataC+
ShieldC
DataC-
CEC
Reserved
SCL
SDA
GND
+5VPower
HPD
Data2+
Shield2
Data2-
SDA
Data1+
Shield1
Data1-
Data0+
Shield0
Data0-
DataC+
ShieldC
DataC-
CEC
Reserved
SCL
GND
+5VPower
HPD
Data2+
Shield2
Data2-
Data1+
Shield1
Data1-
Data0+
Shield0
Data0-
DataC+
ShieldC
DataC-
CEC
Reserved
SCL
SDA
GND
+5VPower
HPD
Data2+
Shield2
Data2-
Data1+
Shield1
Data1-
Data0+
Shield0
Data0-
DataC+
ShieldC
DataC-
CEC
Reserved
SCL
SDA
GND
+5VPower
HPD
DGND DGND DGND DGND DGND DGND
3
DGND DGND DGND
(2125)
BKP1005HS680-T
BKP1005HS680-T
no_use
L14
L17
L18
L19
R74 0
J4112
R84
10K
J4111 J4113
0 no_use C4125
1
2
1
2
2
no_use
22
22
22
R194 22
R195 22
no_use
no_use
D4114
C4126
5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1
no_use
no_use
no_use
no_use
no_use
no_use
no_use
D11
R85
R86
R87
D19
D27
D31
D34
D37
L20
L21
D5
DGND
5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1
DGND
no_use
no_use
no_use
no_use
no_use
no_use
no_use
no_use
no_use
no_use
no_use
no_use
no_use
no_use
6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9
D10
D15
D18
D25
D26
D29
D30
D32
D33
D35
D36
D1
D4
D9
(1608)
(1608)
(1608)
(1608)
(1608)
(1608)
(1608)
DGND
R104
R139
R173
R196
R218
R27
FR_CDSNS
R167 22
R169 22
R190 22
R191 22
R214 22
R215 22
FHDMI_N_INT
R9
10
10
10
R134 22
R135 22
10
10
10
10
R22 22
R23 22
R99 22
R100 22
DV_SCL
DV_SDA
6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9 6 7 8 9
22
22
100
2
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
no_use no_use
no_use no_use
no_use no_use
no_use no_use
no_use no_use
no_use no_use
no_use no_use
+5H
R5
R6
R106
R142
R179
R198
R220
R30
no_use
R11
no_use
no_use
no_use
no_use
no_use
no_use
R111
R150
R184
R205
R224
R39
R15
R101
R137
R171
R192
R25
TP2 TP4 TP16 TP21 TP25 TP30 TP34
47K
47K
47K
47K
47K
47K
R7
0.1/10(BJ)
R107
R143
R180
R199
R221
R14 R36 R110 R147 R183 R203 R223
R31
R12
C69
no_use no_use no_use no_use no_use no_use no_use
Q2 Q4 Q6 Q8 Q10 Q15 Q20
Except
105
105
105
105
R102
R138
R172
R193
105
105
105
R26
47K
47K
47K
47K
47K
47K
TC7SET08FU
R8
R105
R141
R175
R197
R219
R28
R10
no_use
DGND DGND DGND DGND DGND DGND DGND DGND
A830
0
0
R57
1
2
IC9
R13 R35 R108 R146 R181 R201 R222
4
R4PWR5V_B
R3PWR5V_B
R0PWR5V_B
Q1 Q3 Q5 Q7 Q9 Q14 Q19
DSCL4_B
DSDA4_B
DSCL3_B
DSDA3_B
R4PWR5V
R3PWR5V
R2PWR5V
R1PWR5V
R05VPWR
HPD4_B
HPD3_B
DGND DGND DGND DGND DGND DGND DGND
DSCL4
DSDA4
DSCL3
DSDA3
DSCL2
DSDA2
DSCL1
DSDA1
DSCL0
DSDA0
HPD4
HPD3
HPD2
HPD1
HPD0
+5H
AVRL161A1R1NTB
DGND
DGND
DGND
DGND
DGND
DGND
DGND
R67 R66 R65 R64 R63 R62 R61
0.1/10(BJ)
R217
R216
no_use no_use V+ no_use no_use no_use no_use no_use
47K
47K
5
C30
D38
3 +3.3M
V- no_use
R90
10K
DGND D4112
DGND R4130
UPA672T-T1-A
3 6 0
+1.2DH
+1.2DH
no_use
no_use
R4129
D4111
BLM21PG600SN1D BLM21PG600SN1D
0.1/10(BJ) 0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ) 0.1/10(BJ)
0.1/10(BJ) 0.1/10(BJ)
0.1/10(BJ) 0.1/10(BJ)
BLM21PG600SN1D BLM21PG600SN1D
+1.2DH
+1.2DH
Q22
5 2 L22
L1
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ) 1000P(B)
0.1/10(BJ) 100P(CH)
1000P(B)
100P(CH)
1000P(B)
1000P(B)
L13 L31
3
1000P(B)
1000P(B)
100P(CH)
1000P(B)
100P(CH)
1000P(B)
10/6.3
10/6.3
C136
C148
C150
C153
C155
C157
C159
C32
C40
C42
C46
C48
C50
C51
10/6.3
10/6.3
4 1
AVDD12
AVDD12
C12
C73
C74
C75
C76
C77
C78
C81
C4
C5
C6
C7
C8
C9
R3X2P
R3X2N
R3X1P
R3X1N
R3X0P
R3X0N
R3XCP
R3XCN
VDD33
R2X2P
R2X2N
R2X1P
R2X1N
R2X0P
R2X0N
R2XCP
R2XCN
VDD12
R1X2P
R1X2N
R1X1P
R1X1N
R1X0P
R1X0N
R3X2P
R3X2N
R3X1P
R3X1N
R3X0P
R3X0N
R3XCP
R3XCN
VDD33
R2X2P
R2X2N
R2X1P
R2X1N
R2X0P
R2X0N
R2XCP
R2XCN
VDD12
R1X2P
R1X2N
R1X1P
R1X1N
R1X0P
R1X0N
DGND
DGND
DGND
DGND
+3.3H
+3.3H
BKP1005HS680-T BKP1005HS680-T +5H
1000P(B)
100P(CH)
1000P(B)
100P(CH)
1000P(B)
1000P(B)
AVDD12 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 R1XCP 9 8 7 6 5 4 3 2 L11 AVDD12 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 R1XCP 9 8 7 6 5 4 3 2 L30
10/6.3
10/6.3
C133
C145
C147
C149
C152
C154
C156
26 26
C29
C35
C38
C41
C45
C47
C49
100 100
VDD33 R1XCN VDD33 R1XCN
27 99 27 99
I2C add:0xB2
DGND
DGND
R4XCN VDD33 R4XCN VDD33
I2C add:0xB0
FHDMI_N_RST
28 98 28 98
R4XCP AVDD12 R4XCP AVDD12
29 97 100 29 97
R4131
0X4
R4X0N
R4X0P
30
31
HDMI SWITCHER 96
95
R0X2P
R0X2N
J13
J14
J15
0
0
R4X0N
R4X0P
30
31
HDMI SWITCHER 96
95
R0X2P
R0X2N
R4X1N R0X1P 0 R4X1N R0X1P
R4X1P
32 94
R0X1N YD940A0 J16 0 R4X1P
32 94
R0X1N YD940A0
33 93 33 93
R4X2N R0X0P J17 0 R4X2N R0X0P
34 92 34 92
R4X2P
VDD12
35 IC2 91
R0X0N
R0XCP
J18
J19
0
0
R4X2P
VDD12
35 IC1 91
R0X0N
R0XCP
36 90 36 90
+3.3H
R19 47K DSDA0

37 SII9589-3CTUC
89
R0XCN J20 0 DSDA0 DSDA0
37 SII9589-3CTUC
89
R0XCN
+1.2DH
+1.2DH
R20 47K DSCL0 TPVDD12 BKP1005HS680-T DSCL0 DSCL0 TPVDD12 R4132 BKP1005HS680-T
0.1/10(BJ)
R16 R115
38 88 38 88
0.1/10(BJ)
101 L8 101 0X4 L28
10/6.3
10/6.3
CBUS_HPD0 TCVDD12 HPD0 CBUS_HPD0 TCVDD12
C143
5.1K 5.1K
C138
39 87 39 87
C37
C43
C14 DGND C83 DGND
DGND
DGND
R0PWR5V_B R0PWR5V TXCN R05VPWR R0PWR5V TXCN
40 86 40 86
+3.3H
DGND
DGND
1/25 R21 47K DSDA1 TXCP 1/25 DSDA1 DSDA1 TXCP
41 85 41 85
R42 47K DSCL1 TX0N DSCL1 DSCL1 TX0N
42 84
R116
42
No replacement part available. 84
+1.2DH
+1.2DH
BKP1005HS680-T BKP1005HS680-T
4 CBUS_HPD1
No replacement part available. TX0P 5.1K HPD1 CBUS_HPD1 TX0P
0.1/10(BJ)
43 83 43 83
0.1/10(BJ)
C84
DGND
L9
DGND
R45 L29
10/6.3
10/6.3
R1PWR5V TX1N R1PWR5V R1PWR5V TX1N
C144
C139
C44
44 82 44 82
C39
5.1K DSDA3_B DSDA3 TX1P 1/25 DSDA3 DSDA3 TX1P
45 81 45 81
Except
DGND
DGND
DSCL3_B DSCL3 TX2N DSCL3 DSCL3 TX2N
J29 no_use
J30 no_use
J31 no_use
J32 no_use
J33 no_use
J34 no_use
J35 no_use
J36 no_use
R18
HPD3_B CBUS_HPD3
46 80
TX2P
5V :9mA R117 46 80 5V :9mA
5.1K 5.1K HPD3 CBUS_HPD3 TX2P
A830
C16 47 79 3.3V:260mA C85 47 79 3.3V:260mA
DGND
DGND
R3PWR5V_B R3PWR5V ARC R3PWR5V R3PWR5V ARC
1/25 DSDA4_B DSDA4
48 78
VDD12 1.2V:736mA 1/25 DSDA4 DSDA4
48 78
VDD12 1.2V:736mA
49 77 49 77
DSCL4_B DSCL4 RSVDL DSCL4 DSCL4 RSVDL
50 76 50 76
R174
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Data2+
Data2-
Data1+
Data1-
Data0+
Data0-
DataC+
DataC-
Data2+
Data2-
Data1+
Data1-
Data0+
Data0-
DataC+
DataC-
R54
0
0
DGND
LPSBV
LPSBV
CBUS_HPD4
R4PWR5V
DSDA2
DSCL2
CBUS_HPD2
R2PWR5V
DSDA5
DSCL5
R5PWR5V
SBVCC5
PWRMUX_OUT
WKUP
CD_SENSE0
CD_SENSE1
no_use CD_SENSE2
CD_SENSE3
CD_SENSE4
GPIO0
TPWR_CI2CA
RESET#
CSDA
CSCL
INT
SPDIF_IN
CBUS_HPD4
R4PWR5V
DSDA2
DSCL2
CBUS_HPD2
R2PWR5V
DSDA5
DSCL5
R5PWR5V
SBVCC5
PWRMUX_OUT
WKUP
CD_SENSE0
CD_SENSE1
CD_SENSE2
no_use CD_SENSE3
CD_SENSE4
GPIO0
TPWR_CI2CA
RESET#
CSDA
CSCL
INT
SPDIF_IN
Data2+
Data2-
Data1+
Data1-
Data0+
Data0-
DataC+
DataC-
DGND DGND
10K
R4
R187 100
22
22
R4PWR5V_B
no_use
no_use
no_use
R29 47K
R32 47K
R37 47K
R38 47K
1/25 +3.3H R148 47K

R149 47K
R4PWR5V
R2PWR5V
R186 100
4.7K
R162
R153
R154
TP6
R51
R52
R53
R165 22
R166 22
HPD4_B
R151
R170
R44
R48
5.1K
5.1K
5.1K
4.7K
R34
R40
DSDA2
DSCL2
HPD4
HPD2
R50 R164
C22 DGND C118 DGND
+3.3H
5.1K +3.3H
DGND DGND 22K DGND 22K

+3.3H
R49
+3.3H
C20 0.1/10(BJ) C112 0.1/10(BJ) R163
C24 4.7K R127 C120
R136
R145
no_use
5.1K
1/25
DGND
5.1K
C100
1/25
5.1K
C108
0.1/10(BJ) R47 0 0.1/10(BJ)
R24
C18
R33
C21 C113
DGND
10/6.3 no_use 10/6.3 R158
C23 C119 +5.5V
10/6.3
100 10/6.3
(1608)
(1608)
4.7K
R152
R41
BKP1005HS680-T
BKP1005HS680-T
0.1/10(BJ) J21 0 0.1/10(BJ)
10
10
5 DGND DGND
DGND C25
10/6.3
J22 0 DGND DGND
DGND C121
10/6.3
IC414
D4113
L24
no_use no_use
L2
5.1K
J23 0
R43
R155
no_use
5.1K
DGND DGND OUT IN VOUT VDD
J24 0 +3.3M
6
ILIM GND GND GND
+5H J25 0 +5H
5
no_use
C4123
R160
+3.3H /FLAG EN CE NC
10K
no_use
C4124
J26 0 +3.3H
4
R4126
Q4111 Q4112 IC416
no_use
R4123 R4124
R4139
no_use
J27 0 no_use
Q21 no_use no_use
J28 0 UPA672T-T1-A R4125
no_use
no_use
no_use
R4121
D4115
C4121
3 6 no_use
5 2
no_use +5H
no_use
R4122
4 1 DGND
DGND
no_use
V+
no_use
IC415
C4122
4
5
no_use
R4128
3
2
1
+5H V-
R4127
DGND no_use
DGND
Q4113
100
MHL_PRT
+5.5V
no_use
100
+1.8H
6 D4103 BLM21PG600SN1D
0.01/16(B)
0.1/10(BJ)
0.1/10(BJ)
0.01/16(B)
R4115 DGND
1000P(B)
no_use L16
RB521S-30TE61
10/6.3
10/6.3
IC411: NCP380HMUAJAATBG
C130
C54
C56
C58
C60
C62
C66
A NCP380HMUAJAATB
IC411 R1171S501B-E2-F
Fixed / Adjustable current-limiting
DGND
IC413
BLM21PG600SN1D OUT IN 5.0 VOUT VDD
YE997A0
YF097A0
3 2 1
4 5 6
4 5 6
L4101
power-distribution switches
R4118
ILIM GND GND GND

+3.3H
BKP1005HS680-T
0.1/10(BJ)
0.01/16(B)
0.1/10(BJ)
0.01/16(B)
0.1/10(BJ)
R4114 C4110
10/10
to DIGITAL 4/8
RB051L-40
C4111
10/10
10
1000P(B)
/FLAG EN CE NC DGND DGND DGND
RXB_2+
RXB_2-
RXB_1+
RXB_1-
RXB_0+
RXB_0-
RXB_C+
RXB_C-
RXA_2+
RXA_2-
RXA_1+
RXA_1-
RXA_0+
RXA_0-
RXA_C+
RXA_C-
L15
D4105
no_use
3
10/6.3
no_use
CVDD
C53
C55
C57
C59
C61
C63
C65
CVDD
TVDD
TVDD
TVDD
CVDD
DVDD
CVDD
TVDD
TVDD
TVDD
R207
R4111
R4108 R4109
GND
GND
GND
C4112
+3.3H CEC
22K
NC
NC
to 004.sht Blocking control
1/25
18K 2.7K +5.5V

DGND
CB411 R4110 RT_MCLK,RT_SCK/DCLK,RT_WS/D2B,RT_SD0/D0B,RT_SD1/D1A,RT_SD2/D1B,RT_SD3/D2A,RT_SPDIF/D0A

( 0 . 5 % )( 0 . 5 % ) +1.2DH NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NC (HDMI Tx)
R240
C4102 no_use
10/10 BLM21PG600SN1D
DGND (0.5%) 33 128
10K
1.2 IN 6 1 OUT
DVDD NC
MHLVB
BLM21PG600SN1D
BLM21PG600SN1D
Q4101 Q4104 34 127

+5H
L39
R126
no_use
A1576UBTLR DGND
HRX_D[47] A47
35 ALSB:L 126
RXA_5V 0
0.1/10(BJ)
XHI
TC7SET08FU
HRX_D[46] R77 A46 HPA_A R239 0

0.1/10(BJ)
LB91802 3.3A
I2C add:0x98
no_use
R4101
D4104
C4104
36 125
220K
V+
L5
L4
IC412
no_use
C4109
R4116
R4117
HRX_D[45] 33X4 A45 DDCA_SDA

4
5 37 124 ILIM 2 Current

Gate Driver
DGND
0
HDMI RECEIVER
3 HRX_D[44] A44 DDCA_SCL R129 +3.3H Limiter
2
1
3900P(B)
C11
22 0.1/10(BJ)
DTC044EUBTL V- 38 123
10K
R4105
L 3 8 369kHz 1 0 0 0 P ( B ) A43 RXB_5V

C27
C28
R4112
100K
Page 116 M2 DGND MHLVB_PON 39 122
R188
1000P(B)
10K 10UH HRX_D[43] DVDDIO HPA_B
22K
no_use
(0.5%) C2 (0.5%)
DGND
C17
no_use
FR_CDSNS 40
YD893A0 121
7.5K
Vref
R1
HRX_D[42] R78 A42 DDCB_SDA

C1
UVLO
C10
+3.3H Osc
C3
to DIGITAL (2)_W4202 41 120 TSD

R4113
Q4107
(0.5%)
22/6.3
DGND
R133
R4102
HRX_D[41] 33X4 A41 DDCB_SCL GND 5

47K
BST R94
5.1K
42 119 DV_SCL DV_SCL

DGND HRX_D[40] A40
IC3 CEC 10K Flag
no_use
3 /FLAG
(0.5%)
+5H C93 DV_SDA DV_SDA
DGND
43 118 R130 28.63636MHZ
220K
GND
VIN
R17
R3
0.1/10(BJ)
22K
HRX_D[39] A39 DVDD

R2
SW
R204
R206
no_use
(0.5%)
+3.3H FHDMI_N_RST FHDMI_N_RST
R118
44 117 150
22K
22K
2
1
1000P(B)
10P(CH)
ADV7619KSVZ
DGND
Control logic
4.7/6.3
DGND DGND 4 3 2 1 HRX_D[38] R79 A38 XTALN EN block
7 DTC044EUBTL IC4 BD9329AEFJ 45 116 FHDMI_N_INT FHDMI_N_INT EN 4
and timer
3
4
C94
+1.8HRPLL
C102
C105
C106
G YD184B0 HRX_D[37] 33X4 A37 XTALP
5 6 7 8 46 115 HSW1_N_INT
DGND
HRX_D[36] A36 PVDD
XL1
10P(CH) L23 to DIGITAL 5/8
FB
R92 COMMP
EN
SS
R211
R213
3A
2.2K
2.2K
DGND 47 114 HSW2_N_INT
0.1/10(BJ)
DGND
DGND
HRX_D[35] A35 CS 10K BKP1005HS680-T
48 113 HAU_INT
C26
R178
to 005.sht
(0.5%)
+1.8D HRX_D[34] R80 A34 RESETB R140

0.01/16(B) 2.2K
49 112 HRTX_N_RST
R120 0 0
HRX_D[33] 33X4 A33
50 111
INT
HRX_N_INT (u-Com) IC413: R1171S501B-E2-FE
HRX_D[32] A32 SCL R121 22
51 110 HDMI_SCL
(2125)
No replacement part available. DGND DVDDIO SDA R122 22 470P(B)
HDMI_SDA
CMOS-based LDO regulator IC
C13
52 109
J4102
no_use
no_use
DVDD DVDD R176
C164
C165
53 108 C101 R144 HSW_N_RST
DGND no_use
0 6 5 4 HRX_D[31] A31 MCLK R123 100 MCLK RT_MCLK
no_use
HDMI_PON
R4103 C4105
54 107 10K
Q4105 HRX_D[30] R81 A30 AP5 R124 100 LRCLK_DSD2B RT_WS/D2B
no_use
R200
D4101
DGND MHLVB_PON MHLVB_PON

55 106
VDD 6 1 VOUT
10K
3 2
HRX_D[29] 33X4 A29 SCLK R125 100 SCLK RT_SCK/DCLK R182 R212
0.01/16(B)
56 105 MHL_PRT MHL_VBUS_PRT

no_use
12K 100
C4107
R4106
+1.8H HRX_D[28] A28 AP4 SD3_DSD2A RT_SD3/D2A DGND

100K
R208
R210
1 2 3 +1.8D 57 104
+3.3D R131
22K
22K
CB412 0.1/10(BJ) (2125) +3.3H HRX_D[27] A27 AP3 SD2_DSD1B RT_SD2/D1B DGND
Q4102 1.8
DGND
DGND C4101 58 103

DGND RAL035P01 J3 HRX_D[26] R82 A26 AP2 100X4 SD1_DSD1A RT_SD1/D1A
3.3
+ 1 . 8 H L 1.8 1 DTA044EUBTL 59 102 +3.3H +1.2DH +1.8H +5H
no_use HRX_D[25] 33X4 A25 AP1 SD0_DSD0B RT_SD0/D0B
+ 3 . 3 H L 3.3
HRX_D[24] A24
60 101
AP0 R119 SPDIF_DSD0A RT_SPDIF/D0A DGND +3.3H Vref
5 GND
XHI
C4103
0.1/10(BJ)
DGND
HRX_CLK R83 LLC
61 3.3V:101mA 100
NC
100 R177
C15 C68 C86 C90
VL84470
6 5 4 6 5 4 10
62
1.8V:475mA 99 no_use no_use no_use no_use no_use
1000P(B)
1000P(B)
DVDD C31 C70 C87 C91

+Vf +3.3D
63 98
NC DGND Current Limit
C128
R202 C160
Q12 Q18 +3.3H

DVDD
3 2 3 2 64 97
NC no_use no_use no_use no_use
C92
Thermal Shutdown
no_use
C33 C71 C88
no_use
0.01/16(B)
0.01/16(B)
J4101
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
CE 3 2 GND
R113
no_use
Page 116 J8
R185
C162
C142
R189
R209
no_use no_use no_use no_use

680
8
DVDDIO
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
DVDDIO
A12
DVDD
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DVDDIO
DE
HS
VS/ALSB
NC
100K
100K
1 2 3 1 2 3
(2125) C34 C72 C89 C97
J4103 Q11 Q17
to DIGITAL (2)_W4201 RAL035P01 RAL035P01 BKP1005HS680-T no_use no_use no_use no_use
+3.3H
L25
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0 6 5 4 C36 C79 C98
no_use
1 DTA044EUBTL 1 DTA044EUBTL
R4104 C4106
1000P(B)
1000P(B)
R114
22/6.3
1.8K
Q4106
no_use
no_use no_use no_use

D4102
C104
C107
C110
C114
C116
C123
DGND Pin No. Symbol Description
33X4
33X4
33X4
33X4
33X4
R103
33X4
R109
33X4
C95
C99
3 2 C52 C80 C103
R93
R95
R97
R91
R98
no_use
no_use
no_use
no_use
no_use
no_use
no_use
no_use
DGND DGND
0.01/16(B)
TP40
TP41
TP42
TP43
TP44
TP45
TP46
TP47
1 VOUT Output Pin
no_use
DGND
no_use no_use no_use
C4108
R4107
100K
1 2 3 DGND C64 C82

Q4103
2, 5 GND Ground Pin
no_use no_use
+1.8H
RAL035P01 +3.3H +1.8HRPLL BLM21PG600SN1D
0.01/16(B)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
DGND +5.5V +5H C67 DGND DGND DGND DGND DGND DGND DGND DGND DGND 3 CE Chip Enable Pin ("H" Active)
100P(CH)
1000P(B)
1000P(B)
1 DTA044EUBTL L27
10/6.3
1.8 5.0 no_use 4 NC No Connection
10/6.3
C111
C115
C117
C122
C124
C109
C125
C126
C131
C127
C96
DGND
HRX_D[13]
HRX_D[12]
HRX_D[23]
HRX_D[22]
HRX_D[21]
HRX_D[20]
HRX_D[19]
HRX_D[18]
HRX_D[17]
HRX_D[16]
HRX_D[15]
HRX_D[14]
HRX_D[11]
HRX_D[10]
RESISTOR DGND
HRX_D[9]
HRX_D[8]
HRX_D[7]
HRX_D[6]
HRX_D[5]
HRX_D[4]
HRX_D[3]
HRX_D[2]
HRX_D[1]
HRX_D[0]
6 VDD Input Pin
DGND
DGND
IC1, 2: SII9589-3CTUC
HRX_DE
HRX_HS
HRX_VS
REMARKS PARTS NAME RP130Q181D-TR-F RP130Q501D-TR-F to DIGITAL 3/8

VOUT
VOUT
NO MARK CARBON FILM RESISTOR (P=5)

to 003.sht HDMI port processors
VDD
VDD
HRX_CLK,HRX_D[0-47],HRX_DE,HRX_HS,HRX_VS
CARBON FILM RESISTOR (P=10)
(FPGA)
10/6.3
10/6.3
10/10
10/10
4 3 4 3
C129
C137
C163
C161
METAL OXIDE FILM RESISTOR IC6 IC8 Tie one CD_SENCE line
to MHL CD_SENCE, the rest to ground
METAL FILM RESISTOR 1 2 1 2
CE/CE
GND
CE/CE
GND
METAL PLATE RESISTOR CD_SENSE0-4 Always-On Section
FIRE PROOF CARBON FILM RESISTOR

NOTICE (model)
64-68 5
J JAPAN
CEMENT
SEMI
MOLDED RESISTOR
VARIABLE RESISTOR
U U.S.A DGND DGND DIGITAL (1) Sheet1:HDMI Rx CBUS_HPD0-4
39,43,47,51,55 5
MHL Control
C CANADA
CHIP RESISTOR
R GENERAL IC/CB/XL:1-19,40-44,411-419 Serial Ports
T CHINA OHTER :1-249,400-449,4101-4199
9 CAPACITOR K KOREA DDC
DDC0
DDC1
DDC2 NVRAM Booting Sequencer
REMARKS PARTS NAME A AUSTRALIA EDID SRAM
DDC3
NO MARK ELECTROLYTIC CAPACITOR B BRITISH DDC4
TANTALUM CAPACITOR G EUROPE IC3: ADV7619KSVZ DDC5
NO MARK CERAMIC CAPACITOR L SINGAPORE IC4: BD9329AEFJ-E2 INT
CERAMIC TUBULAR CAPACITOR E SOUTH EUROPE Dual port, Xpressview, 3 GHz HDMI receiver HDCP Configuration Status,
V TAIWAN
1ch step-down DC/DC converter I2C
Local Registers
OTP and Interrupt-Control
Registers
74
POLYESTER FILM CAPACITOR I2C
F RUSSIAN IC6: RP130Q181D-TR-F IC8: RP130Q501D-TR-F IC9, 412: TC7SET08FU
VIDEO OUTPUT FORMATTER
POLYSTYRENE FILM CAPACITOR 115

XTALP 80-91
P LATIN AMERICA DPLL 300MHz VIDEO PATH P0 TO P11
P
MICA CAPACITOR
S BRAZIL
XTALN 116 66-76,78
P12 TO P23
VCC Voltage regulator Voltage regulator 2 input AND gate
POLYPROPYLENE FILM CAPACITOR 48-51,54-61
H THAI SCL 110 P24 TO P35 OPEN EN 5V
SEMICONDUCTIVE CERAMIC CAPACITOR 35-39,41-47 Power-Down Section
SDA 109 CONTROL P36 TO P47 7 VREF OSC VREG
POLYPHENYLENE SULFIDE FILM SHUTDOWN BST R0X
S CS 113
INTERFACE 62 LLC IN B 1 5 VCC TMDS Rx
A
CAPACITOR I2C 1 89-96 (Port 0)
CEC 118
CEC
CONTROLLER
BACK-END 94 HS VDD 4 3 VOUT VDD 4 3 VOUT C
COLOR 95 VS/FIELD/ALSB OCP 12V
RXA_5V 126 SPACE IN A 2 R1X
DPLL
93 DE VIN TMDS Rx
5V DETECT CONTROL AND DATA CONVERSION Packet
RXB_5V 122
UVLO 1-6,99,100 (Port 1)
AND HDP 2 Analyzer
HPA_A/INT2* 125
CONTROLLER IBIAS HDCP Repeater
HPA_B 121
INTERRUPT 111
TSD GND 3 4 OUT Y MHL
Authentication SHA
INT1 R2X Demux
DDCA_SDA 124 CONTROLLER TMDS Rx Packet
EDID HDMI INT2* S LVS Analyzer
DDCA_SCL 123 (INT1, INT2) FB 9-16 (Port 2)
REPEATER PROCESSOR ERR
DDCB_SDA 120 HDCP COMPONENT 5 DRV SW OUTPUT
CONTROLLER
KEYS Vref Vref A B Y
PROCESSOR 3
10 DDCB_SCL 119
AUDIO OUTPUT FORMATTER
R3X B
101 AP1/I2S_TDM LOGIC Current Limit L L L
DATA A COMP SLOPE Current Limit TMDS Rx
PREPROCESSOR B 102 AP2 PWM 18-25 (Port 3) D
CE 1 2 GND
FAST SWITCHING
R
RXA_C±
3,4
HDCP AND COLOR C 103 AP3 6
LVS CE 1 2 GND L H L DPLL
HDMI Data Path AV TMDS
TX
PLLs
Xpressview
20,21
RXB_C± ENGINE SPACE 104 AP4 H L L and HDCP Unmask
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter. SS R4X Mute Tx 79-86
CONVERSION TMDS Rx
PACKET/ 106 AP5 8 Soft Start H H H (Port 4)
6,7 28-35 MHL
★ Components having special characteristics are marked
RXA_0±
and must be replaced RXA_1±
9,10
EQUALIZER SAMPLER
INFOFRAME
MEMORY MUTE
105 SCLK/INT2* Demux
12,13 PACKET Pin No. Symbol Description Pin No. Symbol Description
with parts having specifications equal to those originally installed. RXA_2±
PROCESSOR
AUDIO
107 MCLK/INT2*
1 CE Chip Enable ("H" Active)
23,24 100 AP0 1 CE Chip Enable ("H" Active)
★ Schematic diagram is subject to change without notice. 4
RXB_0± ARC
26,27 PROCESSOR ARC SPDIF
RXB_1± EQUALIZER SAMPLER GND 2 GND Ground Pin 2 GND Ground Pin 78
29,30 75
RXB_2± Connect to
3 VOUT Output Pin 3 VOUT Output Pin any one
input port Note: MHL input can be assigned to any port during design
4 VDD Input Pin 4 VDD Input Pin but is hardwired and cannot be selected using firmware.
* INT2 can be made available on one of these pins: HPA_A/INT2, MCLK/INT2, OR SCLK/INT2.
115
RX-A830
DIGITAL 2/8
1
VIDEO AUX
HDMI/
MHL
DIGITAL (1) CB421
HDMI V-AUX DIGITAL(2) FrontHDMI
DC1R019JAXR190 WW27170
AVRL161A1R1NTB
DIGITAL (2)
10
11
12
13
14
15
16
17
18
19
0.1/10(BJ)
to DIGITAL 5/8
0.1/10(BJ)
DV_SCL
1
2
3
4
5
6
7
8
9
DV_SCL FG FG
1000P(B)
no_use
C4216
D4202
C4215
to 005.sht
C4245
C4225
DV_SDA ST421
Reserved
SCL
SDA
GND
+5VPower
HPD
Sheild2
Sheild1
Sheild0
SheildC
Data1+
Data0+
DataC+
DataC-
Data2+
Data2-
Data1-
Data0-
CEC
DV_SDA
(u-com) to 005.sht FG FG
HDMI_PON
HDMI_PON (u-Com)
BLM21PG600SN1D W4202
VDEC_N_RST MHLVBF
VDEC_N_RST to DIGITAL 5/8 L4213
Page 115 A6
TP4215
TP4216
FG MHLVBF_GND
ADCVBS
R4232
ADPb
ADPr
DGND SCN-XH
ADY
2 MB20245
0
R4204
AVRL161A1R1NTB
0
0.047/10(BJ)
RCLAMP0584J
ADCVBS
5 4 3 2 1
C4217
D4201
ADPb
ADPr
+1.8DPLL
D4205
+3.3H
ADY
1.8
RP130Q181D-TR-F 6 7 8 9
YC287A0 +1.2HF
DGND
no_use
DGND
R281
VOUT GND
+1.8H
BKP1005HS680-T
3
2
DGND
IC27
C4206 R4228 47K
1/6.3
C271
CE/CE
L4202
VDD R280 1000P(B) R4225 47K +1.2HF +3.3HF
1
+3.3V +3.3H 1K DGND DGND
1SS400TE61
C4207
no_use
1/6.3
C279
C280
BKP1005HS680-T
BKP1005HS680-T
R276 HDMI_PON
105
10/6.3 D4204 C4226 C4235
no_use
C4208 R4227
0.1/10(BJ)
0.1/10(BJ)
L4204
L4208
1000P(B) 1000P(B)
no_use
1SS400TE61
C252
C253
DGND 0.1/10(BJ)
R4224
R4231
R4237
R260
R272
R278
R274
D4203
4.7K
C4209 C4227 C4236
10K
47K
1K
1M
22
0
DGND
A1576UBTLR
0.1/10(BJ) 10/6.3 22/6.3
C4210 C4228 C4237
R4230
R4235
C4081UBTLR
C4081UBTLR
DGND DGND
22
10
3 Q250 Q251
Q252
R279
0.1/10(BJ)
C4211
+5HF
0.1/10(BJ)
C4229
0.1/10(BJ)
C4238
C250
R4216
5.1X4
R4219
5.1X4
220 1000P(B) 0.1/10(BJ) 0.1/10(BJ)
Q253
C4081UBTLR
10/10 C4212 C4230 C4239
1/25 R282
100P(CH) 0.1/10(BJ) 1000P(B)
C251 100
C4231 C4240
R268
R269
R273
R275
R277
2.2K
220K
2.2K
DSCL3_F
10K
470
DSDA3_F 1000P(B) 100P(CH)

C4232
VDEC_C[0]
VDEC_C[1]
VDEC_C[2]
VDEC_C[3]
VDEC_CLK
R3PWR5V_F
CBUS3_F 100P(CH)
DGND
no_use
R263 R266
AVDD12
AVDD12
+1.8H +3.3H
R4XCP
R4XCN
VDD33
R3X2P
R3X2N
R3X1P
R3X1N
R3X0P
R3X0N
R3XCP
R3XCN
VDD12
R1X2P
R1X2N
R1X1P
R1X1N
R1X0P
R1X0N
R1XCP
R1XCN
+1.8DPLL no_use
BKP1005HS680-T
10/6.3 BKP1005HS680-T
R302 no_use
no_use
no_use R304
R299
10P(CH)
10P(CH)
C299
C300
L254
L253
R4X0N 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VDD33
23 88
0.1/10(BJ)
no_use
0.01/16(B)
R306
R4X0P AVDD12
28.63636MHZ
1K 0.082/16
XL21 24
I2C add:0xB0 87
C294
1 4 R4X1N R0X2P
TP283 TP284 25 86 +1.2HF +1.2HF
+1.8H
HDMI EQUALIZER
R313
+3.3HF R4X1P R0X2N
4
BKP1005HS680-T
2 3
BKP1005HS680-T
47
BKP1005HS680-T
26 85
(0.5%) (0.5%)
R267
10/6.3
R290
R4X2N R0X1P
150
C304
C301
27
YE996A0 84
L4205
L4209
C297
R311 R4X2P R0X1N
L255
+3.3H VDEC_CLK,VDEC_Y[0-9],VDEC_C[0-9],VDEC_DE,VDEC_HS,VDEC_VS DGND

to 003.sht
C295
28 83 DGND
VDD12 R0X0P
R291
1M
(FPGA) 29 82
680
C4233 C4241
(0.5%) DSDA0
IC423 R0X0N
R4209
47KX4
C288 30 81
L251 TP266 10/6.3 10/6.3
to DIGITAL 3/8 DSCL0 R0XCP
C4234 C4242
31 80
no_use 0.01/16(B) CBUS_HPD0
SII9587CNUC-3 R0XCN
10/6.3
R314 32 79 0.1/10(BJ) 0.1/10(BJ)

C255
C289
DGND
R4201 R0PWR5V TPVDD12
R318
4.7K no_use 33 89 78
XTAL TP280
XTAL1 TP281
TP282
0.1/10(BJ) VDEC_C[4] 5.1K DSDA1 TCVDD12

34 77
VDEC_C[5] DSCL1 DGND TXCN
PWRDWN
35 76
VDEC_C[6] CBUS_HPD1 TXCP
AGND
PVDD
ELPF
DGND
DVDD
LLC
36 75
J251
DGND
NC
NC
P0
P1
P2
P3
P4
VDEC_C[7] R4202 R1PWR5V TX0N

0
37 74
5.1K
32
31
30
29
8
27
26
25
24
3
22
21
20
19
18
17
DSDA3 TX0P
NC P5
2
R319 38 73
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
no_use DSCL3 TX1N

TEST_0 P6 VDEC_C[8] R4203 39 72
R254
C281 I2C add:0x42 5.1K CBUS_HPD3 TX1P
ADCVBS AIN1 P7 VDEC_C[9]
C4203
40
5V :10mA 71
VIDEO DECODER
DGND
36 R250 R3PWR5V TX2N
0.1/10(BJ) AIN2 GPO0 VDEC_Y[0]
R270
41 70
+3.3HF
1/25 R4210 47K DSDA4 3.3V:220mA TX2P
39
5 10K AGND
X8841A0
GPO1 VDEC_Y[1]
R4211 47K DSCL4
42
1.2V:548mA
69
ARC
0.1/10(BJ)
C257 C302 R261

VREFP DVDDIO 43 68
1K R262 CBUS_HPD4 VDD12
0.1/10(BJ) VREFN DGND 0.1/10(BJ)
no_use
no_use
44 67
C277
IC21
C267
C282
C286 R252 1K 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
AVDD SFL R320
RSVDL
R4PWR5V
DSDA5
DSCL5
R5PWR5V
SBVCC5
PWRMUX_OUT
LPSBV
RSVD
CD_SENSE0
GPIO0
GPIO1
INT
CD_SENSE1
RSVD
CD_SENSE3
CD_SENSE4
TPWR_CI2CA
RESET#
CSDA
CSCL
SPDIF_IN
C258 no_use 47X4
DGND
0.1/10(BJ) NC P8 VDEC_Y[2] R4238
0.1/10(BJ)
ADV7180BSTZ 0
no_use
no_use
no_use
NC P9 VDEC_Y[3]
R4236
C268
C283
C278
AGND P10 VDEC_Y[4] 10K
+3.3HF
C259
NC P11 VDEC_Y[5]
R4213 47K
R4214 47K
R4233
R4212
R4215
no_use C303
5.1K
5.1K
NC DVDDIO no_use
R4220
0X4
no_use R251 AIN3 DGND 0.1/10(BJ)
DGND
C263 R4234
3.3V : 204mA
10K AIN4 HS VDEC_HS
C264 no_use 1.8V : 116mA C4221 4.7K
AIN5 INTRQ R315 VDEC_VS DGND DGND
0.1/10(BJ)
C269 no_use no_use
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C4222
VDEC_DE +3.3HF
C4218
R4221
AIN6
NC
RESET
ALSB
SDATA
SCLK
GPO3
GPO2
DGND
DVDD
P19
P18
P17
P16
FLD_DE_OUT
VS_OUT
C265 no_use R321 10/6.3

47X4 0.1/10(BJ) C4223 10K
C270 no_use C4219
1000P(B)
0.1/10(BJ)
C4246
L4203 R4217
10/6.3
C4224
ADV7181
BKP1005HS680-T
6
10
R255 C261 DGND 4.7/6.3
ADPb
no_use
no_use
R4218
R292
R296
R305
4.7K
5.1K
ADPr 36 R259 0.1/10(BJ) C273
DGND DGND
R4222
ADY R256 36 C262
0.1/10(BJ)
no_use
0.1/10(BJ)
no_use
R4223
R4229
36 C275
0.1/10(BJ)
4.7K
no_use
R264
R265
R271
R307
+5HF +3.3HF
C298
C291
39
39
39
no_use
+1.2HF 2 R4226
DGND
470P(B) 4
+3.3H R286 +5HF 1 100
1.2
IC424
10K TC7SET08FU
R303 33
R300 33
R310 R1172H121D-T1-F
0.1/10(BJ)
47X4 IC421 V+
0.1/10(BJ)
R308
DGND
C4220
R309
VOUT
4.7K
4.7K
VDD
C4204
3
VDEC_Y[9]
VDEC_Y[8]
VDEC_Y[7]
VDEC_Y[6]
10/6.3
C4201
5 4 V-
X9292A0
VDEC_N_RST
10/6.3
C4213
1 2 3
no_use
no_use
D251
D252
DGND
CEorCE
GND
NC
IC/CB/XL:20-29
DV_SDA
DV_SCL
OHTER :250-349
100
R4242
R4240
DGND
7
J4201
DGND
10
10
0
R4239
R4241
R4243
+3.3HF
10
10
10
IC21: ADV7180BSTZ
10-bit, 4 x oversampling SDTV video decoder BLM21PG600SN1D
0.1/10(BJ)
L4201 +5HF
VOUT
DIGITAL(3) RS-232C
VDD
C4205
BKP1005HS680-T
10/6.3
C4202
CLOCK PROCESSING BLOCK 5 4
XTAL1
DGND
IC422
DIGITAL (3) no_use
no_use
LLC
C4214
L4212
1 2 3
XTAL PLL ADLLTPROCESSING RS-232C
CE
GND
NC
ZE79170
EXC24CH500U
EXC24CH500U
EXC24CH500U
EXC24CH500U
4
3
4
3
4
3
A02+0911-2080 CB33
16-BIT
L4207
L4206
L4210
L4211
0.1/10(BJ)
PIXELDATA 11 5 4 3 2 1 10
10-BIT,86MHz DIGITAL
DGND
FIFO
PROCESSING
0.1/10(BJ)
9 8 7 6 C4243
E
ADC P15TOP0 R4205

AIN1 BLOCK
RI
GND
DTR
CTS
TXD
RTS
RXD
RSR
DCD
AA no_use
1
2
1
2
1
2
DGND
C379
DGND
FILTER
MUX BLOCK
AIN2 2DCOMB
OUTPUT BLOCK
HS
CD_SENSE
FR_N_INT
FR_N_RST
ANALOG
Sheild0
SheildC
Sheild2
Sheild1
AIN3 AA
8
Sheild
Data2+
Data2-
Data1+
Data1-
Data0+
DataC+
DataC-
Data0-
FR_SCL
FR_SDA
R396
R398
VIDEO PN351
+3.3HL
+1.8HL
SHA A/D VS
2.2
2.2
FILTER VBISLICER
TPWR
INPUTS AIN4
DGND
+5H
CEC
FIELD
PD
AIN5 AA
FILTER COLOR GPO0TO GPO3 (#18 L=70:WS48830)
AIN6 DEMOD +3.3M W4201 CB422
SFL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SCN-XH 52610-2271
R397
0.1/10(BJ)
MB20340 VY93990
22K
R394
to DIGITAL(1)
C377
REFERENCE I2C/CONTROL
INTRQ 22K Page 115 A8
to DIGITAL(1)
FORCEOFF
+3.3M
CD_SENSE0,1,3,4 IC423: SII9587CNUC-3 001.sht
Tie one CD_SENSE line
to MHL CD_SENSE, the HDMI port processor (HDMI Rx)
VCC
GND
005.sht
(u-Com)
rest to ground
R399 C385 DGND
SCLK SDATA ALSB RESET PWRDWN 16 15 14 13 12 11 10 9
IC32 TRS3221ECPWR
100K 10/10 232C_MOSI Always-On Section Page 115 F1
1 2 3 4 5 6 7 8 232C_MISO Page 119 D9
CBUS_HPD0,1,3,4 to DIGITAL (1)_CB8
EN
C1+
V+
+3.3M MHL Control

to DIGITAL (1)_CB75 4
0.1/10(BJ)
0.1/10(BJ)
0.1/10(BJ)
IC27: RP130Q181D-TR-F
R395
0.1/10(BJ) C376
C378
C380
C382
W31
22K
Voltage regulator MF40407

Serial Ports
DDC 0
DDC DDC 1
9 VDD 4 3 VOUT
DDC 3 EDID SRAM
NVRAM Booting Sequencer
DIGITAL(2) DIGITAL(3)
IC32: TRS3221ECPWR DDC 4
DGND DDC 5 IC/CB/XL:421-429 IC/CB/XL:30-39
3 V to 5.5 V single channel RS-232 line driver/receiver
with ±15 kV IEC ESD protection Configuration, INT OHTER :4201-4299 OHTER :350-399
HDCP Status, and
I2C OTP
Local Registers Interrupt Control
I2C Registers
Sheet2:VDec/FHDMI/232C
Vref EN 1 16 FORCEOFF DIN
11 13
DOUT
C1+ 15 IC421: R1172H121D-T1-F
Current Limit 2 VCC Power-Down Section
CE 1 2 GND CMOS-based positive-voltage regulator IC R0X
V+ 3 14 GND FORCEOFF
16 TMDS Rx
A
(Port 0)
C1- 4 10
13 DOUT Auto-Powerdown INVALID C
12 R1X DPLL
C2+ 5 12 FORCEON FORCEON VDD 4 5 VOUT TMDS Rx
Packet
Pin No. Symbol Description (Port 1)
NOTICE (model) Analyzer
1 CE Chip Enable ("H" Active) C2- 6 11 DIN J JAPAN MHL HDCP Repeater
9 8 Demux Authentication SHA
2 GND Ground Pin V- 7 10 INVALID ROUT RIN RESISTOR CAPACITOR
U U.S.A Packet
3 VOUT Output Pin 1
C CANADA Analyzer IC424: TC7SET08FU
RIN 8 9 ROUT EN REMARKS PARTS NAME REMARKS PARTS NAME
R GENERAL
4 VDD Input Pin NO MARK CARBON FILM RESISTOR (P=5) NO MARK ELECTROLYTIC CAPACITOR
T CHINA
Vref 2 input AND gate
R3X B
10 CARBON FILM
METAL OXIDE
RESISTOR (P=10)
FILM RESISTOR NO MARK
TANTALUM
CERAMIC
CAPACITOR
CAPACITOR
K KOREA
CE 1
Current Limit
2 GND
TMDS Rx
(Port 3) D
METAL FILM RESISTOR CERAMIC TUBULAR CAPACITOR
A AUSTRALIA DPLL TX IN B 1 5 VCC A B Y
B BRITISH HDMI Data Path AV TMDS
METAL PLATE RESISTOR POLYESTER FILM CAPACITOR R4X and HDCP Unmask Mute Tx L L L
G EUROPE TMDS Rx
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter. FIRE PROOF CARBON FILM RESISTOR POLYSTYRENE FILM CAPACITOR
L SINGAPORE Pin No. Symbol Description (Port 4) MHL IN A 2 L H L
CEMENT MOLDED RESISTOR MICA CAPACITOR
★ Components having special characteristics are marked and must be replaced SEMI VARIABLE RESISTOR P POLYPROPYLENE FILM CAPACITOR
E SOUTH EUROPE
1 CE Chip Enable Pin
Demux H L L
V TAIWAN H H H
with parts having specifications equal to those originally installed. CHIP RESISTOR SEMICONDUCTIVE CERAMIC CAPACITOR 2 GND Ground Pin GND 3 4 OUT Y
F RUSSIAN ARC
★ Schematic diagram is subject to change without notice. S
POLYPHENYLENE
CAPACITOR
SULFIDE FILM
P LATIN AMERICA 3 NC No Connection Connect to
ARC SPDIF
S BRAZIL any one input
4 VDD Input Pin port
H THAI
5 VOUT Output Pin of Voltage Regulator Note: MHL input can be assigned to any port during design
but is hardwired and cannot be selected using firmware.
116
RX-A830
DIGITAL 3/8
1
to 001.sht HRX_CLK,HRX_D[0-47],HRX_DE,HRX_HS,HRX_VS
(HDMI Rx)
HRX_CLK
to DIGITAL 1/8
VDEC_CLK,VDEC_Y[9-0],VDEC_C[9-0],VDEC_DE,VDEC_HS,VDEC_VS
to 002.sht
(VDec) HTX1_CLK,HTX1_D[0-35],HTX1_DE,HTX1_HS,HTX1_VS
to DIGITAL 2/8 D[0-15]
to 004.sht
A[0-22] HTX2_CLK,HTX2_D[0-35],HTX2_DE,HTX2_HS,HTX2_VS
(HDMI Tx)
VDEC_CLK
to 005.sht MCBUS_N_RD
R572
to DIGITAL 4/8
O U T 1 _ D [ 3 5 ]2 2 X 4 H T X 1 _ D [ 3 5 ]
(u-Com) MCBUS_N_WR_FP B1
IO1 IO3
AA10 VDEC_HS
OUT1_D[34] HTX1_D[34]
to DIGITAL 5/8 FPGA_N_CS
B2
IO1 IO3
AA3 VDEC_C[8]
IC50 OUT1_D[33] HTX1_D[33]
C1 AA4 VDEC_C[5]
IO1 IO3 OUT1_D[32] HTX1_D[32]
2 C2
D2
IO1
EP4CE15F23C6N IO3
AA5
AA7
VDEC_C[2]
VDEC_Y[5]
R573
IO1 YD917A0 IO3 O U T 1 _ D [ 3 1 ]2 2 X 4 H T X 1 _ D [ 3 1 ]
CB51 HRX_D[26] E1 AA8 VDEC_Y[4]
no_use IO1 IO3 OUT1_D[30] HTX1_D[30]
HRX_D[24] E3 AA9 VDEC_DE
IO1 IO3 OUT1_D[29] HTX1_D[29]
+2.5FPG HRX_D[27] F1 AB10 VDEC_VS
OUT1_D[28] HTX1_D[28]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Standard HRX_D[25] F2
IO1
FPGA IO3

Yamaha Rx-A830 Full

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Yamaha Rx-A830 Full

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AV RECEIVER

RX-A830 SERVICE MANUAL

UPDATING FIRMWARE .......................................... 18–20 REMOTE CONTROL ........................................... 144–146

Copyright (c) Yamaha Corporation All rights reserved.

■ TO SERVICE PERSONNEL AC LEAKAGE

WARNING: CHEMICAL CONTENT NOTICE!

About lead free solder

■ REMOTE CONTROL PANELS

U, C, R, T, K, A, B, G, F, L, S models (8 ohms) PHONO (MM) to AV OUT (R, T, K, A, B, G, F, L, S models)

Maximum Input Signal (1 kHz) ■ Video Section

Headphone Jack Rated Output/Output Impedance Pb/Pr ...................................................................0.7 Vp-p / 75 ohms

Tuning Range Dimensions (W x H x D)

R, L, S models ......................... 87.5 to 108.0 / 87.50 to 108.00 MHz Weight

50 dB Quieting Sensitivity (IHF) (1 kHz, 100 % MOD.) Finish

Signal to Noise Ratio (IHF) U, C, R, T, K, A, B, G, F, L, S models .............................. Black color

Mono ........................................................................................71 dB B, G, F, L models ........................................................Titanium color

Stereo ......................................................................................69 dB Accessories

Harmonic Distortion (1 kHz) Remote control ..............................................................................x 1

Mono ........................................................................................ 0.3 % Batteries (R03, AAA, UM-4) ..........................................................x 2

Stereo ...................................................................................... 0.5 % FM antenna (1.4 m) ......................................................................x 1

■ AM Section Conversion plug (T model) ...........................................................x 1

DLNA™ and DLNA CERTIFIED™ are trademarks or registered trademarks

HDMI, the HDMI Logo, and High-Definition Multimedia Interface are

Android is a trademark of Google Inc.

“SILENT CINEMA” is a trademark of Yamaha Corporation.

222.5 (8-3/4") 212.5 (8-3/8")

• SET MENU TABLE

Front Presence [Use] / None

Bass Cross Over 40 / 60 / [80] / 90 / 100 / 110 / 120 / 160 / 200 Hz

PEQ Data Clear OK / CANCEL * Select “ENTER”

MAIN MENU SUB-MENU PARAMETER VALUE [INITIAL VALUE]

Initial Volume [Off] / On

DC OUT Power Mode [Continuous] / Main Zone Power Sync.

remains and a high voltage continues to exist there.

1. Removal of Top Cover

2. Removal of Front Panel Unit and Sub-Chassis Unit

Side plate (L)

Push rivet OPERATION (5) P.C.B. ①

OPERATION (2) P.C.B.

Knob ④ ⑤ Push rivet

⑫ CB79 Board-to-board connectors

Cable OPERATION (4) P.C.B.

DIGITAL (3) P.C.B.

When checking the MAIN (1) P.C.B.:

Rubber sheet and the cloth

When checking the DIGITAL (1) P.C.B.:

DIGITAL (1) P.C.B.

P.C.B. CHECKING JIG

Rubber sheet and cloth

● Confirmation of firmware version and checksum

● Initializing the back-up IC (EEPROM: IC82 on DIGITAL P.C.B.)

"MAIN ZONE " key "PURE DIRECT" key

USB storage device

Writing is started. Writing being executed.

USB UPDATE VERIFYING... Sx-x:xx%

S1: NET (IC951/IC953 on DIGITAL (1) P.C.B.) section

UPDATE SUCCESS PLEASE... POWER OFF!

List of Error Messages

Error Number Error Message Cause

0001 Microprocessor clearing error Microprocessor failure

0002 Microprocessor writing error

0004 Microprocessor checksum error Microprocessor failure / Mismatch of checksum

0008 DSP1 status port error

0010 DSP1 checksum error DSP1 failure /