B.E/B.Tech.

DEGREE PRACTICAL EXAMINATIONS'

APRTL-MAY 2013

R-2008

Fourth Semester

EIE & rCE)

.-("." -EEE,
EE2258 - Linear and Digital Integrated Circuits Lab

Time: 180 Minutes Max.Marks:100

1. Simplify using K-map and imptement using any suitable logic gates
F (A,B,C,D) : t (3,4,5,7,9,13,[4,15)

Z. (a) Design & implement 4xl Muttiptexer by using suitable logic gates & vetify its truth
table
(b) Design & construct Full adder by using suitable logic gates & verify its tmth table.

3. (a) Design & implement tx4 demultiplexer by using suitable logic gates & vetify its truth
table
(b) Design & construct Full subtractor by using suitable logic gates & verify its truth
table.

4. (a) Design a binary to gray code converter using suitable logic gates and verify their
function.
(b) Design and implement 4x2 encoder using suitable logic gates and verify its truth
table.

5. (a) Design a gray to binary code converter using suitable logic gates and verify their
function.
(b) Design and implement 2x4 decoder using suitable logic gates and verify its truth
table.
 6. Design an asynchronousiripple 4-bit binary
up counter using iK fiip flops.

v. Design an asynchronous/ripple 4-bit binary down

counter using JK flip flops.

8. Design an asynchronous/ripple 4-bit decimal (BCD)

up counter using JK flip flops.

r.-

9' Design an aslmchronous/ripple 4-bit decimal (BCD

dorvn counter using JK flip flops.

10. Design a 4 bit s;mchronous binary up counter

using JK flip flops.

' I l ' Design a 4 bit s;mchronous binary down counter

using lr< nrp nopr.

l2' Design & construct a 4 bit Seriar in seriar out shift resister.

13. Design & construci a 4 brt Serial i1 parallel out shift regisiei.

14. Design & construct a4 bit paralrer in serial out shift register.

l5- Design & construct a4bitparalrel in parallelout shift

resister.

l6- (a) Design and verify the experi ntal and theoretical loop gains of amplifiers using IC
i4i in tire invening anci non-inve
(b) Design a circuit and study th of j4L cp_amD as coffrnararor