Digital Control Methods for Current Sharing of Interleaved Synchronous

Buck Converter

Pål Andreassen, Tore M. Undeland

Norwegian University of Science and Technology
O.S. Bragstadsplass 2E
Trondheim, Norway
Tel.: +47 – 73594210
Fax: +47 – 73594279
E-Mail: pal.andreassen@elkraft.ntnu.no
URL: http://www.elkraft.ntnu.no/eno/

Keywords
«Converter control», «DSP», «ZVS converters»

Abstract
The quasi square wave operation of the synchronous buck with interleaved parallel outputs has been
successfully used in low voltage high current DC-supply for microprocessors. This topology results in fast
transient response and high power density.
In this paper, two digital control strategies for current sharing control are tested by simulation in Simulink,
and tested in the laboratory. The digital current control methods are tested using a 150 MHz Texas
Instrument TMS320F2812 DSP and studied with regard to the current reference step response.
The results from the simulations and the experiments show that it is possible to increase control
performance by using a predictive controller but that this would require extra cost and design effort to
implement a low noise and high bandwidth measurement hardware on the output voltage.

Introduction
The quasi square wave (QSW) operation of the synchronous buck converter is proven to result in fast
transient response, high power density and zero voltage switching (ZVS) [1]. This topology is a good
candidate for high current low voltage DC-supply for microprocessors. The synchronous buck in QSW
operation is operated in a so called synchronous continuous conduction mode [3]. By allowing reverse
current through bidirectional switches, the power may flow in both directions. Because of this, the ZVS-
QSW converter could be used in topologies where bidirectional power flow is needed [2].

The disadvantages of the quasi square wave operation are high transistor peak current and high
input/output current ripple, to achieve zero voltage switching.

IL1
Io IL1 IL2
V in
+
IL2
Vo Io

Fig. 1: Interleaved ZVS Quasi Square Wave Buck Converter

The current ripple is more than 2 times the average output current. High turn-off current of the main
switch tends to increase the turn off losses, especially when minority-carrier devices such as IGBTs are
used [2].

Because of the high current ripple, interleaved parallel outputs are necessary in order to keep the ripple
current in both the input capacitor and the output capacitor low. With the interleaved parallel outputs a
controller is needed in order to ensure load current sharing and phase shift of the current ripple.

The most common solution in order to implement current sharing is analog peak current mode control [4].
The error signal of the output-voltage controller is used as a common peak current reference signal for all
parallel outputs. The common reference signal is compared with the instantaneous inductor current in a
separate controller for each output. The PWM output is set low if the inductor current is larger than the
reference signal. The result is a separate duty cycle for each module in order to level out the peak current
in all of the outputs. The sharing of the average current will therefore be dependent on the variation of
inductance in each output.

A direct implementation of the analog peak current mode control scheme in digital hardware would
require a very fast A/D converter because you would need a large number of samples per switching
period. The need for large signal processing capabilities would require expensive hardware. Therefore,
methods more applicable to digital control hardware have been developed [5, 6].

Digital control and sampling strategies

The TMS320F2812 DSP used in these experiments has two event-managers. With the event-manager an
up-down timer can be set up to a triangular wave form and compared to an input value to generate
symmetric pulse width modulation (PWM). The event-manager can then generate up to four interrupts. It
can generate an interrupt on timer underflow, on timer period match and on compare match both in up-
and down-counting direction. Fig.2a shows the available interrupts. A compare match triggers the
switching of the transistors.
Sampling of interleaved currents
Based on the theory of symmetric PWM, in steady state the peak current will be on compare match in up-
counting direction, the valley current will be on compare match in the down-counting direction, and the
average value of the inductor current will be on timer underflow and on period match. The interrupts can
trigger a sampling of the current. In which interrupt to sample the current may be selected based on if the
peak current, the valley current or the average current is to be controlled.

Timer1 Timer2
Timer PWM1 PWM2

Compare
PWM Compare 1&2

Int Int Int Int

Sample[n] Sample[n+1]
V in,V o,IL1,IL2 V in,V o,IL1,IL2
(a) (b)
Fig. 2: (a) Single triangle sampling and interrupts (b) Interleaved sampling and pulse width modulation
This method of sampling the current and generating a pulse width modulated signal is often used in new
digital control of motor drives. With the ZVS-QSW converter this sampling method can be very useful in
average current control in order to filter out the ripple current which will be more than 200% peak to peak
of the average current. Analog filtering of this ripple would result in long delay times in the feedback and
low bandwidth for the control, but with the timer underflow sampling this ripple current is filtered out
digitally. The factors that will reduce the bandwidth of this digital control will now be the delays in the
feedback loop, the effect of zero order hold (ZOH) sampling, and the computational speed of the DSP.

The average current may be sampled at both the period match and timer underflow. This can be utilized so
that all measurements, Vin, Vo, IL1 and IL2 are sampled at the same time. The average current in the L1
inductor is sampled at timer underflow of timer1. And the average current in the L2 inductor is sampled at
period match of timer2 which is the same as timer underflow of timer1. Fig. 2b shows the principle of
sampling and the pulse width modulation of the interleaved signals.
Control design
A digital average current sharing controller is implemented using symmetric PWM and timer underflow
sampling. The structure of the control system is shown in Fig. 3a. The bandwidth of the current mode
controller is reduced due to delays in the feedback loop and due to the effect of the zero order hold.
Linear control
The control to inductor current transfer function for one of the parallel outputs is derived by averaging
over one switching period and by linearization. Eq. 1 shows the derived transfer function. Ro is the load
resistance, L is the output filter inductance, and C is the output capacitor.

1
(s + )
iL ( s ) Vin RoC
H sys ( s ) = = ⋅ (1)
d ( s) L ( s2 + s + 1 )
RoC LC

The system transfer function is then discretized by adding a zero order hold element and sampler at the
sampling frequency of 50 kHz [9]. A discrete PI controller is then added to the system. It is the frequency
response of the discretized system that is studied. The gain and time constant of the discrete controller is
adjusted for sufficient open loop phase margin. The design criteria used is an open loop phase margin of at
least 500 with input voltages, Vin, up to 2 times the nominal input voltage.
Predictive control
With digital control, predictive methods may be used in order to compensate for the effect of zero order
hold sampling and delays in the feedback loop. In [6] a general predictive control law is proposed. This
method can be adapted to the average current sharing control of the ZVS-QSW converter. With symmetric
PWM and timer underflow interrupt sampling, the current in the inductor at the time, nTs, is given by the
following equation.

Vin − Vo V
iL [n ] = iL [n − 1] + ⋅ d n ⋅ Ts − o ⋅ d n '⋅ Ts (2)
L L

where iL[n] is the inductor current at the nth interrupt, Vin is the input voltage, Vo is the output voltage, dn is
the duty cycle in the nth period, L is the inductance, and Ts is the sampling period. The duty cycle can
also be described as dn=(1-dn’). Eq. (2) can be rewritten to
 IL1 PWM

V in
+ Compare
IL2
Vo
- dn' T s d n+1' Ts

Ts Ts

iL(t) Vin − Vo
- −Vo
PWM1 H iL1(Z) Sampler L
L
-
i[n-1] i[n]
H v(Z) Sampler ILavg,ref i[n+1]
-
PWM2 H iL2(Z) Sampler Voref

Digital control system Int Int Int

(a) (b)

Fig. 3: (a) Digital average current sharing control (b) Sampling and PWM with predictive control

Vin V
iL [n ] = iL [n − 1] + ⋅ d n ⋅ Ts − o ⋅ Ts (3)
L L

The predicted current at the next interrupt will then be

Vin V
iL [n + 1] = iL [n − 1] + ⋅ ( d n + d n +1 ) ⋅ Ts − 2 ⋅ o ⋅ Ts (4)
L L

The control objective would then be to control the predicted inductor current to the current reference
value, iL[n+1]= iLavg,ref. The next duty cycle,dn+1, can now be calculated based on Eq. (4)

L V
d n +1 = − d n + ⋅ (iLavg ,ref − iL [n − 1]) + 2 ⋅ o (5)
Vin ⋅ Ts Vin

Eq. (5) is the predictive control law for the average current sharing of the interleaved QSW converter. The
controlled current waveform and the symmetric switching and sampling scheme is illustrated in Fig. 3b.

Simulations of the converter control system

The simulations are done in Simulink. The modeling of the converter is with the dynamic node technique
[9]. Elements in the converter are modeled separately and connected together by capacitive nodes in the
system. The control system is modeled with the standard elements of the Simulink library. The values of
the circuit elements illustrated in Fig.3a are the same through all simulations and laboratory tests. The
values used are, L1=L2=13µH, C=40µH, Ro=2.1 Ω and Vin=10V.
Simulations of the interleaved converter with linear control
The simulation set up of the linear control system and the simulation result of a current reference step is
shown in Fig.4. The discrete transfer function of the current controller is based on the previously
described design criteria and takes into consideration the delay due to the zero order hold.
 Vin

Voltage input
Vin i_L
6
g i_L2 Zero-Order
RepSeq Hold1
Add Relay Transport g2 v cp 5
Delay
Terminator
Io vo
4
RepSeq2 dyNode dual Sync Buck Converter PI output
Add3 Relay1 Transport 1/R
Delay1 3
Resistive Load

num(z) Zero-Order
100 Hold 1
z-1
Gain1 Saturation Add1
Discrete Coilcurrent 1 [A]
Transfer Fcn 0
Outputvoltage[V]
Coilcurrent 2[A]
num(z) -1
100 0 0.005 0.01 0.015 0.02
z-1
Add4 Time [s]
Gain5 Saturation1 Discrete
Transfer Fcn1
1.2

Current reference

Fig. 4: Simulation set up and simulation result of a current reference step.

Simulations of the interleaved converter with predictive control

The simulation set up of the predictive control system is shown in Fig.5. The simulation result of a current
reference step is shown in Fig.6.

With the output voltage measurement, the predictive current controllers are coupled together. This can
result in oscillations. Therefore, the gain in the current feedback loop should be reduced in order to reduce
the oscillations. The gain will not be according to the predictive control law, but close to. The
performance of the controller is not significantly reduced by reducing the gain. Also a filter on the output
voltage measurement will reduce oscillations between the two current controllers.

Vin

Voltage input
Vin i_L

g i_L2 Zero-Order
RepSeq Hold2
Add Relay Transport g2 v cp Zero-Order
Delay 1 Hold
Terminator
Io vo
28e-6s+1
RepSeq2 dyNode dual Sync Buck Converter Zero-Order
Add3 1/R Transfer Fcn
Relay1 Transport Hold1
Delay1 Pred Out
Resistive Load
Noise
1 2/Vin
100
z
Gain1 Saturation Unit Delay Add2 Gain3

-K-

1 Add1
Gain
100
z
Gain5 Saturation1 Unit Delay1 Add5 -K-

Add4
Gain2

1.81

Constant2

Fig. 5: Simulation set up of the predictive controller.

The simulations were first done assuming no noise and no filter with reduced bandwidth on the voltage
measurement. The result of the no noise simulation is shown in Fig.6a. In any practical circuit this will not
be possible. A filter on the measurement will be needed and still then there will be some noise on the
sampling input. Therefore a simulation with more realistic filter and noise properties is performed. The
results of the predictive control with filter and noise is shown in Fig.6b.
 6 6

5 5

4 4

3 3

2 2

1 1

Coilcurrent 1 [A] Coilcurrent 1 [A]

0 0
Outputvoltage[V] Outputvoltage[V]
Coilcurrent 2[A] Coilcurrent 2[A]
-1 -1
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
Time [s] Time [s]

(a) (b)
Fig. 6: Simulation of a current reference step of the predictive controller (a) without and (b) with noise.

A comparison of the reference step response of the linear control and the predictive control show that the
predictive controller theoretically will have the faster step response. But, there is very little noise rejection
in the voltage feedback loop of the output voltage and this leads to ripple on the output. The ripple can be
reduced by filtering the voltage measurements more. But this will again reduce the performance. An outer
linear voltage control loop would result in better noise rejection and the negative feedback loop will
reduce the voltage ripple.

Test set-up and experiments

A control board with a Texas Instruments F2812 DSP is used to test the digital control techniques. Two
parallel synchronous buck converters are coupled together. The input voltage, Vin, the output voltage, Vo,
and the current, ILx, in each of the two inductors is sampled. The current sharing is controlled using the
two different digital control techniques implemented in the F2812 DSP.

The same circuit values as the values used in the simulations are used in the laboratory set up. The
measurement of a current reference step to the linear control is shown in Fig.7. The measurement of a
current reference step to the predictive control is shown in Fig.8.

The measurement of the reference step to the linear control system show a transient as expected from
simulations. The high frequency noise is rejected and the to parallel controllers work as two independent
current sources.
6 3

5 2,5

4 2
Voltage[V]

Current[A]

3 1,5

2 1

1 0,5

0 0
0 0,005 0,01 0,015 0,02
Time[s]

Vout[V] IL_1[A] IL_2[A]

(a) (b)
Fig. 7: Measured current reference step of linear controller (a) oscilloscope data (b) sampled data
 6 3

5 2,5

4 2

Voltage[V]

Current[A]
3 1,5

2 1

1 0,5

0 0
0 0,005 0,01 0,015 0,02
Time[s]

Vout[V] IL_1[A] IL_2[A]

(a) (b)
Fig. 8: Measured current reference step of predictive controller (a) oscilloscope data (b) sampled data

The measurement of the reference step to the predictive control system, show that noise on the voltage
measurement is reflected into the system. The noise on the voltage measurement results in ripple on
average output current. Also, the performance of predictive control is the reduced due to the reduced
bandwidth on the filtered output voltage measurement.

Conclusion
This paper has discussed and tested two digital control techniques for average current sharing of the
interleaved synchronous buck converter. The results both by simulation and experiments show that any
improvement in control performance by using a predictive control method is only possible when
implementing a low noise high bandwidth measurement on the output voltage. Higher performance of the
control is possible but not without the additional cost of better measurement hardware.

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