Oracle

 Confidential  

faq ORACLE’S SPARC M5-32 SERVER

Technical Frequently Asked Questions
March 26, 2013

This document is for internal purposes only, and is Oracle Confidential

Overview and Positioning

System Specifications / Installation Data
Software, Firmware, and Operating System
General Questions
Glossary

1.0 Overview and Positioning

What is the SPARC M5-32 Server?

The SPARC M5-32 server is a new massively scalable symmetric multiprocessor (SMP) architecture data
center class server with advanced RAS capabilities for very large mission critical enterprise workloads
and system consolidation opportunities. Utilizing the new 6 core, 8 threads per core M5 processor with a
large 48MB shared level 3 cache, the SPARC M5-32 server delivers high performance per processor
core and extreme system throughput with up to 1536 total processor threads in a 32 processor
configuration. The SPARC M5-32 server has the highest total system memory for  a  32  processor  server
at 32 terabytes within a single cabinet for the most demanding workloads and also includes expansive IO
connectivity with 64 internal high performance PCIe Gen 3 slots and 32 internal hard disk drives. All in the
same single server chassis thus reducing datacenter complexity and cost. A new unique combination of
virtualization technologies delivers maximum flexibility for virtualizing workloads, tackling server
consolidation and multi-hosting deployments.

The design of the SPARC M5-32 server has merged high performance mission critical data center server
technologies with the best of the SPARC T-series servers by sharing common processor core (SPARC
S3 core), virtualization technologies (Dynamic Domains, Oracle VM for SPARC, and Solaris 11 and
Solaris 10 Zones),and system management (ILOM). This blend of technologies now completes an end-
to-end product family of SPARC processor, Solaris 11 and Solaris 10 operating system based servers
from the SPARC T-series servers to the SPARC M5-32 server with the benefit of common virtualization,
system management and administration.

2.0 System Specifications / Installation Data

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Q: Are there special power requirements for the SPARC M5-32?

The SPARC M5-32 is 3-phase power only and dual power grid ready. The SPARC M5-32 has six AC
power inputs, three per power grid. Unlike the previous SPARC M9000 server, a 3-phase power cord
option is available, and all six cables are delivered.

Q: Is the airflow of the SPARC M5-32 the same as for the M9000-32?

No. While the M9000-32 has bottom to top airflow, the M5-32 has front to back airflow.

Q: Is a raised floor required for the SPARC M5-32?

No. M5-­‐32  has  front  to  rear  airflow  and  can  be  installed  in  either  raised  floor  or  true  floor  data  centers.      
Special  consideration  should  be  taken  for  raised  floor  installations  due  to  the  total  server  weight.      See  
SPARC  M5-­‐32  Installation  Guide  for  more  information.

3.0 Software, Firmware, and Operating System

Q: What are the required software versions for the SPARC M5-32 Server?

System Software Version Level

System Firmware (includes 9.x

hypervisor, host config, OBP,
POST, ILOM)
Minimum OS (Control Solaris 11.1
Domain)
Minimum OS (Guest Solaris 10 1/13
Domains) Solaris 10 Update 9 or Update 10 (with S10
U11 Maintenance Bundle U11)
Minimum level Oracle VM for 3.0
SPARC
Oracle Enterprise Ops Center Available mid-2013

Solaris 11.1 will be pre-installed on the control domain

Q: Where can I find firmware updates for the SPARC M5-32?

For firmware and software updates, please log into MOS at https://support.oracle.com

Q: Since there’s no built-in DVD, how is software loaded on the SPARC M5-32?

The ILOM supports rKVMS. Like on the T-series, the M5-32 can access a DVD using the remote media
capability of the ILOM.

Physical Domains (PDoms)

The SPARC M5-32 can support up to four physical domains, or PDoms. These can also be referred to as
Dynamic Domains. Each PDom is made by combining one or more DCUs. If a PDom is originally made

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from a single DCU with four CMUs, and more CPUs are required, a single CMU cannot be added to the
PDom. A complete DCU must be added.
A DCU can be place in only a single PDom. The boards in a DCU can not be split between different
PDoms.

4.0 General Questions

Q: Does the M5-32 support hot-plug?

Unlike the previous SPARC M8000 and M9000, the SPARC M5-32 does not support hot-plug of a CMU
board while the PDom is running. Adding/removing a CMU is a cold service event. However, hot-plug of
PCIe cards, disks, fans, power supplies, and the redundant service processors are supported. The ability
to dynamically reconfigure the logical domains is also supported.

Because physical domains can be resized, even if a reboot is required, they are called Dynamic Domains
because they provide full isolation and are recognized as hard partitioning for Oracle licensing purposes.

Q: Can additional CMU boards be added (or removed) to the SPARC M5-32 server?
Unlike the previous M8000 and M9000 servers, the SPARC M5-32 does not support hot-plug of the CMU
boards. The target PDom must be brought down before adding (or removing) a CMU to one of the DCUs.
If a DCU is not configured in a running PDom, then a CMU can be added (or removed) to that DCU
easily.

Q: What about adding (or removing) a DCU to a running PDom?

Adding (or removing) a DCU to a PDom is the same as adding (or removing) a CMU to an active DCU.
The addition (or removal) of a DCU to a PDom is a cold-service event. The PDom must be shut down
first.

Q: What electrical provisioning is required for the SPARC M5-32 server?

Unlike the previous M8000 and M9000 servers, the SPARC M5-32 is 3-phase only. Please review the
SPARC M5-32 Installation Guide (link reference at end of this document) for specifics on electrical and
installation considerations.
A power calculator is available to provide approximate power requirement estimations at:
http://www.oracle.com/us/products/servers-storage/sun-power-calculators/index.html

Q: Do the SPP boards have failover like the primary SP boards?

Yes, they do. If you have a PDom configured with more than one DCU, then there are multiple SSPs in
the PDom. Only one is primary. If it should fail, the system will automatically failover to the next SPP in
the PDom, with no downtime. However, replacing the faulty SPP will require the PDom to be shut down.

Q: How are logical domains configured?

They are configured just the same as they are on the T-series. However, instead of a single hypervisor for
the entire platform, the SPARC M5-32 supports a separate hypervisor for each dynamic domain (PDom).
This means the SPARC M5-32 could have up to four different hypervisors running at the same time.

5.0 Glossary

 
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Alternate pathing See Multipathing; sometimes used synonymously with multipathing.

ASR Automatic system recovery. A RAS feature that initiates a system reboot
sequence that bypasses failed system components or a software failure.
ATO Assemble-To-Order. Allows customers to configure options from the
manufacturing plant.
Availability A measurement of the percentage of time that a system is accessible by
users and is providing service.
Base IO card SPARC M5-32 Base IO card supports dual pathing to two pairs of 2.5-in
SAS hard disk drives and includes two 10-Gb Ethernet ports
Bounded Physical Domain Similar to a Physical Domain, except it is limited to only a single DCU.
This means it cannot expand beyond 8 M5 processors and it does not
use the SSB boards.
CMT See Chip Multithreading Technology.
CMU CPU/Memory Unit (board), contains two SPARC M5 processors and 64
DIMM slots
Chip Multithreading Allows for the simultaneous execution of two threads of code per
Technology processor generally providing better performance than previous
generations of processors.
Domain Configuration Unit A grouping of four CMU boards, one IOU both controlled by own SP
(DCU) Proxy
DR Dynamic Reconfiguration. DR allows the logical assignment of system
resources (CMU boards, IO options) to system domains.

Physical Domain A Physical Domain (PDom) made from one or more DCUs. A Physical
Domain utilized the Scalable Switch Board (SSB) to communicate
between DCUs. See Bounded Physical Domain.
Dual pathing See Multipathing; sometimes used synonymously with multipathing.
Fault resilience Capability of a system to mask many individual errors, but not all. This
approach generally requires redundancy of some components and
additional software. An example would be the dual path capability and
automatic failover for storage and networks. Another term for “high
availability.”
Fault tolerance Capability of a system to mask any individual point of failure. This type
of system is typically implemented with component redundancy and
clock synchronization to maintain each unit in “lock step” with it s
counterpart.
FC-AL Fibre Channel arbitrated loop. A loop topology used with Fibre Channel.
FMA Solaris fault management architecture. Generates fault indictments
from the service processor. FMA provides three system activities: error
handling, fault diagnosis, and reponse.
Hard Domain See Physical Domain (PDom)
High availability Capability of a system to mask many individual points of failure or to
significantly compensate for them. This type of system is built upon
standard components with limited hardware and/or software

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components to minimize the impact of failures. Generally, this type of

system is less costly than a fault tolerant system.
Hot-plug A component that can be electrically safe to remove or add while the
system is still running. Typically, the system must be rebooted before
the hot-plug component is configured.
Hypervisor The SPARC Hypervisor is a small firmware layer that provides a stable
virtualized machine architecture to which an operating system can be
written. There is one hypervisor per PDom.
ILOM Oracle Integrated Lights-Out-Manager software
IO board unit (IOU) or IO The SPARC M5-32 includes 4 IOUs that each include sixteen PCIe Gen
column 3 slots and four Base IO card slots
Logical domain A virtual machine comprising a discrete logical grouping of resources
that has its own operating system and identity within a single computer
system
Multipathing A higher availability option which provides two independent paths to
storage and/or networks. An intermediate software layer is generally
required to mask the failure of one path from the application. When both
paths are functional, higher bandwidth and throughput is possible as a
secondary benefit beyond higher availability.
PCI Peripheral component interconnect. An industry-standard for connecting
peripherals such as disk drives, tape drives and other external devices.

PCICS PCI Cassette of IOU. A short dedicated PCIe cassette provided for to fit
into the IOU board
PSU Power Supply Unit
Physical Domain (PDom) An electrically fault-isolated hard domain comprised of one or more
DCUs. Each PDom is an independently configurable and bootable
entity with full hardware domain isolation for fault isolation and security
purposes.
RAS Reliability, availability, and serviceability, Three aspects of the design of
a system contributing to continuous operation and minimizing system
downtime for services. Together reliability, availability, and serviceability
provide for near continuous system operation.
Redundancy Duplication for the purpose of achieving fault tolerance. Refers to
duplication or addition of components.
Reliability Ability of a system to operate continuously without failures and to
maintain data integrity. Reliability influences MTBF.
rKVMS Remote keyboard video mouse and storage
SC System Control. See Remote System Control.
SCSI Small Computer Systems Interface. An ANSI standard for controlling
peripheral devices by one or more host computers.
Serviceability A measurement of the time to restore a system to operation when a
failure has occurred. Serviceability influences MTTR.

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SONET Synchronous Optical Network/OC48, a networking standard providing

up to 2.4 Gbits/sec. of line speed over a distance of 2 km with single
mode Fibre Channel.
SP Service processor
SPP Service processor proxy. There is one SPP per DCU to control and
monitor the components in the DCU.
SSD Solid-state drive

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