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An Overview of RF Power Amplifier Techniques and Effect of Transistor

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Article  in  International Journal of Applied Engineering Research · January 2014

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 International Journal of Applied Engineering Research
ISSN 0973-4562 Volume 9, Number 2 (2014) pp. 257-276
© Research India Publications
http://www.ripublication.com

An Overview of RF Power Amplifier Techniques and Effect

of Transistor Scaling on its Design Parameters

Veeraiyah Thangasamy *1, Noor Ain Kamsani2, Mohd Nizar Hamidon3,

Muhammad Faiz Bukhori4
1, 2, 3
Department of Electrical and Electronics Engineering,
Universiti Putra Malaysia, 43400 UPM Serdang, Malaysia * veeraiyah@gmail.com
4
Department of Electrical, Electronics & Systems Engineering,
Universiti Kebangsaan Malaysia, 43600 Bangi, Malaysia

Abstract

A strong market growth for wireless systems has taken place over the last two
decades, driven by persistent demands of ever smaller form-factor, increased
power-efficiency and reliability. Radio frequency (RF) power amplifier (PA)
is a critical block in a wireless transceiver, consuming most power and
affecting battery life. Battery life is directly affected by the linearity and
efficiency characteristics of the integrated PA. In this paper, we critically
review key theories and techniques that are used in RF power amplifier
designs, with emphasis on efficiency and linearity improvement. The device’s
physical size, material and processes greatly affect the power characteristics of
PAs. Hence, we also critically review how scaling, semiconductor materials
and technologies relate to RF power amplifier designs, with emphasis on
power and frequency.

Keywords – RF power amplifier, linearity, efficiency, peak-to-average power

ratio (PAPR), Scaling, current gain cut-off frequency (fT).

I. INTRODUCTION
Modern communication systems such as mobile phones, satellite links, and radio
broadcasts apply a wide range of frequencies from the HF to millimeter wavelength.
The transmitter output power of these systems range from a few milliwatts to
megawatts. Various types of modulation schemes such as QPSK, GMSK and OFDM
are in use although multilevel QAM is increasingly popular for emerging applications.
The choice of a particular PA technique is often a challenging consideration between
efficiency, linearity and bandwidth requirements; because no single PA technique
 258 Veeraiyah Thangasamy et al

suits all the applications. RF power amplifier (PA) converts the dc-power of the
supply into RF output power. A transmitter consists of one or more stages of PAs and
additional circuits including signal generators, modulators, frequency converters,
processors and power supplies. The power amplifier may be a single stage or
multistage depending on the output power level required.
In this paper, basic PA topologies of class-A, -B, -C, -D, -E, and -F are reviewed
and their performance discussed in section II. Different architectures are employed to
improve the efficiency and linearity of PAs. These architectures include envelope
elimination and restoration (EER), envelope tracking (ET), Doherty, and outphasing;
all of which are discussed and theirs output power against efficiency is compared in
section III. In section IV, the effects of transistor scaling on PA’s power and
frequency characteristics are discussed. How different semiconductor materials affect
the PA’s power and frequency are reviewed in section V. The various conventional
transistor technologies such as CMOS, HBT, and HEMT are discussed in section VI,
and finally a conclusion is drawn in section VII.

II. RF POWER AMPLIFIER TOPOLOGIES

A transistor is a key device in any power amplifier circuit. The biasing circuit and the
drive signal at the input of PA will determine the different transistor topologies of
operation. Fig.2 shows the ideal output and transfer characteristics of a NMOS
transistor of a single-ended PA circuit of Fig.1 with the location of quiescent point for
different topologies of operation.

VDD
Vgs5
Idc
Vgs4
---------> V d s
---------> Id

RFC
Vgs3 Class A
Output o
Filter Vgs2
Idrain Io
Drive Vgs1 Class AB
Q1 + +
and Vo Class C
Vds RL Class B
Bias - - o
------->Vds Vth Voc
------->Vgs

Fig.1. Single-ended PA using NMOS Fig.2. Ideal output and transfer

transistor characteristics of NMOS transistor.

A. LINEAR MODE PAs

Class-A: In this topology, the quiescent point is set in the middle of the transfer
characteristics as shown in Fig.2, and the transistor remains in active region at all
time, that is, Vgs is maintained between Vth and Voc (open channel voltage). As a
result, the drain current and the drain voltage waveform are sinusoidal as shown in
Fig.3a. Both cycles of the input signal appear at the output and hence the amplifier is
highly linear and the gain is high. However the efficiency is poor because of the
saturation voltage of the transistor. The theoretical efficiency is 50 %. To obtain the
An Overview of RF Power Amplifier Techniques and Effect 259

optimum efficiency close to the theoretical value, the design for optimum load
resistance (Ropt) is essential [1]. The class-A topology is perfectly linear and there is
no harmonics developed by the transistor during the amplification process, and hence
class-A PAs can be operated until the maximum frequency capability (fmax) of the
transistor. The class-A operation is well suited for varying envelope modulated input
signals (such as QAM) because of its high linearity.
Class-B: The transistor is biased such that the quiescent point lies at the threshold
point (Vth) of the characteristics as shown in Fig.2, so that the transistor is ON only
for half the cycle of the input signal, and the drain current is half sinusoidal as shown
in Fig.3b. Full sinusoidal drain current can be obtained by connecting two transistors
in push-pull manner in which each transistor conducts for half the cycle of the input.
The efficiency of ideal class-B PA is 78.5% which is higher than in class-A operation.
The pair of transistors in push-pull connection should be perfectly matched to obtain
an output current of smooth sinusoidal. However, cross-over distortion occurs in
class-B when the input signal crosses zero where both the transistors are in their cut-
off state. This cross-over distortion degrades the linearity.
Class-AB: The poor linearity in class-B is improved by compromising the efficiency.
In this mode, the transistor is biased between class-A and –B, and the efficiency lies
between 50-78.5%. The cross-over distortion associated with class-B is reduced in
class-AB and hence the linearity is improved.
Class C: For PAs intended for narrow band application, it is possible to reduce the
bias voltage below the cut-off voltage of the transistor and the transistor is said to be
in class-C operation. In this class of operation, the transistor is active less than half the
cycle of the input signal and thus the linearity is lost, but the efficiency theoretically
increases to 78.5-100%. Class-C operation produces higher order harmonics because
of nonlinearity of operation. Third harmonic can be controlled by bias control and the
second harmonic is limited by employing the differential structure [2].
Class A input Class A output Class B input Class B output
2 2
← Vin
←V in
Vq
←V ds ←V ds
1 Vq,Vth 1

Vth
←Id
←Id
0 90 180 270 360 450 540 0 90180 270 360 450 540 0 90 180 270 360 450 540 0 90 180 270 360 450 540
← θ = 360 → ← θ=180 →

(a) (b)
Class AB input Class AB output Class C input Class C output
2 2

←Vin
←Vin ←Vds
Vq Vth 1
Vth
1 ←Vds
Vq

←Id ←Id
0 90 180 270 360 450 540 0 90 180 270 360 450 540
0 90 180 270 360 450 540 0 90 180 270 360 450 540 ← →
← θ=180-360→ θ<180

(c) (d)
Fig.3. Waveforms of ideal class-A, -B, -AB, -C power amplifiers.
260 Veeraiyah Thangasamy et al

B. SWITCHED MODE PAs

Class-D: In contrast to the class-A, B, -AB and -C PAs discussed above, the transistor
in class-D amplifier operates as a switch as shown in Fig.4. The drain current is half
sinusoidal and the drain voltage is a square wave as shown in Fig.7 (a). Since the
drain voltage and drain current do not exist at the same time, ideally there is no power
loss in the transistor and hence the efficiency reaches 100%. However, in practice,
there are losses due to non-zero drain resistance, loss due to parasitic capacitance or
inductance and switching loss due to transit time of transistors which limit the
practical efficiency less than 80% [3].One way to reduce the drain resistance is to
have large transistors. However, large transistors will have large parasitic output
capacitance that has to be charged and discharged to every cycle of the RF input
which limits the maximum usable frequency of class-D PAs. For the given output
power, a class-D PA should be operated with maximum voltage and minimum current
for achieving higher efficiency [4].
Class-E: The class-E amplifier concept was introduced by Sokal [5] and is shown in
Fig.5. The output network consists of a shunt capacitor and a series resonant circuit.
In class-D mode, the parasitic capacitance of the transistor degrades its performance.
Where as in class-E, the parasitic capacitance becomes part of the output network and
hence its effect on the transistor performance is minimized and this makes class-E
design more promising. The output network shapes the drain current and the drain
voltage such that no overlap occurs between them as shown in Fig.7(b). A driving
stage precedes the switching transistor of the final stage. Maximum output power can
be obtained when the duty cycle of the drive input frequency is 50 %. Moreover, to
obtain maximum efficiency class-E includes two conditions: zero voltage switching
(ZVS) and zero voltage derivative switching (ZVDS) [5].
Class-F: ZVS condition of the above class-E operation requires fast drive signal
which in turn increases the stress on the active device. So in class-F amplifier, the
active device is operated in class-B mode and the harmonics at the output are
combined to increase the power output and efficiency [6]. Drain voltage adds odd
harmonics to build a square wave and drain current adds even harmonics to shape a
near sinusoidal wave as shown in Fig.8. Ideally, the overlapping of current and
voltage waveform is eliminated and the transistor consumes no power while switching
resulting in 100% efficiency.

Fig.4. Class-D Power Amplifier Fig.5. Class-E power amplifier

An Overview of RF Power Amplifier Techniques and Effect 261

Fig.6. Class-F power amplifier

Class D input Class D output Class E input Class E output

1 1
←V in ←V ds ←Vin ←Vds

Vth Vth
← Id
←Id

0 90 180 270 360 450 540 0 90 180 270 360 450 540 0 90 180 270 360 450 540 0 90 180 270 360 450 540

(a) (b)
Class F input Class F output

1
←V in

Vth
←Id ←Vds

0 90 180 270 360 450 540 0 90 180 270 360 450 540

(c)
Fig.7. Waveforms of ideal class-D, -E and -F power amplifiers.
Drain voltage

← 1st harmonic
← combined
harmonic
← 3rd
harmonic

0 180 360 540 720

ωt
Drain current

← combined
harmonic

← 2nd
harmonic
← 1st harmonic
0 180 360 540 720
ωt
Fig.8. Waveforms of drain current and drain voltage in class-F PA employing
harmonic-peaking
 262 Veeraiyah Thangasamy et al

The technical comparison of class-A, B, AB and C PAs are summarized in Table

I. Class-A is ideal to amplify any input signal that requires high linearity, but its
efficiency is poorest amongst all PAs. The highly efficient class-AB PA is most
suitable for mobile devices while offering higher linearity than class-B and class-C
PAs. The class-C PA is well suited for CW (continuous wave) applications or FM
signals where linearity is not a primary concern. All three classes of switched mode
PA have a theoretical efficiency of 100%. However, the drain current of Class-D and
E amplifiers produces more harmonics and the waveforms are not purely sinusoidal
[7]. In Class-F PA, the harmonics are controlled not to appear to the load and
comparatively near sinusoidal waveform is developed at the load. Therefore, class-F
design is more promising for cellular and personal communications at VHF and UHF.

TABLE 1 Summary of PAs Topologies

Topology Bias Point Conduction Theoretical Linearity

Angle (%) Efficiency (%)
Class A 0.5 100 50 Good
Class B 0 50 78.5% Average
Class AB 0-0.5 50-100 50-78.5 Moderate
Class C <0 <50 78.5-100 Poor
Class D Cut-off and saturation 50 100 Poor
Class E Cut-off and saturation 50 100 Poor
Class F Cut-off and saturation 50 100 Poor

III. PA EFFICIENCY AND LINEARITY ENHANCEMENT TECHNIQUES

PAs exhibit high linearity when operated in linear mode (class-A, -B and -AB) and
exhibit high gain when operated in switched mode (class-D, -E and -F). The high
efficient switch mode PAs can amplify only constant envelope modulated signal (such
as GSM) without distortion. Whereas, spectral efficient high data rate communication
systems currently in use such as WiMAX and LTE requires varying envelope and
phase modulated signal. Thus, modern communication systems require highly linear
PAs to avoid adjacent channel interference and distortion. Though many techniques
are proposed and investigated by researchers, techniques such as Doherty, envelope
elimination and restoration (EER), envelope tracking (ET) and outphasing are found
to be most prominent for efficiency and linearity enhancement. This section will
discuss these techniques.

Envelope Elimination and Restoration (EER)PA:

The EER technique was proposed by Khan [8] in 1952. It mainly improves the
linearity of switched (class-E and -F) RF amplifier. The input RF signal is split into
two paths: one path through a limiter which extracts the phase modulated signal and
another path via an envelope detector which extracts the amplitude modulated signal
as shown in Fig.9. The phase modulated signal is amplified by the switched RF PA
and the amplitude modulated signal modulates the power supplied to the RF PA and
thus restore the amplitude modulation at the output.
An Overview of RF Power Amplifier Techniques and Effect 263

Fig.9. Envelope Elimination and Restoration (EER) PA block diagram

PAs applying Khan technique have very high linearity and the linearity depends
upon the power supply modulator rather than switched mode RF amplifier [9].
Alignment of the phase and envelope paths and the bandwidth of the supply
modulator are very important to achieve maximum linearity. Faab in [9], mentioned
two conditions for maximum linearity: i) the envelope detector bandwidth should be
at least twice the RF signal bandwidth, and ii) the misalignment should not exceed
inverse of the one-tenth of the RF bandwidth.
For wide dynamic-range OFDM employing in modern communication where the
peak-to-average power ratio (PAPR) is high, it is more challenging to realize the
limiter [10]. Linear regulator if used as supply modulator it will develop much power
loss as heat. In [11], a buck converter, integrated in IC was presented as supply
modulator. It has a bandwidth of 15 MHz and operated at 130 MHz. A multilevel
converter in series with series regulator was proposed in [12], which provides
increased efficiency compared with a linear regulator.

Envelope Tracking (ET) PA:

This ET architecture is similar to EER architecture. However, the RF PA operates in
linear mode (class-A, -B and -AB). The RF input drive preserves both amplitude and
phase information. A time-varying voltage proportional to input RF signal is obtained
by an envelope detector and used to control a supply modulator as shown in Fig.10.
The supply modulator output dynamically control the drain voltage of the RF PA and
reduces power loss as shown in Fig.11.

Fig.10. Envelope Tracking (ET) PA block diagram

264 Veeraiyah Thangasamy et al

(a) (b)
Fig.11. Waveforms (a) without ET (b) with ET

In ET PA, the linear mode RF PA is always operated in deep saturation region to

obtain high efficiency [13]. Since the modulator control the power loss in the system,
overall efficiency of the ET PA is the product of the RF amplifier efficiency and the
modulator efficiency, given by [14]:
ηETPA= ηRFPA + ηmod.
In [15], a switching modulator was employed as the supply modulator to obtain
wide bandwidth and high efficiency. When the RF amplifier is operated near
maximum output power region, the output power is more sensitive to drain bias. On
the other hand, when it is operated in the back-off region, the output power is
sensitive for RF input voltage. Therefore, any noise developed by the supply
modulator will be present at the drain of the RF amplifier and possibly fall into the
receiver band [16]. So, a low noise supply modulator must be designed accurately in
this architecture.

Doherty Architecture PA:

This architecture was developed in 1932 [17], and it increases the average efficiency
of the linear mode PA by parallel combination of their output powers as shown in
Fig.12. The carrier PA is in the class-B mode while the peaking PA is biased into
class-C mode. The operation of Doherty PA is best explained in [18]. In the low-
power region, the carrier PA is active and the peaking PA is cut-off. This is because
the RF input is insufficient to overcome the negative bias of the class-C peaking PA.
In the medium-power region, the RF input increases and hence the carrier PA
saturates and the peaking PA becomes active. In peak-power region, both PAs are
saturated and each PA delivers half the output power. The resultant instantaneous
efficiency curve for the typical Doherty PA is shown in Fig.13.

Fig.12. Doherty PA block diagram

An Overview of RF Power Amplifier Techniques and Effect 265
1

.9

.8

.7

Efficiency
.6
←Doherty PA ←Class-B PA
.5

.4

.3

.2

.1

0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1
Output Power(Normalised)

Fig.13. Output power versus efficiency of Doherty PA [18]

Outphasing Architecture PA:

This architecture was introduced by Cheriex [19] in 1935, and its principle is shown
in Fig.14. The amplitude and phase modulated input signal S(t) is split into two
constant envelope out-phased signals S1(t) and S2(t). The input signal envelope
information is transformed into the phase difference α(t) between S1(t) and S2(t).
Then, the two signals are amplified by highly efficient non-linear PAs (class-B, C, D,
E, F). By combining the outputs, an amplified version the original signal is recovered.
The output signal exhibits high efficiency and high linearity, and hence this technique
also called as LINC (Linear Amplification using Nonlinear Components). Practically,
there are many difficulties that degrade the performance [20]-[24]. The operation of
signal separator is quite complex and difficult to implement using RF analogue
components. Mismatch between the two PAs will introduce more distortion in the
output. The efficiency of the system is constrained by the efficiency of the power
combiner at the output. This architecture is not suitable for signals with large peak-to-
average ratio.

Fig.14. Outphasing PA block diagram

 266 Veeraiyah Thangasamy et al

In section II, different topologies of PAs are discussed. Class-A, -B, and -AB PAs
are better in terms of linearity but they exhibit poor efficiency. On the other hand,
class-D, -E and -F PAs are more efficient but poor in linearity. Hence, efficiency is
achieved at the cost of linearity and vice-versa. To improve the linearity and
efficiency, four different techniques are discussed in section III. In all the four cases,
improvement in efficiency is achieved by additional circuit complexity compared to
conventional linear and switched mode PAs. For the EER and ET PAs, the
complexity arises due to power supply modulation. In the case of outphasing and
Doherty PAs, the two signal branches used contribute to circuit complexity.
The comparison of theoretical efficiencies for the four cases is shown in Fig.15.
The graph shows that EER, ET and outphasing architectures have better efficiency.
However, they are relatively more complex compared with Doherty PA. Doherty
technique is more suitable for efficiency enhancement for base station PAs. However,
as shown in the Fig.15, the efficiency of Doherty PA degrades at low power levels.
Also, the use of quarter-wave matching line provides a narrow bandwidth, so it is not
suitable for wideband applications. The outphasing PA has good efficiency over a
wide range of output power. However, use of non-isolated combiner at the output will
create strong nonlinearity. On the other hand, use of isolated transformer combiner
can improve the linearity but leads to increased complexity.
1

0.9
EER PA
0.8 ↓
Outphasing PA→
0.7
Efficiency

0.6
ET PA→ ← Doherty PA ←Class-B PA
0.5

0.4

0.3

0.2

0.1

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Output Power(Normalised)
Fig.15. Output power versus theoretical efficiency of EER, ET, Doherty, Outphasing
and class-B PAs [9]

IV. TRANSISTOR SCALING

The reduction of the transistor’s physical size, otherwise known scaling, enables
increased number of transistors to be fabricated on a given chip. This is reflected on a
trend over the last 4 decades that closely follows the observations of Moore’s Law –
which describes that transistor count on ICs doubles every 18 months. Transistor
scaling effectively increases computational speed and functionalities while driving the
cost per functions down for every technology generation. The ITRS roadmap of the
different technology nodes are shown in Fig.16 [25], which shows that as one
An Overview of RF Power Amplifier Techniques and Effect 267

technology node advances to another, the transistor dimensions are scaled down by a
factor of 1.4, or the size shrink by a factor of almost 0.7.
400

350 350nm
Scaling factor
S=350/250=1.400
300
Shrink factor
1/S=250/350=0.714
Technology Node

250 250nm

200
180nm
150
130nm

100 90nm
65nm Projection
45nm
50 32nm
22nm 16nm
11nm 8nm
0
1996 2000 2004 2008 2012 2016 2020
Year

Fig.16. Transistor technology nodes

Two scaling techniques are employed: full scaling and constant voltage scaling.
Full scaling parameters are shown in Table II [26], in which the dimensions of the
transistor and the supply voltage are scaled with same factor so that the electric field
remains constant. Constant voltage scaling parameters are summarized in Table III, in
which the dimensions of the transistor are scaled but the supply voltage is kept
constant.
It can be seen from the table that full scaling reduces the power dissipation by a
factor S2 at the cost of reduction in drain current by a factor of S. On the other hand,
constant voltage scaling increases the drain current by a factor of S but also increases
power dissipation by the same factor. The power density for the case of constant
voltage scaling is increased by a large factor S3, which could raise reliability issues
for integrated PAs. Due to the scaled down channel length, the transit time of carriers
is decreased resulting in increased frequency of operation of PAs. The increase of
drain current in constant voltage scaling would further extend the frequency due to
faster charging and discharging of transistor capacitance.
The choice of a particular scaling strategy therefore depends on the target
application. PAs for a base station transceiver require power output in the order of
watts; hence constant voltage scaling could be used in view of the high power
requirements. Whereas, the full scaling technique will fulfill the requirement of low
power dissipation (of a few milliwatts) of mobile devices.
 268 Veeraiyah Thangasamy et al

TABLE II Full Scaling Parameters

Transistor parameter Before scaling After scaling

Channel length L L/S
Channel width W W/S
Supply voltage VDD VDD/S
Threshold voltage Vt Vt/S
Transit frequency fT fT ×S
Drain current ID ID/S
Power dissipation P P/S2
Power density P/Area P/Area

TABLE III Constant Voltage Scaling Parameters

Transistor parameter Before scaling After scaling

Channel length L L/S
Channel width W W/S
Supply voltage VDD VDD
Threshold voltage Vt Vt
Transit frequency fT fT ×S2
Drain current ID ID×S
Power dissipation P P×S
3
Power density P/Area S ×P/Area

V. SEMICONDUCTOR MATERIALS
The 57–64 GHz industrial–scientific–medical (ISM) band is available for ultrahigh-
speed data communications. It offers a thrilling opportunity for wireless personal area
network (WPAN) applications, such as real-time short-range gigabits/second video
transmission [27]. As multimedia broadband services get increasingly popular, the
demands for high-frequency devices are growing. The 10- and 40 GB/s systems are
being deployed, and development of future 160 GB/s systems is underway.
Device scaling, as described in section IV, would be a strategy to attain high
frequency of operation of PAs. However, as device scaling enters the nano-scale, the
intrinsic physical limits of Silicon could limit the scaling benefits by the year 2020
[28]. Therefore, the wide bandgap III-V semiconductor materials are being used in
parallel to Si in order to increase the device frequency. Table IV shows the physical
characteristics of Si and other main wide bandgap semiconductor materials [29].
 An Overview of RF Power Amplifier Techniques and Effect 269

TABLE IV Physical Characteristics of Si and Main Wide Bandgap Semiconductors

Characteristic Si GaAs InP SiC GaN Diamond

Bandgap, 1.12 1.43 1.35 3.26 3.45 5.45
Eg [eV]
Electron mobility, 1500 8500 5400 1000 1250 10000
µn [cm2/V.s]
Breakdown field, 300 400 500 3200 2000 2200
Ec [kV/cm]
Thermal conductivity, 1.5 0.46 0.68 4.9 1.3 22
λ [W/cm.K]
Electron drift velocity, 1 1 1 2 2.2 2.7
vsat [×107cm/s]

As can be seem from the Table IV, electron mobility in GaAs and InP is higher
than in Si, which increases the fT and fmax of the device. Higher drift velocities of
electrons in SiC and GaN boosts the current gain of the device, resulting in high
output power. The higher thermal conductivity of SiC and diamond, results in better
heat dissipation and device reliability. Higher breakdown field of the wide bandgap
materials results in higher breakdown voltage, which allows the device to operate at
higher operating voltages than a Si-based device can. The breakdown voltage of a
junction is given by [29]:
2
ε E
VB ≈ r c (1)
2qN d
where q is the charge of electron and Nd is the doping concentration. With a higher
breakdown voltage, more doping can be applied to the material resulting in reduction
in the drift region. This will shorten the transit time of electron resulting in higher fT
and fmax. An appropriate comparison of operating voltage, fT and fmax is discussed in
the following section. Diamond demonstrates the capabilities of the best theoretical
performance in every category compared with other wide bandgap materials.
However, this material requires high temperature for processing and has an expensive
cost compare to other materials. In other reported works diamond has been used in
sensors, oscillators and field emission devices but no power device has reported using
diamond as device material yet. It is projected that the diamond will be used as device
material for power amplifier in the next 20 to 30 years.

VI. HIGH FREQUENCY TRANSISTOR TECHNOLOGIES

Millimeter wave (mmW) technologies have evolved tremendously in recent years for
applications such as automotive radars, satellite systems and point-to-point radios.
The various technologies are shown in Fig.17. The reported current-gain cutoff
frequencies and device operating voltages for various transistor technologies are
summarised in Fig.18 and Fig.19 respectively.
270 Veeraiyah Thangasamy et al

Fig.17. High frequency transistor technologies

Silicon CMOS technology is very popular in industries because of its low cost,
low supply voltage and high integration capability. However, its low breakdown
voltage, low operation speed and increased leakage due to scaling are serious
drawbacks at millimeter wave frequencies. Silicon-based BiCMOS integrates the
BJT/HBT with CMOS. Due to moderate operating voltage and moderate cutoff
frequency in BiCMOS devices (as shown in Fig.18 and 19), this technology is able to
address the power and frequency requirements of the emerging 60 GHz WLAN and
77 GHz automotive radar applications [26].

1000 [43] 10
BiCMOS BiCMOS
900 GaAs HEMT 9 [57] GaAs HEMT
GaN HEMT GaN HEMT
800 InP HEMT 8
InP HEMT
SiGe HBT
SiGe HBT
700 InP HBT 7 [55]
[45] InP HBT
Operating Voltage(V)

600 [59] 6 [35]

fT(GHz)

[47] [48] [52] [56] [36]

[42]
500 [46]
5 [54]
[49]
[44]
400 [58] [44]
[51] [41] 4
[40] [42]
300 [35] [31] [38] [33]
[52] [34] [31]
3
[36] [37]
200 [50] [61] [30] [38]
[60]
[56] 2
[32] [40]
[54]
100 [39]
[37] [49] [58] [61]
[53] [55] [57] [48] [34]
[33] 1 [46]
[51]
[60]
0 [47] [59]
0 50 100 150 200 250
0
Technology Node(nm) 0 50 100 150 200 250
Technology Node(nm)

Fig.18. Reported current gain cutoff Fig.19. Reported operating voltages for
frequencies for various technologies various technologies.

HEMT-based transistors fabricated using III-V substrates are used in millimeter

wave frequencies. The high electron mobility of GaAs and InP increases the device
operation beyond 300 GHz microwave region, as shown by Fig.18. However, the
smaller thermal conductivity of GaAs and InP compared with Si causes increased
substrate heating, leading to device exhaustion. Hence, these devices are suitable for
 An Overview of RF Power Amplifier Techniques and Effect 271

operation in low power levels as evident from Fig.19. GaN-HEMT can produce five
times more power compared with GaAs and InP based PAs [62] because of its high
thermal conductivity and high break down voltage and this is evident from the
reported operating voltage as shown in Fig.19.
HBT-based transistors utilize the high gain and low noise advantages of bipolar
transistors. The integration of group III-V materials increases the cutoff of frequency
of HBTs. As seen in Fig.18, the highest reported cut-off frequency of 1 THz is
attained by InP-HBT at the 130 nm node. This trend of the InP-HBT shows that when
the device is further scaled down then its operation can extend into terahertz regime.
Reported works in Fig.18 shows that SiGe-HBT is widely used in lower mmW
frequencies while InP-HBT occupies the higher mmW frequencies. For higher power
requirements such as airborne radar, ship radar and military applications, GaN-HEMT
is the best candidate at lower mmW frequencies while InP-HBT is well suited for high
frequencies above 300 GHz. For applications of moderate power requirement such as
wireless base station PA and satellite transmitter, GaAs-HEMT and SiGe-HBT are
suitable candidates.
The increased gate-leakage and the variation of threshold voltage have become a
barrier for further scaling of the planar CMOS transistor [63]. Multigate FinFET
technology overcomes this problem by providing better control of gate leakage and
improved performance. Even though FinFET technology has been developed over a
decade, most of the intended applications are in the digital systems, hence it is not
included in this review.

VII. CONCLUSION
In this paper, the different topologies of power amplifiers have been studied and their
theoretical performance compared. Four different architectures to improve the
linearity and efficiency of power amplifiers have been explained. In addition, specific
issues and challenges of each architecture have been discussed. The promising
benefits of EER and ET techniques are generating a lot of interests. The bandwidth of
EER PA is constrained by the supply modulator and hence greater challenge is faced
by wideband applications. Also EER technique requires more accurate time alignment
for achieving high efficiency. Whereas, the ET PA is quite tolerant for time mismatch
and also generates less distortion compared with EER PA. In view of the complexity
and the size, outphasing and Doherty are appropriate for base station application; EER
and ET are suitable for wireless hand set applications.
The scaling effect of transistors was discussed. The geometry scaling of silicon-
based CMOS results in increased frequency of operation at the cost of reduced output
power. Hence CMOS based PA is best suited for low power wireless devices
operating at lower frequency band such as GSM, WiMax and LTE. The properties of
wide bandgap semiconductor materials were summarized and discussed. Wide
bandgap semiconductors could meet the demand of high frequency and high power
requirements of PAs especially for military and radar applications. GaN-HEMT is a
promising candidate for PAs at the lower mmW range while InP-HBT demonstrates
good power performance at higher mmW frequencies. The moderate cutoff frequency
272 Veeraiyah Thangasamy et al

and better power handling capabilities of SiGe HBT could fulfil the requirement of
PAs for wireless base station transmitter and WLAN.

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