DLP Projector: Service Manual

DLP PROJECTOR
SERVICE MANUAL
MODEL：PB6100 / PB6200
CAUTION
BEFORE SERVICING THE PROJECTOR,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
1
Index
1. Safety Precautions -------------------------------- 3
2. Engineering Specification---------------------- 4
3. Spare Parts List ---------------------------------- 32
4. Block Diagram ------------------------------------ 36
5. Packing Description ---------------------------- 44
6. Factory OSD Operation ------------------------ 50
7. Firmware upgrade procedure --------------- 57
8. RS232 Communication Protocol ----------- 61
9. Trouble Shooting Guide ----------------------- 73
10.CUSTOMER ACCEPTANCE CRITERIA ---- 78
11. Schematics ---------------------------------------- 96
2
1. Safety Precautions
3
2. Engineering Specification
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3. Spare Parts List
Model : PB6100
Item Component Description Type
1 42.J8618.001 U/C PC+ABS PB6100 R
2 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2
3 54.J8612.001 BALLAST PHG201G16 PB6100 R
4 60.J8605.001 ASSY Lower Case PB6100 R
5 23.10102.001 BLOWER 12V 50*50*20MM ADDA R
6 60.J8617.001 ASSY LAMPBOX PB6100 R
7 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R
8 60.J8604.001 ASSY R/C PB6100 R
9 55.J8608.001 PCBA REAR IR BD PB6100 2
10 65.J8602.001 ASSY AC INLET+THERM SW PB6100 R
11 55.J5019.001 PCBA THERMAL BD DX850 2
12 55.J5020.001 PCBA EMI BD DX850 2
13 55.J8601.001 PCBA MAIN BD PB6100 2
14 60.J8607.001 ASSY DOOR PB6100 R
15 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI 2
16 65.J8603.001 CW DIA44DEG110 PB6100 PRODISC R
18 55.J8623.001 PCBA CHIP BD PB6100 2
19 65.J7602.001 PL ZOOM PB7200 ASIA R
20 71.08060.000 IC DMD 0.6SVGA 8060-624C 12DDR R
32
Model : PB6100
21 31.J8601.001 BADGE AL PLATE PB6100 R
22 60.J1334.001 ASSY CAP LENS SL700X R
23 60.J8603.001 ASSY F/C PB6100 R
24 55.J8611.001 PCBA PFC BD PB6100 2
25 55.J8613.001 PCBA FAN BD PB6100 2
26 65.J5003.001 FOOT ADJ DX850 R
27 44.J0502.005 CTN 415*325*255 PB6100/BENQ VI R
28 47.J8605.001 CUSHION FRONT EPE PB6100 R
29 47.J8606.001 CUSHION REAR EPE PB6100 PB6100 R
30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R
31 50.J0508.503 SIGNAL/C 15/15P 20276 1800MM R
32 50.J1303.501 CABLE RCA Y/Y 1600MM BLK R
33 56.26J86.001 REMOTE CR14AI PB6100 R
34 42.20019.002 BAG PE 250*350 LD FP741/NEC R
35 46.00003.012 CARD WARRANTY 7254E R
36 49.J8601.001 MANUAL USER PB6100/ PB6200 R
37 53.J8601.001 CD MANUAL USER PB6100/ PB6200 R
38 60.J8618.CG1 ASSY Service LAMP 200W/U PB6100 0
39 60.J8621.001 ASSY S2+ EGN 12D PB6100 0
33
Model : PB6200
1 55.J8501.001 PCBA MAIN BD PB6200 2
2 42.J8618.001 U/C PC+ABS PB6100 R
3 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2
4 54.J8612.001 BALLAST PHG201G16 PB6100 R
5 55.J5020.001 PCBA EMI BD DX850 2
6 60.J8605.001 ASSY L/C PB6100 R
7 55.J8608.001 PCBA REAR IR BD PB6100 2
8 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R
9 60.J8607.001 ASSY DOOR PB6100 R
10 23.10102.001 BLOWER 12V 50*50*20MM ADDA R
11 60.J8617.001 ASSY LAMPBOX PB6100 R
12 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI 2
13 65.J8603.001 CW DIA44DEG110 PB6100 PRODISC R
14 60.J8621.001 ASSY S2+ EGN 12D PB6100 0
15 55.J8623.001 PCBA CHIP BD PB6100 2
16 71.08060.000 IC DMD 0.6SVGA 8060-624C 12DDR R
17 31.J7601.061 NAME PLATE AL PB6200 R
19 60.J1334.001 ASSY CAP LENS SL700X R
20 60.J8603.001 ASSY F/C PB6100 R
34
Model : PB6200
21 55.J8611.001 PCBA PFC BD PB6100 2
22 55.J8613.001 PCBA FAN BD PB6100 2
23 65.J5003.001 FOOT ADJ DX850 R
24 44.J7601.051 CTN AB PB6100/BENQ(VI) R
25 45.L2701.011 LBL CTN 120*100 BLUE FP559 R
26 47.J8605.001 CUSHION FRONT EPE PB6100 R
27 22.91007.001 SKT PLUG 2/3P W/G R
28 27.01818.000 CORD SVT#18*3C 10A125V 1830US R
29 44.J0501.011 CTN ASSY 350*240*48 7765P R
30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R
31 50.J0508.503 SIGNAL/C 15/15P 20276 1800MM R
32 50.J1303.501 CABLE RCA Y/Y 1600MM BLK R
33 56.26J86.001 REMOTE CR14AI PB6100 R
34 46.00003.012 CARD WARRANTY 7254E R
35 49.J8601.001 MANUAL USER PB6100/ PB6200 R
36 53.J8601.001 CD MANUAL USER PB6100/ PB6200 R
37 60.J8618.CG1 ASSY Service LAMP 200W/U PB6200 0
35
4. Block Diagram
PB6100 DMD projector being using the SGA DMD Engine made by BENQ, it included
front end circuitry that digitizes and scaling processes for the input analog VGA and TV signals. As
shown, in figure below the front end circuitry consists of :
1. Frond end Circuitry

1.1 Power supply module include PFC and DC/DC portion. DC/DC portion provide 12V, 5V and
3,3V for whole system.
12V Lamp Fan1
PFC
Lamp Power
IGNITOR
POWER SUPPLY
Module
AC IN
Lamp Fan Power Fan

DC to DC
EMI Filter
12V,5V,2.5V For System
1.2 Pixelworks scaler(PW166) with x86 CPU, OSD and SDRAM is used for system control. It control
whole system operation and with crucial role of this system.(Include fan speed, inter-lock SW,….)
1.3 A/D-decoder(AD9883) is used for decoding VGA analog signal to digital signal(RGB 888) which
provide 24 bit true color resolution. It can accept SOG(sync on green) and composite signal for PC
input. It also support YPbPr signal.
1.4 The video decoder that process TV video signal input. The TV video signal support both of
composite and S-video input and output YUV format to scaler processor. The basic block as
following.
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From Power Supply
Regulator(3.3v)
12V,5V,2.5V
EEPROM
(16K bit)
ThERMAL IC
SENSOR
Scaler (memory +cpu+osd)
RGB888 Signal To DMD Driver
Power(12V,5V,2.5V) To DMD Driver

D-Sub Input
AD Converter
Control Signal To DMD Driver

S-Video& RCA input
Video Decoder
2. DMD driver board that transfer PW166 scaler output RGB888 signal to DMD chip acceptable
signal for driving DMD mirror operation. The relate diagram as below:
RAMBUS CLOCK RAMBUS RDRAM

400mHz
GEN
Address
Data &
60MHz
CLK
100MHz
DATA , CONTROL,60MHz
DATA-GY(7:0),RV(7:0),BU(7:0)
DMD Chip
VSync,HSync,ACTDATA
Front End (0.6 SVGA
PIXEL CLOCK(CLKIN) DDP 1000 VBIAS SR16C DDR)
Circuit VRST DMD
MBRST
Resetz,Poweron (15:0)
Voltage VCC2 RESET DRIVER
LampLitz GEN
VCC2
CWY(1:3)
SENSOR BOARD CWindex Control Signal MOTOR DRIVER COLOR Drum
Color Wheel
CWCTR
37
3. Whole system block diagram is show as below:
Lamp Module Optical Device
PFC EMI Filter
Optical Engine Lamp On Power Board and Ballast
DMD Color Wheel DC/DC

Fan/BD Ballast
Control Signal
Data &
2.5V, 5V, 12V

Fan
Power & DMD Driver

DMD CHIP Board
Control Data
Control Signal
Sensor Signal RGB 888
Main
Color Wheel
Sensor Board Board
Color Wheel
Sensor
PW166 Scaler
Keypad
A/D Converter Video Decoder
IR Rear Board
Video Input
D-Sub Input
S-video Input
Overview
The Main Board of PB6100 is mainly composed of an ADC converter(AD9883) , a
ImageProcessor(PW166) , a EEPROM(24C16) and a flash memory (MBM29LV800B) .
The input signal is analog RGB format , which comes from the standard VGA D_SUB connector ,
the analog signal input to ADC converter , which output RGB digital data stream to Image Processor .
The Image Processor also known as “Scaler” , which indicate its main function , expand or
downsize the digital picture from ADC to a fixed size digital image output .
The CPU which control the whole system is embedded inside the Image Processor , there is also
a Real Time Operating System which incorporates with the CPU as hardware layer interface .
The EEPROM stores the system information such as brightness , contrast …which ensure the
system operates under the most user friendly circumstance .
The Flash memory stored the Software Program which control the system , the CPU will read the
Flash as its execution command .
38
Block Diagram
Below is the simple block diagram of PB6100 Main Board .
I2C
D_SUB
I2C EEPROM
Analg Flat Panel

Interface RGB888 signals
AD9883
Address
Control Signals Image Processor Flash

PW166
Data
I2C
S-Video
YUV 422
RCA
Video Decoder
SAA7118
Control Signals
Clock Clock
GEN signal
Control Signals
RGB 888
Signals
I2C
DMD Driver
As the diagram shown above , here is the function of every discrete blocks .
- D_SUB input
Analog RGB data input , the standard maximum analog input resolution is SXGA .There also
some interface signals from the VGA cable , they are
ADHSYNC – Providing the Horizontal Synchronization signal to AD9883.
ADVSYNC - Providing the Vertical Synchronization signal AD9883.
DDC interface – Providing Digital Display Channel , which include VCC(Pin9) ,
SCL(Pin15) , SDA(Pin12) .
- Analog Flat Panel Interface (ADC Converter) , AD9883

The ADC converter digitizes the input analog RGB data signal from D_SUB and output the
digital data streams to Image Processor .
The normal voltage level of analog RGB input signals is about 0.7V , while the ADC digital
signal output to Image Processor is LVTTL level , about 3.3V.
The ADC , AD9883 could supports up to pixel rate at about 140MHZ , which is about SXGA
75HZ analog input signal .
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There are some other interface signals related to AD9883
SOGIN – Sync On Green input from Image Processor , the signal enable the PB6100 support
the very special VGA input signal .
GCOAST – Input signal from Image Processor , the signal enable the PB6100 support the
Machintosh analog input format .
GCLK – Output to Image Processor as Pixel Clock , providing the reference clock for Image
Processor .
GHS – Providing the Horizontal Synchronization signal to Image Processor .
GVS - Providing the Vertical Synchronization signal to Image Processor .
GRE,GGE,GBE – Digital data stream to Image Processor which is higher than SXGA
75HZ .
. Image Processor (PW166)

The most important IC is the image Processor , here below list its main function
- Supporting input digital data stream up to UVGA and output digital data up to SXGA
- Two input port , which are Graphic port ( VGA format ) and Video port ( video decoder format ) .
- Frame rate conversion , the output frame rate is independent from the input frame rate and
the most important feature of the Image Processor is memory inside , there is no need
of external memory for frame rate convertion .
- Up and Down scaling of different input resolution , ensure the same output image size .
- Providing Bitmap OSD picture , which if more fancy than normal OSD chip .
- On chip Microprocessor
The Image Processor is a highly integrated circuit , it include MCU , Scaler , Memory , OSD . This
will increase the stability of the system .
There is some control signals list below
DCLK – pixel clock output to DMD driver BD , provided as a reference clock for DMD driver
DVS – Vertical synchronization signal output to DMD BD , provided as Vertical reference signal
for DMD driver .
DHS – Horizontal synchronization signal output to DMD BD , provided as Horizontal reference
signal for DMD driver .
DEN – Data enable signal output to DMD BD , provided as a valid data indicator signal for
DMD driver .
VCLK – V-port pixel clock .
VPEN – V-port data enable .
VVS – V-port Vertical Synchronization .
VHS – V-port Horizontal Synchronization .
VFILED – V-port Even/Odd frame indicator .
RESETZ – Output to DMD driver BD as RESETZ signal for DMD normal operation .
ABNORMAL – Input to CPU for indicating abnormal condition , if the CPU detects an
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abnormal status , it will disable lamp ignition .
POWERON – Output to power to enable the other power source into normal working situation .
LAMPLIT – Input signal as an indicator that the Lamp is ON or OFF
LED1, LED2 – Output to enable the LED ON or OFF .
IRRCVR0 – System IR input to CPU as remote control signals .
MCKEXT – Memory clock to CPU .
DCKEXT – Data clock to for Scaling .
I2C_SDA , I2C_SCL – I2C format data transfer line .
. EEPROM
Store the system information for user friendly .
. Flash Memory
System software was stored in this chip , the memory size is 8M bits
. DDP1000
The DDP1000 transfer signal from PW166 to DMD for driving DMD mirror operation.
. Direct Rambus Memory

The DDP1000 utilizes a high speed Direct Rambus Memory. To support the RDRAM a
Direct Rambus clock generator CDCR83 is utilized. It can transfer input clock from 50MHz
to 400MHz.
IR Receiver schematic:
The IS1U621 is miniaturized receivers for infrared remote control systems. PIN diode and
pre-amplifier are assembled on lead frame, the epoxy package is designed as IR filter. The
demodulated output signal can directly be decoded by a microprocessor. The main benefit is the
reliable function even in disturbed ambient and the protection against uncontrolled output pulses.
Electronic System Protection for abnormal state:

The circuit of electronic system protection for abnormal state is used for the hardware light off and
power off in abnormal state of thermal and safety issues. If the protection function is active then the
software system will detect the abnormal signal.
41
Sensor BD:
The Sensor BD provides the color wheel index signal to DMD BD. The CWINDEX shall indicate the
beginning of the red light on the DMD device. The phase of the display data on the DMD based on the
CWINDEX signal. It can be configured to delay the CWINDEX for electronic alignment of the color
wheel. The timing of CWINDEX and the delayed CWINDEX is shown in Figure 1.
CWINDEX
DELAYED
CWINDEX
DMD COLOR Red
FIGURE 1
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PB6100 Lamp on Sequence
Signal Voltage Change Description
POWERON LowÆHigh 1. This signal should go from low to high after all
the DC supplies are within spec. Then RESETZ
can go high.
2. After the power key pressed 3 second
continuously, the POWERON signal will
activate.
RESETZ LowÆHigh DMD is working, when the DMD reset.
LAMPEN LowÆHigh Lamp lights up.

LAMPLIT LowÆHigh Indicate ”Lamp on”.
PB6100 Normal Lamp off Sequence

Signal Voltage Change Description
RESETZ HighÆLow DMD is off.
LAMPEN HighÆLow Lamp is off.
LAMPLIT HighÆLow Indicate “lamp off“.
POWERON HighÆLow Power down the system, but the peripherals of the
CPU still power on.
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5. Packing Description
44
45
46
47
48
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6. Factory Menu
1. How to enter factory menu:
I. Hold press "UP" button until the "Lamp hours info." OSD display on
bottom-right of screen (Fig-1)
(Fig-1) Lamp Hours Info
II. Press keypad <Power> and <Blank> key simultaneously again, then enter
Factory menu.
50
2. Factory layer:
I. DMD layer (Fig-3):
(Fig-3) DMD layer
1. CW delay: Adjust color wheel delay.(Note this value before upgrade software)
2. White peak: Adjust DMD white peak.

In PC mode default value set 10, in Video mode is 0.
Software auto set this value as source find.
3. DLP Brightness: Adjust DLP Brightness.

Default setting is 36.Do not change this value.
4. DLP Contrast: Adjust DLP Contrast.

Default setting is 30.Do not change this value.
5. Burn-In Hour: set how many hours to burn-in.

Projector will enter burn-in mode on next selection.
6. Burn-In: After you set burn-in hours, set this selection to “On” and system will
enter going to burn-in immediately.
Projector will run color change (Red, Green, Blue, Black, White) on screen.
System will auto turn off after burn-in hour count down to 0 and burn-in
complete.
(You can also cancel burn-in sequence by set this selection to “Off”).
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II. ADC layer (Fig-4): (only available when input source is analog RGB)
(Fig-4) ADC layer

1. ADC Brightness: ADC brightness auto calibration black.
2. ADC Contrast: ADC contrast auto calibration white.
3. ADC Offset RGB: value to tell you calibrate result.
4. ADC Gain RGB: value to tell you calibrate result.
5. Fac Brightness: adjust default brightness value in source PC.
6. Fac Contrast: adjust default contrast value in source PC.
III. Color layer (Fig-5):
(Fig-5) Color layer
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1. PbPr: enter PbPr color control Layer.
When Source is YPbPr (Never Change these setting)

(Note these values Before Upgrade Software)
PbPr G Offset : combine with user OSD brightness in YPbPr
PbPr G Gain: combine with user OSD contrast in YPbPr
PbPr R Offset: offset of color red
PbPr G Offset: offset of color green
PbPr R Gain: saturation R
PbPr B Gain: saturation B
2. 6500,11500 R,G,B: 6500K/11500k submenu
(Never Change these setting)

6500 R :gain of color red while color temp is 6500
6500 G :gain of color green while color temp is 6500
6500 B :gain of color blue while color temp is 6500
6500 R :gain of color red while color temp is 11500
11500 G :gain of color green while color temp is 11500
53
11500 B :gain of color blue while color temp is 11500
3. PC 9300 and Video 9300: 9300K submenu.
(Never Change these setting)

PC 9300 R :gain of color red while PC color temp is 9300
PC 9300 G :gain of color green while PC color temp is 9300
PC9300 B :gain of color blue while PC color temp is 9300
Video 9300 R :gain of color red while Video color temp is 9300
Video 9300 G :gain of color green while Video color temp is 9300
Video 9300 B :gain of color blue while Video color temp is 9300
IV. Optic layer (Fig-5):
(Fig-5) Optic layer

1. Test Pattern: system auto produce pattern for engineer test.
2. Spoke light: unit display full white.
3. Curtain Red: unit display full color red.
4. Curtain Green: unit display full color green.
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5. Curtain Blue: unit display full color blue.
V. Lamp layer (Fig-6):
(Fig-6) Lamp layer

1. Interpolation: De-interlace Mode
2. Filter: system auto select Filter.
3. Lamp Hour: value to tell you lamp usage hours.
4. Usage Hour: value to tell you unit usage hours.
5. Fac Lamp Hours: Record all of the amp usage hours
6. Data Reset: Reset all data to default include factory assign value.
Never try to reset all data.
VI. Others layer (Fig-7):
(Fig-7) YPbPr layer

1. Gamma index: system auto select DLP gamma index
2. Gray value: adjust here to check DMD fail pixel.
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3. Blue value: adjust here to check DMD fail pixel.
4. Scaling: tell you what scaling mode is using now.
5. Pc/PbPr Mode: index of input timing
6. RS232: Enable / Disable RS232 control
VII. FAN Layer.
T1-DMD: DMD sensor temperature

T2-Lamp: Lamp sensor temperature
T3-Blwr: Blower sensor temperature
F1-Lamp:Lamp fan speed in RPM
F2-Blst: Blaster fan speed in RPM
F3-Blwr : Blower fan speed in RPM
Manual Fan Speed: Change fan speed by manual.
SOG Threshold : Change SOG threshold level of AD
More Options: Change to Fac7 submenu
(Fac7 Submenu)
( This menu only for control testing)
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7. Firmware upgrade procedure
PB6100/PB6100 Download Procedure
Hardware required
1. D-sub download cable (full ping D-SUB P/N : 50.J2402.201)
2. Download board ( P/N : 55.J1316.001 )
3. PS2 Download cable from download BD to PC ( P/N : 50.J0510.5D1 )
4. (Cable/RS232D MD8PM/DS9PF 1800MM)
5. Adaptor for Download BD ( DC12 V)
6. DVD player with YPbPr (Progressive) output
7. PC timing/pattern generator
8. Personal computer or laptop computer
Software required
1. FlashUpgrader.exe (or FlashUpgraderNT.exe if you’re using Windows NT®)
2. pwSDK.inf
3. romcode.hex
4. configdata.hex
5. gui.hex
6. flasher.hex
Download procedure
1. Record CW delay value in factory page 1 on the unit to be upgraded.
Fig. 1
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2. Record all Color Temperature values in factory page 3.
Fig. 2
3. Power down the projector and turn the power switch off after cooling.
4. Setup the download board as Fig. 3
PS2 Download cable to PC

P/N : 50.J0510.5D1
Download BD
P/N : 55.J1316.001
D-Sub connector to Projector

P/N : 50.J2402.201
Power supply DC 12 V
Fig. 3
5. Connect the D-Sub to PC input of Projector.
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6. Run FlashUpgrader.exe and open the file pwSDK.inf. You can browse to locate it. Select the
correct COM port and use 115200 as the BAUD rate.(as Fig. 4)
Fig. 4
7. Press the “Flash” button , and then turn on the power switch. (as Fig. 5)
Fig. 5
8. Now the progress bar in the FlashUpgrader should be running.
9. Download is complete ,Pls turn off power switch , and turn ON power switch.
10. Power on projector and the factory settings should be restored.
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Calibration procedure
1. Use any video pattern generator to output XGA 60Hz PC timing with 32 grayscale pattern.
Enter the factory OSD page 2 and execute ADC Brightness and ADC Contrast.(as Fig. 6)
Fig. 6
2. Restore CW delay value and color temperature values.
Verification
Check the version number in the factory OSD page 1.(as Fig. 1)
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8. RS232 Communication Protocol / Codes
External Communication Protocol
External communication protocol include two parts：A. setup connecting, B. send command.
BenQ default Serial Port :

Baud Rate: 19200
Parity: none
Data bits: 8
Stop bits: 1
Flow Control:none
A. Setup Connecting
A typical Packet transaction session is shown in Figure 1
PC BenQ Projector
Host System Target
System
a
Packet to Target =>
<= ACK b
<= Packet to Host
c
Packet to Target =>
<= ACK d
<= Packet to Host
e Packet to Target =>

Figure 1
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a. 1st Packet to Target (BenQ PB6XXX) structure like as below (Table 1)
Byte0 0xBE Magic

Byte1 0xEF Number
Byte2 0x01 Packet Type
Packet
Byte3 0x05 Packet size (Low)
Header
Byte4 0x00 Packet size (High)
Byte5 0xD1 CRC (Low)
Byte6 0xFA CRC (High)
Byte7 0x01 System Info Type
Byte8 0x02
Packet Version Number
Byte9 0x00
Payload
Byte10 0x00 Object ID
Byte11 0x00 Level
Table 1
b. The Ack of Packet to Host (PC) (Table 2)
Ack Byte0 0x1E PAK

Byte1 0xBE Magic
Byte2 0xEF Number
Packet
Header
Byte6 0xD1 CRC (Low)
Byte7 0xFA CRC (High)
Byte9 0x02
Byte10 0x00
Payload
Byte12 0x00 Level
Table 2
PAK means that PC will follow the received Packet data

c. Packet same as 1st Packet (Table 1)
d. Same as Ack (Table 2)
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e. Packet to Target (BenQ PB6XXX) structure (Table 3)
Byte0 0xBE Magic
Byte1 0xEF Number
Packet
Header
Byte5 0xA9 CRC (Low)
Byte6 0xC6 CRC (High)
Byte8 0x00
Byte9 0x00
Payload
Byte11 0x00 Level
Table 3
B. Send Command
1. Introduction
Command packets consist of “Header” and “Payload”. The Packet Header is consistent for all packets. The Packet
Payload type and content varies based on the type of packet sent. The entire packet size is variable, being the sum of the
fixed-size Packet Header and variable-sized Packet Payload.
Packet Header (fixed size) Packet Payload (variable size)
Figure 2 Packet Format
Packet Header Format

All Packets use the same Packet Header format illustrated Figure 3.
Byte 0 1 2 3 4 5 6
Magic Number Type Packet Payload Size CRC
0xBE 0xEF type size_lo size_hi crc_lo crc_hi
Figure 3 Packet Format
63
The Packet Header size is fixed at seven bytes (Intel byte ordering is used). The following code fragments are taken
from these source files
The Packet Header definition is shown below:
typedef struct
{
BYTE ePacketType; // type of the payload
WORD nPacketSize; // size of the payload
WORD nCRCPacket; // CRC for the entire packet
} PACKET_HEADER;
Magic Number
The Magic Number is a fixed value that is used to insure packet alignment if there are partial packets received or
bytes lost. The Magic Number is a WORD in length (2 bytes). The Magic Number value is 0xEFBE. Because Intel
byte ordering is used, the ls-byte of the word is sent first (byte0 = 0xBE), then the ms-byte (byte1 = 0xEF).
Packet Type
The Packet Type (ePacketType) is a BYTE in length number that defines the type of data in the packet. The following
entries are valid packet typess:
Table 4 Packet Type Name Packet Type Description

Packet Number
Types pt_INVALID 0 Invalid Packet Type
RESERVED 1 RESERVED
pt_EVENT 2 Host can send any event defined in BenQ PB6XXX

software.
pt_OPERATION 3 Host can send any operation defined in BenQ PB6XXX
software.
Packet Payload Size
The Packet Payload Size (nPacketSize) is a BYTE that defines the size of the Payload portion of the packet. If the
packet contains only header information, this is zero. Therefore, the total byte count of any packet = nPacketSize plus
7 (since the Packet Header is seven bytes long).
Packet Checksum (CRC)

Each packet is CRC’ed using the tables later in this document. This number is the CRC value for the complete packet
including the Packet Header and Packet Payload. The CRC is calculated with the nCRCPacket value initialized to
zero.
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2. Packet Payload Definition
Event Packet Type

The Event packet is used by the host system to send virtual events (such as Zoom, Source, Auto Adjust, etc.) to the
target system. Packet payload size is 6 bytes.
Byte Field Name Field Value Description
0-1 Virtual Event Virtual Event ID as defined through

Configurator
2-5 Parameter Parameter that can be associated with the
event.
. Table 5 Event Packet Type Format
The source code definition of the Message packet data structure is:
typedef struct
WORD eEvent;
DWORD dwParam;
} EVENT_MESSAGE;
This lets you send any event defined in Configurator to the system including all remote, IR, or special events
Operation Packet Type

The Operation packet is used by the host system to execute operations (such as Brightness, Contrast, Image
Position, etc) in the target system. The Operation packet payload size is 25 bytes.
Byte Field Name Field Description

Value
0 Operation Type 1 OPERATION_SET
2 OPERATION_GET
3 OPERATION_INCREMENT
4 OPERATION_DECREMENT
5 OPERATION_EXECUTE
1-2 Operation Operation ID as defined in Configurator
3-4 Is Avail Operation is available
5-8 Operation Target Used for Operation with Targets. These Targets are
defined in configurator. For instance,
op_BRIGHTNESS has a Target of either MAIN or
PIP window..
9-12 Operation Value Value of the Set on a set or the Value of the
Get on a Return.
65
13-16 Operation Value of The Minimum Value of the set for operation
minimum. command.
17-20 Operation Value of The Maximum Value of the set for operation
maximum command.
21-24 Operation Value of The Increment Value of the set for operation
Increment command.
Table 6 Operation Packet Payload Format
The source code definition of the Operation packet data structure is:
typedef struct
eOPERATION_TYPE eOpType;
WORD eOperation;
WORD bisAvail;
DWORD dwTarget;
DWORD dwValue;
DWORD lmMin;
DWORD lmMax;
DWORD lmInc;
} OPERATION_MESSAGE;
This lets the user directly perform logical operations such as “Set Contrast = 80”.
66
3. Send Command
PC BenQ PB6XXX
Host System Target System
a
Packet to Target =>
<= ACK b
Figure 4
a. The structure of Command (EX. input select) send to Target (BenQ PB6XXX) like as below
(Table 7)
Byte0 0xBE Magic
Byte1 0xEF Number
Packet
Header
Byte5 0x80 CRC (Low)
Byte6 0xC7 CRC (High)
Byte7 0xC9
Virtual Event ID
Byte8 0x00
Packet Byte9 0x00
Payload Byte10 0x00
Parameter
Byte11 0x00
Byte12 0x00
Table 7
b. Target return to Host (PC) Ack like as below Table 8

Ack Byte0 0x06 ACK
Table 8
67
C. Serial Communication Cable and Parameters
For external serial communication from a computer to BenQ projector, BenQ recommends
manfactures use RS-232 communations over a straight through serial cable a 9 pin female D-sub9
connector.
The standard D-sub9 connector on the computer is a male connector, and BenQ projector, too. The
wiring between the computer and BenQ projector is a straight through cable. A 9 pin female to 9 pin
female stright through cable is a very standard part and readily available in many lengths.
Female D-sub9 pinout numbering and definitions on both terminal :
Pin number Name

2 Transmit
3 Receive
5 Ground
PW Serial uses the following default serial port settings:

. Baud Rate: 19200
. Parity: none
. Data bits: 8
. Stop bits: 1
. Flow Control: none
68
D. Software Flow Chart
Build serial communication port

Baud rate: 19200
Parity: none
Data bits: 8
Stop bits: 1
Transmit 1st Packet (see Table 1)
Delay 100ms
Transmit 2nd Packet (see Table1)
Delay 100ms
Transmit 3rd Packet (see Table3)
Transmit Command (see Table7)
69
Command List
Event Packet Type command:
Command Packet Header (7 bytes) Packet Payload (6 bytes)
Power BE EF 02 06 00 13 CE AA 00 00 00 00 00
Auto BE EF 02 06 00 F7 C8 8E 00 00 00 00 00
Input select BE EF 02 06 00 C4 C8 8D 00 00 00 00 00
Menu BE EF 02 06 00 26 C9 8F 00 00 00 00 00
Exit BE EF 02 06 00 FE CA 97 00 00 00 00 00
Zoom + BE EF 02 06 00 AD CD B4 00 00 00 00 00
Zoom - BE EF 02 06 00 7C CC B5 00 00 00 00 00
PIP Source BE EF 02 06 00 37 C6 CE 00 00 00 00 00
Freeze BE EF 02 06 00 46 CE AF 00 00 00 00 00
Ratio BE EF 02 06 00 04 C6 CD 00 00 00 00 00
Force PC BE EF 02 06 00 AE C6 C7 00 00 00 00 00
Force Video BE EF 02 06 00 51 C6 C8 00 00 00 00 00
Force S-Video BE EF 02 06 00 80 C7 C9 00 00 00 00 00
Force YPbPr BE EF 02 06 00 B3 C7 CA 00 00 00 00 00
RS232 Power ON BE EF 02 06 00 3E C4 D7 00 00 00 00 00
RS232 Power OFF BE EF 02 06 00 C1 C4 D8 00 00 00 00 00
Blank BE EF 02 06 00 1A CC B3 00 00 00 00 00
Operation Packet Type command
PC Picture Controls
Brightness + BE EF 03 19 00 44 A0 03 C7 02 CC CC 00 00 00 00 CC×16
Brightness - BE EF 03 19 00 2A 0A 04 C7 02 CC CC 00 00 00 00 CC×16
Contrast + BE EF 03 19 00 2E 19 03 C5 02 CC CC 00 00 00 00 CC×16
Contrast - BE EF 03 19 00 40 B3 04 C5 02 CC CC 00 00 00 00 CC×16
YPbPr Picture Controls

Brightness + BE EF 03 19 00 7B 14 03 D9 02 CC CC FF FF FF FF CC×16
Brightness - BE EF 03 19 00 15 BE 04 D9 02 CC CC FF FF FF FF CC×16
Contrast + BE EF 03 19 00 FA 6A 03 F1 02 CC CC FF FF FF FF CC×16
Contrast - BE EF 03 19 00 94 C0 04 F1 02 CC CC FF FF FF FF CC×16
70
S-Video / Composite Video Picture Controls

Brightness + BE EF 03 19 00 E9 18 03 35 02 CC CC 00 00 00 00 CC x16
Brightness - BE EF 03 19 00 87 B2 04 35 02 CC CC 00 00 00 00 CC x16
Contrast + BE EF 03 19 00 16 FC 03 36 02 CC CC 00 00 00 00 CC x16
Contrast - BE EF 03 19 00 78 56 04 36 02 CC CC 00 00 00 00 CC x16
Color + BE EF 03 19 00 83 A1 03 37 02 CC CC 00 00 00 00 CC X16
Color - BE EF 03 19 00 ED 0B 04 37 02 CC CC 00 00 00 00 CC x16
Tint + BE EF 03 19 00 00 0F 03 4A 02 CC CC 00 00 00 00 CC x16
Tint - BE EF 03 19 00 6E A5 04 4A 02 CC CC 00 00 00 00 CC x16
Sharpness + BE EF 03 19 00 43 D0 03 38 02 CC CC 00 00 00 00 CC x16
Sharpness - BE EF 03 19 00 2D 74 04 38 02 CC CC 00 00 00 00 CC x16
Misc Controls

Color Temp –50 (0) BE EF 03 19 00 69 49 01 ED 02 CC CC 00 00 00 00 CE FF FF FF
CC CC CC CC CC CC CC CC CC CC CC CC
0 (10) BE EF 03 19 00 1C 89 01 ED 02 CC CC 00 00 00 00 00 00 00 00
50 (20) BE EF 03 19 00 69 1C 01 ED 02 CC CC 00 00 00 00 32 00 00 00
PIP Controls
PIP Size
Off BE EF 03 19 00 15 02 01 8C 02 CC CC 01 00 00 00 03 00 00 00
Small BE EF 03 19 00 E4 42 01 8C 02 CC CC 01 00 00 00 00 00 00 00
Medium BE EF 03 19 00 74 83 01 8C 02 CC CC 01 00 00 00 01 00 00 00
Large BE EF 03 19 00 85 C3 01 8C 02 CC CC 01 00 00 00 02 00 00 00
PIP Position
Upper-Left BE EF 03 19 00 1D 66 01 43 02 CC CC 01 00 00 00 00 00 00 00
Upper-Center BE EF 03 19 00 8D A7 01 43 02 CC CC 01 00 00 00 01 00 00 00
Upper-right BE EF 03 19 00 7C E7 01 43 02 CC CC 01 00 00 00 02 00 00 00
71
Mid-Left BE EF 03 19 00 EC 26 01 43 02 CC CC 01 00 00 00 03 00 00 00
Mid-Center BE EF 03 19 00 DE 64 01 43 02 CC CC 01 00 00 00 04 00 00 00
Mid-Right BE EF 03 19 00 4E A5 01 43 02 CC CC 01 00 00 00 05 00 00 00
Lower-Left BE EF 03 19 00 BF E5 01 43 02 CC CC 01 00 00 00 06 00 00 00
Lower-Center BE EF 03 19 00 2F 24 01 43 02 CC CC 01 00 00 00 07 00 00 00
Lower-Right BE EF 03 19 00 DB 61 01 43 02 CC CC 01 00 00 00 08 00 00 00
PIP Source
S-Video BE EF 03 19 00 E8 36 01 DA 02 CC CC 01 00 00 00 03 00 00 00
Video BE EF 03 19 00 DA 74 01 DA 02 CC CC 01 00 00 00 04 00 00 00
PIP Brightness BE EF 03 19 00 FE 0B 01 35 02 CC CC 01 00 00 00 CE FF FF FF
-50 (48) CC CC CC CC CC CC CC CC CC CC CC CC
0 (126) BE EF 03 19 00 8B CB 01 35 02 CC CC 01 00 00 00 00 00 00 00
50 (204) BE EF 03 19 00 FE 5E 01 35 02 CC CC 01 00 00 00 32 00 00 00
PIP Contrast BE EF 03 19 00 01 EF 01 36 02 CC CC 01 00 00 00 CE FF FF FF
-50 (58) CC CC CC CC CC CC CC CC CC CC CC CC
0 (131) BE EF 03 19 00 74 2F 01 36 02 CC CC 01 00 00 00 00 00 00 00
50 (204) BE EF 03 19 00 01 BA 01 36 02 CC CC 01 00 00 00 32 00 00 00
PIP Color BE EF 03 19 00 94 B2 01 37 02 CC CC 01 00 00 00 CE FF FF FF
–50 (129) CC CC CC CC CC CC CC CC CC CC CC CC
0 (157) BE EF 03 19 00 E1 72 01 37 02 CC CC 01 00 00 00 00 00 00 00
-50 (185) BE EF 03 19 00 94 E7 01 37 02 CC CC 01 00 00 00 32 00 00 00
PIP Tint -50 (0) BE EF 03 19 00 17 1C 01 4A 02 CC CC 01 00 00 00 CE FF FF FF
0 (128) BE EF 03 19 00 62 DC 01 4A 02 CC CC 01 00 00 00 00 00 00 00
50 (255) BE EF 03 19 00 17 49 01 4A 02 CC CC 01 00 00 00 32 00 00 00
72
9. Trouble Shooting Guide
Optical Engine
No. Item Trouble Shooting Guide
1. Change lamp
1 Brightness 2. Check overfill size: If overfill too large, re-install SL and AL to
ensure correct position
1. If Uniformity is within 3% of spec: Change lamp
2. Check FM installation
2 Uniformity
3. Check overfill size: If overfill too small, re-install SL and AL
to ensure correct position
1. Clean DMD
3 FOFO Contrast
2. Clean PL
1. Clean PL
4 ANSI Contrast 2. Clean DMD
3. Change PL
5 Color Check CW 50% point. Replace CW if necessary
6 Color Uniformity Change CM
1. Readjust LP: Make sure the LP end is touching with
7 Blue Edge DMD_HSG Datum
2. Check LP: If LP is crushed, replace with new LP
1. re-install SL and AL to ensure correct position
8 Blue/Purple Border
2. Check FM installation
1. Change Projection Lens
9 Focus
2. Put shim metal between upper side of DMD and DMD datum
10 Dust Clean DMD
1. Check connector between FPC and M/B
2. Re-install DMD with FPC
Horizontal/Vertical
11 3. Check if any pin of C-Spring is missing or damaged
Strips
4. Change new FPC/C-Spring
5. Change new DMD
12 Pixel Fail Change new DMD
73
Main board
1.chk voltage input from F/B : 2.5V,5V,12V
2.chk oscillator Y2,Y3 output frequency (16.257MHz,10MHz)
3.chk MCLK(U24-5,130MHz) and DCLK(U25-5,40MHz)
System no work 4.chk U17 whether S/W inside or bad soldering
5.change U22(bad soldering)
Yes 6.chk Reset IC (U14)
No 7.chk Abnorm al signal
8.chk Resetz(RN25-5),Poweron(RN25-6) ,DVS(RN18-3),DEN(RN18-
1),DHS(RN18-2),DCLK(RN18-4)
No data
1.chk output from U15(RN6,RN7,RN8,RN9,RN10,RN11) [graphics input]
Yes 2.chk output from U13 (Via VUV[0:7}&VY{0:7]) [video input]
No 3.chk U22 and its peripherals (as above block)
No im age when graphics

is the current input 1.chk D_SUB cable and L9
2.chk GHS(UH2-4),GVS(UH702-4)
3.chk U15 voltage source U12(3.3V),UB16(3.3V)
Yes 4.chk U15 GHS(64),GVS(63),GFBK(65),G CLK(66)
No 5.chk U15 soldering
6.change U15
No im age when video

is the current input 1.chk U13 voltage source U12,UA6
4.chk Y1 output frequency(24.576MHz)
Yes 5.chk U13 output signals to U22
6.chk U13 soldering
No 7.chagne U13
Unable to download 1.change U17

Yes
2.chk U711 enable pins(1,4)
No
Yes 1.change U21

Unable to save
O SD setting
1.chk RN725-RN728 soldering

No 2.chk U27,U28
Yes
Keypad
m alfunction
No
74
DMD Driver
Start
Yes
1.chk J702,2.5V(4,,5,6),5V(3),12V(1)
Power Voltage No
2.chk bead L710-L714,L44
Yes
DDP 1000
function 1.chk clock frequency (unit:MHz)
No a.Y901(30)b.Y5(20) C.UY1(100)
C.Motor Controller(8.33)
Yes 2.chk ACTDATA,POWERON,RESETZ,CLKIN,HSYNC,
VSYNC,SYNCVALID from Front End
3.chk CW spinning frequency 120Hz , if wrong, chk
1.LAMPEN Signal to Ballast. MTRDATA , MTRCLK , MTRSELZ
2. 3.5s after LAMPLIT,DMD Become Active and Peripheral
Display an Image . No
Hardware
.
Yes
Image Color
No 1.chk CW spinning in cloclwise
2.chk CW tape position and width
3.chk cutrain displayed 220us after CW index
Yes 4.sequence color transition during CW spoke interval
Image Quality 1.Output from DAD1000 : VBIAS(22-25V),VRST(-26V),

No
VCC2(7.5V)
2.chk control signal of DMD chip from
U29(RN40,RN45)
3.chk data sequence from U29 to FPC(RN37~RN44)
Yes
4.chk JP2,JP3 soldering
Lamp On
1.chk CWINDEX
2.chk LAMPEN
No 3.chk LAMPLIT
75
Smaller boards
Fan control:
1.chk the voltage of Q F1 (5,6,7,8)
2.chk the fan voltage U502(2,15),U503(8)
FAN/BD No 3.check Y501(32.768kHz)
No 5V
1.Check Q 701 & therm al Breaker
Yes
LED dark
1.chk LED voltage from J1
Keypad
No 2.chk the m ounting direction of LEDs
function
No work
1.chk buttons contact to PCB
Yes
Rear Front IR
No 1.chk U1 voltage source(5V)
function
2.chk U1 output signal (always 5Vdc in regular tim e,no pulse voltage)
PFC BOARD
76
DC-DC BOARD
Appendix: Abbreviations
PWR Power supply module
M/B Main board
F/C Front End Circuit
D/B DMD Driver Circuit
FPC FPC transmission board
K/B Keypad board
R/B Rear IR board
CW Color wheel
S/W Software
S/B Sensor board
F/B Fan board
AL Aspherical Lens
SL Spherical Lens
FG Front Glass
LP Light Pipe
FM Fold Mirror
CM Concave Mirror
PL Projection Lens
77
10. CUSTOMER ACCEPTANCE CRITERIA
CONTENT
1.0 SCOPE
2.0 PURPOSE
3.0 APPLICATION
4.0 DEFINITION
5.0 CLASSIFICATION OF DEFECTS
6.0 CLASSIFICATION OF DEFECTIVES
7.0 INSPECTION STANDARD
8.0 GENERAL RULES
9.0 TEST CONDITIONS
10.0 TEST EQUIPMENTS
PART Ⅰ INSPECTION CRITERIA
1. PACKING, MARKING AND ACCESSORY

2. APPEARANCE ON VISIBLE PARTS
3. INSTALLATION
4. FUNCTION
5. SAFETY DEFECT CLASSES
78
1.0 SCOPE
This document establishes the general workmanship standards and
functional acceptance criteria for PROJECTOR produced by BENQ.
2.0 PURPOSE
The purpose of this publication is to define a procedure for inspection of
the PROJECTOR by means of a customer acceptance test, the method of
evaluation of defects and rules for specifying acceptance levels.
3.0 APPLICATION
The "Customer Acceptance Criteria" is applicable to the inspection of the

PROJECTOR, completely packed and ready for dispatch to customers.
Unless otherwise specified, the customer acceptance inspection should
be conducted at manufacturer's site.
4.0 DEFINITION
The "Customer Acceptance Criteria" is the document defining the

process of examining, testing or otherwise comparing the product with a
given set of specified technical, esthetic and workmanship requirements
leading to an evaluation of the "degree of fitness for use", including
possible personal injury or property damage for the use of the product.
5.0 CLASSIFICATION OF DEFECTS
The defects are grouped into the following classes:

5.1 Critical defect
A critical defect is a defect which judgment and experience indicate
that there is likely to result in hazardous or unsafe conditions for
individuals using product.
5.2 Major defect
A major defect is a defect, other than critical one, is likely to result in
failure, or to reduce materially the usability of the product for its
intended purpose.
5.3 Minor defect
A minor defect is a defect that is not likely to reduce materially the
usability of its intended purpose, or is a departure from established
standards having little bearing on the effective use of operation of
the product.
79
6.0 CLASSIFICATION OF DEFECTIVES
A defective is a product which contains one or more defects. The

defective will be classified into following classes:
6.1 Critical defective
A critical defective contains one or more critical defects and may
also contain major and/or minor defects.
6.2 Major defective
A major defective contains one or more major defects and may also
contain minor defects but contains no critical defect.
6.3 Minor defective
A minor defective contains one or more minor defects but contains
no critical and major defects.
7.0 INSPECTION STANDARD
Unless otherwise specified, the inspection standard will be defined by

MIL-STD-105E, NORMAL INSPECTION LEVEL Ⅱ, SINGLE SAMPLING PLAN.
7.1 Acceptance Quality Level
7.1.1 Critical Defect:

When a critical defect is found, this must be reported immediately
upon detection, the lot or batch shall be rejected and further
shipments shall be held up pending instructions from the
responsible person in relevant department.
7.1.2 Under normal sampling

Critical Defective : 0% AQL
Major Defective : 0.65% AQL
Minor Defective : 2.5% AQL
7.1.3 Under special sampling

Critical Defective : 0% AQL
Major Defective : 1.0% AQL
Minor Defective : 4.0% AQL
80
8.0 GENERAL RULES
8.1 The inspection must be carried out by trained inspectors who have good
knowledge about the product.
8.2 The inspection must be based upon the documents concerning the completely
assembled and packed product.
8.3 When more defects appear with the same unit only the most serious defect
have to be taken into account.
8.4 Defects found in accessory packed with the product such as Cable,
Connector, Manual, CD and the like, and being inspected as
a part of the complete product, must be included in the evaluation.
8.5 The evaluation must be within the limits of the product specification and, for
not specified characteristics, refer to the sample machine or the judgment of
BENQ QA Engineer. But any kind of proposals or judgments must be
reasonable and acceptable by both sides.
8.6 Faults must be able to be repeatedly demonstrated.
9.0 TEST CONDITIONS
Unless other prescription, the test conditions are as followings:
Nominal voltage : refer to operation manual

Environmental illumination variable from 400 to 700 lux
Temperature :
Operating : 0~ 35 ℃
Storage : -10~ 60 ℃
Humidity:
Operating : 10 ~ 90 % RH
Storage : 10 ~ 90 % RH
Altitude:
Operating : 0 ~ 6000 ft above sea
level,
81
10.0 TEST EQUIPMENTS
10.1 Pentium with 32MB of system memory , 64M RAM and above are
recommended.
10.2 Win98 or later Operation Environment
10.3 VGA or any Windows compatible display with a resolution of at

least 640x480 pixels, and set to high color or true color
mode.
10.4 Quantum card/Chroma & Test pattern files
10.5 Dark room
10.6 29 points optical measure equipment
10.7 Pattern generators
10.8 DVD player
10.9 Mouse
82
PART Ⅰ INSPECTION CRITERIA
■ Packing, marking and accessory
△ Inner packing material broken. minor

△ Carton damaged with hole over 1.5 cm in diameter. minor
△ Carton crashed with dent over 5 cm in diameter. minor
△ Printing of carton is illegible. minor
△ Broken packing bag minor
☆ Spec. label's serial number not the same as carton label's. Major
☆ Packing model not the same as carton. Major
☆ Marking missing/wrong. Major
☆ Accessory shortage/wrong. Major
☆ Projector missing(found none in carton). Major
☆ Label on box missing or damaged Major
☆ Strange objects in the box Major
■ Appearance on visible parts
△ Poor printing on panel sticker(segment broken, illegible). minor

△ Damage or deviation when viewed at a distance of 50 cm. minor
△ Cover/case is dirty(removable). minor
△ Cover/case exists black spot(irremovable). minor
△ Cover/case is scratched. (Note 1) minor
△ Spec Label reverse, rugged, illegible printing. minor
△ LED sink over 1 mm. minor
☆ Label/screws shortage or missing. Major
☆ Wrong logo of panel sticker. Major
☆ Wrong spec. label printing. Major
☆ Label on product wrong or missing Major
■ Installation
☆ Any accessory which are failed Major

to meet the installation purpose
83
■ Function
△ Abnormal sound during projection(from 50 cm). minor

☆ LED won’t light / No power / can't work. Major
☆ Other function test please refer to Note 2.
■ Safety defect class
☆ Any item which violates the approved safety standard. major

★ Electrical shock or smoke. Critical
Note 1 : Please refer to attachment 1.

Note 2 : Please refer to attachment 2.
Attachment 1 Scratch Acceptance
Any scratch which exceeds the maximum allowance is treated as a minor defect.
Black spot, Soil, Bubble inspective standard

2
Spec. (mm ) A side B side C side 備註
0.05 mm2 以下 Accept Accept Accept 1. A、B、C side defineted as
Black between 2 cm Diagram - A1
Soil 0.05 ~0.1mm2 4 5 6 2.. LOGO 周邊 2 cm 內不
Bubble between 5 cm 可有 0.05m ㎡以上之斑點
0.1~0 5m ㎡ 3 4 5 (0.05m ㎡以內斑點不計)
between 5cm
0.2~0.3mm2 2 3 4
between 10cm
PS : Any kind of defect not seen from 45 cm(18 inches)(It’s about an arm’s length) with
15 seconds should not be a reject.
Any scratch which exceeds the maximum allowance is treated as a minor defect.
Spec. (mm) A side B side C side Remake
Scratch W<0.1 L<1 1 2 3 1. The separation distance
Dent between defects must great
W<0.1 L<2 0 1 2
than 10mm.
W<0.1 L<3 0 0 1
84
Diagram - A1 Definition of Projector's sides
85
Attachment 2 Quality Specification of PB6100
Following item’s spec. will base on Engineering spec.

Item Spec Remarks
1. Brightness Minimum 1120 lumens major
2. Uniformity Minimum 50 % major
3. ANSI Contrast Ratio 150:1 major

4. FOFO contrast Ratio 700:1 major
5. Screen Size For Testing 60” at 2m major
6 .Focus Range 1.5~6m major
7. Keystone Distortion <1.0% major
8. Audible Noise Level Typical 34dBA at 25°C major

Maximum 35dBA at 25°C
9. Power Connector IEC - 06 major
10. Throw Ratio 47” ±5% Diagonal at 2m major
12. Power consumption Typical 285W / Standby <15W
13. Blue Border <2 lux with 40” (diagonal) image size
Purple Border <4 lux with 40” (diagonal) image size
14. Light Leakage In Active Area <1.5 lux within 47” (diagonal) image size
Light Leakage out of Active Area <5 lux between of 47” (diagonal) image size and 60”
(diagonal) area
15. IR Receiver , IR Receiver X 2 (Front, Rear)
16. Check the remote control function whether it is correct
17. Check the DVD image whether it is correct
86
18.Color Temprature
1.8.1 White .298±.040 .318±.040
1.8.2 Red .627±.040 .369±.040
1.8.3 Green .333±.040 .559±.040
1.8.4 Blue .137±.040 .061±.040
19. Focus
1.9.1 for PROT lens 1.Pattern:区 pattern
2.Observation:2m to screen(wide only)
3.Criteria:
1.pattern uniform and clear-------->OK
2.If can’t focus uniform and clear，switch to 区 pattern
and focus uniform clear all over screen (central must
clear than corner)
Measure flare and defocus
a.flare:R,G≦2.5 B≦3.5
b.defocus:≦2.5
(区 pattern: Chroma 84,flare and defocus pattern: chroma 34)
1.9.2 for AOCI lens(A.17) (A.19) Flare : Defocus
R <=4.5 R < = 2.0
G<=4.5 G < = 2.0
B<=4.5 B < = 2.0
20.Lateral Color Pattern(A.19) Center of screen All other area
R-G <1/2 <1
G-B <1/2 <1
R-B <2/3 <1
21. Compatibility
21.1 PC PC Compatible 640X400 Æ 1024X768, compressed
1280X1024; Composite-Sync; Sync-on-Green; Interlace
Mode (8514A);
Detailed Support Timing Specification refer to Appendix
E.1
PC Frequency H-Sync 24 ~ 88 KHz
Limitation V-Sync 48 ~ 100 Hz
Pixel Clock 140 MHz
21.2 Video NTSC/ NTSC4.43/ PAL (Including PAL-M, PAL-N)/
SECAM/ PAL60/
21.3 YPbPr NTSC 480i/ 480p, PAL 576i/ 720p, HDTV 720p/1080i
87
DMD Image Specification
1. SCOPE
This document specifies the image quality requirements applicable to the XGA RGBW
Palmtop Configuration F Component Kit. The Component Kit provides the XGA RGBW
Palmtop Projector with Digital Imaging functionality based on Digital Micromirror Device
(DMD) technology.
2. Definitions
2.1 Blemish
A blemish is an obstruction, reflection, or refraction of light that is visible, but out of
focus in the projected image under specified conditions of inspection (see Table 1).
It is caused by a particle, scratch, or other artifact located in the image illumination
path.
2.2 Dark pixel
A dark pixel is a single pixel or mirror that is stuck in the OFF position and is visibly
darker than the surrounding mirrors.
2.3 Bright pixel
A single pixel or mirror that is stuck in the ON position and is visibly brighter than
the surrounding mirrors.
2.4 Unstable pixel
A single pixel or mirror that does not operate in sequence with parameters loaded
into memory. The unstable pixel appears to be flickering asynchronously with the
image.
2.5 Adjacent
Two or more stuck pixels sharing a common border or common point , also referred
to as a cluster .
2.6 Streaks
Artifact resulting from localized variation in mirror tilt angle relative to surrounding
mirrors . They are similar in appearance to window scratches but appear at the
mirror
Level . Streaks appear as faint diagonal or arcing patterns in the image.
2.7 Sea of Mirrors ( SOM )
SOM is a rectangular array of off-state mirrors surrounding the active area.
2.8 Eyecatcher
A small localized light “spot” which haas high spatial frequency and high
differential
Brightness. These are due to various DMD window or window aperture “defects”
Including : digs , voids , particles and scratches.
88
2.9 Border Artifacts
All variations of these artifacts are acceptable under this image quality
specification.
Border artifacts are a general category of image artifacts that may show up on
screen in the area outside of the active array. Border artifacts include: Exposed
Bond Wires , Exposed Metal 2 , and Reflective Edge.
2.9.1 Bond Wires

Bond Wires attach the die to the superstructure. If visible, they will appear as
short light parallel lines outside of the Sea of Mirrors ( SOM ).
2.9.2 Exposed Metal 2 is due to a shift in positioning of either the die or the
window aperture which may allow light to be reflected off of the layer of
metal 2 that is below the super structure ( mirrors ). This defect is located at
the outer edge of the SOM.
2.9.3 Reflective Edge

Reflective Edge is light that may reflect from the edge of the DMD”s
window aperture onto the projection screen. It will appear as a thin diffuse
line outside of the SOM.
2.10 Two Zone Blue 60 Screen

The Two Zone Blue 60 screen is used to test for major dark blemishes. Refer to Figure
1 for configuration. All areas of the screen are colored a Microsoft Paintbrush blue 60
( green and red set at 0 , blue set at 60 ).
NOTE : If linear degamma table being used in order to generate an equivalent blue
level on the test screen image.
2.11 Two Zone Gray 10 Screen

The Two Zone Gray 10 screen is used to test for major light blemishes. Refer to Figure
1 for configuration. All areas of the screen are colored a Microsoft Paintbrush gray 10
( green , red , and blue set at 10 ).
NOTE : If linear degamma is not used then the Microsoft Paintbrush values must be
adjusted to match the degamma table being used in order to generate an equivalent
gray level on the test screen image.
89
3. ACCEPTANCE REQUIREMENTS
3.1 Conditions of Acceptance
All DMD image quality defects must be determined under the folloeing projected
image test conditions :
a. Projector degamma shall be linear.
b. Projector error diffusion shall be “off “.
c. Projector brightness and contrast settings shall be set to nominal.
d. The diagonal size of the projected image shall be a minimum of 60 inches.
e. The projection screen shall be 1X gain.
f. The image shall be in focus during all Table 1 tests.
g. The projected image shall be inspected from an 8 feet minimum viewing distance.
3.2 Test Sequence

Tests shall be run in the sequence listed in Table 1
TABLE 1. Image Quality Specification
SEQ TEST SCREEN ACCEPTANCE CRITERIA

#
1 Major Dark Two Zone 1. No blemish will be darker than Microsoft Blue
Blemish Blue 60 60 in the Critical Zone
2. <=2 blemishes in the Non-Critical Zone
3. No blemish will be >1/2” long / diameter
2 Major Light Two Zone 1. No blemish will be lighter than Microsoft Gray
Blemish Gray 10 10 in the Critical Zone
2. <=2 blemishes in the Non Critical Zone
3. No blemish will be > 1/2” long / diameter
3 Eyecatcher Gray 10 1. No eyecatcher will be lighter than Microsoft Gray

10
Streaks Blue 60 1. No streaks

Gray 10
White
90
Projected Any screen 1. No adjacent pixels.
Image 2. No bright pixels ( Active Area )
3. <= 1 bright pixel ( SOM )
4. ≤ 4 dark pixels
5. ≤ 6 minor blemishes.
6. No DMD window aperture shadowing on the
Active Area
7. No unstable pixels in Active Area
Notes :
1. Projected blemish numbers include the count for the shadow of the artifact in addition to
the artifact itself, so that the count usually represents a single artifact on the window.
2. No blemish shall be more than 5 inches long or have a total area of more than 5 square
inches on a 60 inch diagonal projected image. ( <= 1/2 inch for Major Blemish tests )
3. During all Table 1 tests , projected images shall be inspected in accordance with the
conditions of inspection specified in Section 3.
4. The rejection basis for all cosmetic DMD defects ( scratches , nicks , particles ) will be
the projected image tests referenced in Table 1.
5. Any other image quality issue not specifically defined in this document shall be
acceptable.
6. Black screens shall not be used as a basis for rejecting DMDs for image quality.
Figure 1. Major Blemish Two Zone Screen
Non Critical Zone
Critical Zone
center 25%
91
Optical Measurement
1.Scope:
This document describes critical optical related test definitions and Instructions for data or
video projectors. The other general terminologies are specified in ANSI IT7.228-1997.
2.General Requirements
1. The unit under test should be allowed to stabilize without further
adjustment for a minimum of 5 minutes, at nominal ambient room
temperature of 25°C, before making measurements.
2. Measurements shall take place in a light proof room, where the only
source of illumination is the projector. Less than 1 lux of the light
on the screen shall be from any source other than the projector.
3. All measurements shall be made on flat screens that do not provide
any advantage to the performance of the unit
4. All measurements shall be made at standard color temperature
setting, 100% white image (per ANSI IT7.228-1997), except
where noted
3.Practical Requirements
1. When measuring contrast manually, operators should not wear white clothing since
light reflected from white clothing can influence the measurement.
2. Unless otherwise specified, the projection lens is set in the widest zoom position since
zoom function can influence the measurement.
3. Measurement should be performed with Minolta Chromameter, Model CL-100, or
equivalent.
A1. ANSI BRIGHTNESS

ANSI Lumens = (L1+L2+L3+L4+L5+L6+L7+L8+L9)/9 (lux) x A(m^2)
A (Area) = W * H (m^2)
W: width of projected image (m)
H: height of projected image (m)
92
L10 L11
L1 L2 L3
L4 L5 L6
L7 L8 L9
L13 L12
Note: L10, L11, L12, L13 are located at 10% of the distance from corner itself to L5
A2. BRIGHTNESS UNIFORMITY

Brightness Uniformity = Minimum (L10,L11,L12,L13)/ Average (L1,L2,L3,L4,L5,L6,L7,L8,L9)
A3. JBMA UNIFORMITY

JBMA Uniformity = Average (L1,L3,L7,L9)/ L5
A4. ANSI CONTRAST

ANSI Contrast = Average lux value of the white rectangles/Average lux value of the black
rectangles
Contrast Ratio shall be determined from illuminance values obtained from a
black-and-white ”chessboard” pattern consisting of 16 equal rectangles. The white rectangles
shall be at 100% gray and the black rectangles at 0% gray. Illuminance measurements shall
be made at the center of each of the rectangles.
A5. FOFO CONTRAST

FOFO Contrast = Lux value at the center of a solid white screen/the lux value at the center of
a solid black screen
A6. JBMA CONTRAST

JBMA Contrast = Average (L1,L2,L3,L4,L5,L6,L7,L8,L9) under solid white / Average
(L1,L2,L3,L4,L5,L6,L7,L8,L9) under solid black
A7. LIGHT LEAKAGE

Leakage = The maximum light leakage under a solid black pattern in or outside of the
projected image
93
A8. IMAGE DISTORTION
Keystone = (W2-W1)/ (W1+W2) x 100%
Vertical TV dist = (H1+H2-2xH3)/2H2 x100%
Horizontal TV dist = (W1+W2-2xW3)/2W1 x100%
W1: image width at image bottom
W2: image width at image top
W3: image width at the half image height.
H1: image height at image left
H2: image height at image right
H3: image height at half image
Note:
1. Keystone and Vertical TV Distortion are recommended for Front Projection Display
2. Vertical and Horizontal TV Distortion are recommended for Rear Projection Display
A9. THROW RATIO

Throw ratio = projection distance / the width of the projected image
A10. ZOOM RATIO

Zoom ratio = maximum / minimum image diagonal size at a fixed projection distance
A11. FOCUS RANGE
The minimum/maximum focus distance is the minimum/maximum projection distance (The
distance between the outermost element of projection lens and screen), expressed in meter,
at which the image is still at its acceptable focus level.(acceptable focus level is specified by
FOCUS LIMIT SAMPLE approved by customer)
A12. COLOR
Color is expressed as (x, y) in 1931CIE chromaticity values
Note: Color is measured at the center of the screen that is entirely the measured color under
default brightness and contrast settings.
A13. ANSI COLOR

ANSI Color is expressed as (u, v) in 1976 CIE chromaticity values
Note: Color is measured at the center of the screen that is entirely the measured color under
default brightness and contrast settings.
A14. COLOR UNIFORMITY

Color Uniformity is the maximum color difference (△x, △y) between any two points out of
L1~L13
94
A15. ANSI COLOR UNIFORMITY
ANSI Color Uniformity: △u’v’= [(u’1-u’0)^2+(v’1-v’0)^2]^1/2
(u’0,v’0): the average color of L1~L13
(u’1,v’1): the spot with maximum deviation from (u’0,v’0)
A16. PROJECTION OFFSET

Projection Offset= Image height above projection lens optical axis / Total image height x
100%
Note: Optical engine should be kept horizontal attitude
A17. Customer Defined Focus
i. Focus test procedure (Wide only)
a. Pattern: Cross Hatch (Refer to A27 for all related test patterns)
b. Steps:
Step 1: Get best focus at Screen Center with “Phon Pattern”
Step 2: Check “Cross Hatch” at 60”, Wide position.
Step 3: Observe R, G, B color separately and check “Center and 4 corners of
screen” for “Defocus” and “Flare” (Check line only, no check point)
Step 4: Good (“Defocus” << A, “Flare” << B)Æ No more check needed
Step 5: LimitÆ Check “Defocus” (60” <A pixels)
Check “Flare” (60” <B pixels)
Step 6: Worst unit of the dayÆ Check “Letter pattern” (Screen to Observer 6m,
Wide and Tele same spec) with:
“Defocus” < C pixels
“Flare“ < D pixels
ii. Criteria: Measure the flare size with agreed “Grid” paper and as follows:
Grid of 1.5
1 Pixel
pixels
Flare
Defocus
1.5 pixels
95
5 4 3 2 1
D D
Screw Holes
GND
1
1
5 9 5 9 5 9 5 9
4 8 4 8 4 8 4 8
POWER FAN
3 7 3 7 3 7 3 7
2 6 2 6 2 6 2 6
V12 V12
H1 H2 H3 H4 V12 V12
V DD_F V DD_F
HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 VDD_F VDD_F
C C
SDA SDA
SDA SCL SCL SDA
SCL SCL
FAN1_E FAN1_E
FAN1_E FAN2_B FAN2_B FAN1_E
FAN2_B FAN2_B
G ND G ND
GND GND
Optical Points
OP1 OP2 OP3 OP4 OP5 OP6 OP7 01_POWER 02_FAN

B B
OP OP OP OP OP OP OP
OP8 OP9 OP10 OP11 OP12 OP13 OP14

Benq Corporation
Project Code Model Name OEM/ODM Model Name
A
99.J8677.001 PB6100 ODM A
Title
FAN BOARD
Size PCB P/N PCB Rev. Document Number Rev.

<Size> 48.J8613.S02 S02 0
99.J8677.B12-C3-304-002
Date: Wednesday, August 06, 2003 Sheet 1 of 3

Prepared By Reviewed By Approved By
ANGEL HU KEN JA CHEN JACK CHEN
5 4 3 2 1
5 4 3 2 1
RS701
CS701 CS702
47
RS702
1000P K 1000P K
G1
380Vdc Q701 J7304
T6301 47 V12 5V
1 10 SI4431DY-T1
1
VDD 3 8 LAMP-SYNC 1
J6301 C6301 2 7 LAMPLIT 2
R6301 0.01U M RA601 2 1 6 3
1 LAMP-RXD
1
D CA1 47K 680K CA2 3 9 R701 5 4
D
2 0.01U M 0.01U M D7301 + C7301 + C7303 47K
3 SCL 5
10CTQ150S 470U 25V 470U 25V R702 6
D6301 US1M SDA
4
therm FAN_P 7
2
2062010103
2 1 2 8 47 8
J6302 W
D6302 1
G2
18Vcc 2 1 W VDD
1
G2
DRILL-22 D7302 L7301 20D0049108
2 R6307 47 ES1D 1 2
1
2060089102 4 10UH 5
1
D6303 SS3H10 + C7302 4
RS703 470U 25V R7313 R7314 + C7305 FAN1_E
R6308 2 1 3 FAN1_E
1K 1K 220U J7302 2
CS703 CS704 47
2
R6309 US1J 5 25V 20L2021005 1 FAN2_B
47 FAN2_B
2
10KF 600UH
G1
C6304 RS704
2200P J 2200P J
1
RA602 1U Z
+ C6302 680K 47
47U 50V
CY6301
6
R7305 U6305 L7302 2V5
2
1 2
GND G
VIN VOUT
C 330 180U K C
G1
ON
RA603 3300P Y1
FB
PQ1CY1032Z
2
680K V12 J7301
1
D7303 1
G1
V12
4
RF5 VDD V12 SS24 R7310 + C7308 1
1
U6302 1K C7309 2.4K 220U 2
1000P M 25V 5V 2
2
U6301 PC123FY1 3 3
2
2
R7304 4
L
5.1K 4
TOP247Y 1 5
C 5
S
R7306 6 6
C7307 2V5
R6302
4
R7308 R7312 0.1U K R7311 7

6.8 15K 3.32KF 30K F 2.32KF 7
G2
GND 8 8
C7306
U7302 0.1U K
20D0038108
G2
1
R6304 C6303 C6306 LM431 R7307

30K + 0.1U M + 2
47U 50V C7310
VDD VDD
10U 470
16V
2
B R7309 B
2.32KF
R402 R401
TP1 TP2 TP3 TP4 TP5 100 4.7K
G1
1
1 LAMPLIT
W2 L2 500 OHM J7303 2
IN 20L2021005 3
H6 QF1
DC601 4 LAMP-SYNC
L1 500 OHM SI4431DY-T1 5 LAMP-RXD
1
1 3 IN 3 8
1
VDD VDD_F R404
1
2 7 100
G2
SF10L60U RF4 1 6 + CF2
hsink2 47K 5 22U
FOR DC601 16V
2
FOR U6301 TR601 TR602 380Vdc RF1 47 Note:Bllast control Pin
t
4
2 1 2 1
1
Benq Corporation
NTC 5 OHM NTC 5 OHM
3
CC601 + CC602
0.47U K 100U RF2 2K 1 QF2
FAN_P
450V MMST3904 Project Code Model Name OEM/ODM Model Name
2
A
99.J8677.001 PB6100 ODM A
CF1 Title
RF3 FAN BOARD
0.1U M 10K Size PCB P/N PCB Rev. Document Number Rev.
<Size> 48.J8613.S02 S02 0
99.J8677.B12-C3-304-002

5 4 3 2 1
5 4 3 2 1
R518 OPEN R511

VDD_F
V12 2.4K
C518 220P J V12
CA506 C506 CA507
VDD_F R507 R512 2.4K 0.47U K 0.1U M 0.47U K R517
R519 OPEN
CA508 V12
U501 4.7K U502 4.7K
1
0.1U M C519 220P J
1
D Q503 D
1 VDD NC 16 3 SCL 14 SMBCLK VCC 15
2 15 2SB772S 12 2 3 Q506
32.768KHZ AR FR SDA SMBDATA VCC
3 14 FAN1_B 2SB772S
2
R501 2M A F RA501
4 13 3 C507
2
BR NC 4.7K R510 DXP1
5 B ER 12 VDD_F 11 ALERT 2200P K FAN1_E RA503
10M 6 CR E 11 10K DXN 4 4.7K
R502 7 10 Q504 6 C508
C DR RESET FAN1_P
3
8 9 2N3904 5 2200P K
VSS D R509 DXP2 FAN2_B
3
25.6KHZ 1 1 OUT1 Q505
CD4049UBCM 2.2K OUT2 16 1
10 13 R516 2N3904
VDD_F
2
FAN4_P FG1 FG2
1
C501 Y501 C502 R508 7 R514 2.2K
2
+ C505 2.2K GND + C509
9 8 10K
10P J 10P J 22U RB501 CLK GND 22U
2.2K FANSPIN1
16V G768B R515 RB502 16V
2
2.2K 2.2K
32.768KHZ
R513
FANSPIN4 VDD_F
Crystal generate the clock for fan control IC.
10K
2 fan speed control and 2 thermal sensor detect IC

C C
RA504
G2
V12
J501
3
2
1
680 VDD_F
4 FANSPIN2
3 FAN2_P
2 VDD_F
1 RA502
Q501 4 C504
SI4431DY-T1 5.6K R504 0.1U M
G1
U505 G751-2
10K
20L2021004
8
7
6
5
R520 5 1 SDA SDA

0 A2 SDA
FANSPIN2 U503
6 2 SCL SCL
A1 SCL
1 OUT VCC 8
7 A0
R503 2 7
F.G. SDA SDA
J502 47K 3
O.S.
3
3 6
G2
10 FAN1_E Q502 R505 ON/OFF SCLK SCL

1 8
GND
B FAN1_B VDD_F B
9 2N3904 VCC
8 2.2K 4 GND CLK 5 32.768KHZ
FAN1_P
2
7 C510
G760A
4
6 0.1U M
5 FANSPIN1 RA505
R506 2.2K
4 FAN2_P
1
820
3 FAN4_P GND
+ C503
2 FANSPIN4 47U
G1
1 16V
2
Thermal sensor
20L2021010
Fan control IC
Benq Corporation
A
99.J8677.001 PB6100 ODM A
Title
FAN BOARD

<Size> 48.J8613.S02 S02 0
99.J8677.B12-C3-304-002

5 4 3 2 1
5 4 3 2 1
D D
80*2_CONN DMD_CHIP
DD[63 :0]
DD[63:0] DD[63:0]
C MBRST[15:0] C
MBRST[15:0] MBRST[15:0]
DCLK_L
DCLK_L DCLK_L
D MDSER
DMDSER DMDSER
SACCLK
SACCLK SACBUS SACCLK
SACBUS SACBUS
SCTRL_L
SCTRL_L LOADB_LZ SCTRL_L
LOADB_LZ TRC_L LOADB_LZ
TRC_L TRC_L
P3P3V
P3P3V P3P3V
V CC2
VCC2 VCC2
G ND
GND GND
80*2_CONN DMD_CHIP
B B
A
Benq Corporation A
99.J8677.001 PB6100 ODM
Title
CHIP BOARD

<Size> 48.J8623.S01 S01 0
99.J8677.B12-C3-304-003

ANGEL HU DAVID HN LIN KELVIN LIAO
5 4 3 2 1
5 4 3 2 1
DD[63 :0] DD[63 :0]

DD[63:0]
D
J1 D
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15 TP17
18 17
20 19 TP21 BINSEL0
BINSEL0
22 21 TP23 BINSEL1
BINSEL1
24 23
P3P3V TP24 26 25 VCC2
P3P3V TP25 28 27 TP26 VCC2
30 29
SACCLK SACCLK TP27 32 31 TP28 D MDSER DMDSER
SACBUS SACBUS TP29 34 33 TP30 LOADB_LZ LOADB_LZ
SCTRL_L SCTRL_L TP31 36 35
TRC_L TRC_L TP32 38 37 TP33 DCLK_L DCLK_L
40 39
D D62 TP34 42 41 TP35 D D63
D D60 TP36 44 43 TP37 D D61
46 45
D D58 TP38 48 47 TP39 D D59
D D56 TP40 50 49 TP41 D D57
52 51
D D54 TP42 54 53 TP43 D D55
D D52 TP44 56 55 TP45 D D53
C 58 57 C
D D50 TP46 60 59 TP47 D D51
D D48 TP48 62 61 TP49 D D49
64 63
D D46 TP50 66 65 TP51 D D47
D D44 TP52 68 67 TP53 D D45
70 69
D D42 TP54 72 71 TP55 D D43
D D40 TP56 74 73 TP57 D D41
76 75
D D38 TP58 78 77 TP59 D D39
D D36 TP60 80 79 TP61 D D37
20L1065080
J2
2 1
D D34 TP62 4 3 TP63 D D35
D D32 TP64 6 5 TP65 D D33
8 7
D D30 TP68 10 9 TP69 D D31
D D28 TP72 12 11 TP73 D D29
14 13
D D26 TP78 16 15 TP79 D D27
D D24 TP82 18 17 TP83 D D25
20 19
22 21
D D22 TP87 24 23 TP88 D D23
D D20 TP91 26 25 TP92 D D21
28 27
B D D18 TP96 TP97 D D19 B
30 29
D D16 TP100 32 31 TP101 D D17
34 33
D D14 TP106 36 35 TP107 D D15
D D12 TP108 38 37 TP109 D D13
40 39
D D10 TP110 42 41 TP111 D D11
DD8 TP112 44 43 TP113 DD9
46 45
DD6 TP114 48 47 TP115 DD7
DD4 TP116 50 49 TP117 DD5 P3P3V
52 51
DD2 TP120 54 53 TP121 DD3
DD0 TP123 56 55 TP124 DD1
58 57
60 59 R1 R2
MBRST14 TP125 62 61 TP126 MBRST15 1K 1K
MBRST12 TP127 64 63 TP128 MBRST13
MBRST10 TP129 66 65 TP130 MBRST11 H1
MBRST8 TP131 68 67 TP132 MBRST9 1 4 BINSEL0 BINSEL0
70 69 GND 2 3 BINSEL1 BINSEL1
MBRST4 TP135 74 73 TP136 MBRST5 6240019001
80 79 BINSEL1 BINSEL0 DMD Bin
A
20L1065080 0
0
0
1
B
C
Benq Corporation A
1 0 D Project Code Model Name OEM/ODM Model Name
MBRST[15:0] 1 1 E 99.J8677.001 PB6100 ODM

MBRST[15:0]
Title
CHIP BOARD

<Size> 48.J8623.S01 S01 0
99.J8677.B12-C3-304-003

5 4 3 2 1
5 4 3 2 1
DD[63 :0]
DD[63:0]
D D10
D D11
D D12
D D13
D D14
D D15
D D16
D D17
D D18
D D19
D D20
D D21
D D22
D D23
D D24
D D25
D D26
D D27
D D28
D D29
D D30
D D31
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
TP1
D TP2 T POINT A D
T POINT A
G01
G03
G05
C01
D04
C03
H02
H04
D06
H06
D10
C09
C07
D12
C13
E01
E03
E05
A01
K06
B06
K04
B04
A03
A07
B10
A09
B12
A13
A15
L05
L03
1
U1A
1
MBRST[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
MBRST[15:0]
MBRST15 Y20
MBRST14 MBRST_15 READ_OUT2
AB20 MBRST_14 READ_OUT2 AB22
MBRST13 AA19 AA23 READ_OUT
MBRST12 MBRST_13 READ_OUT D MDSER
AC19 MBRST_12 SCAN_TEST M28 DMDSER
MBRST11 AA17
MBRST10 MBRST_11
AC17 MBRST_10
MBRST9 Y16 VCC2
MBRST8 MBRST_9
AB16 MBRST_8
MBRST7 AB14 N29 V CC2 VCC2
MBRST6 MBRST_7 VCC2A
Y14 MBRST_6 VCC2B P02
1
MBRST5 AC13 P30 C1 C2 C3 C4 C5
MBRST4 MBRST_5 VCC2C + 1U 0.1U M 0.1U M 0.1U M 0.1U M
AA13 MBRST_4 VCC2D R01
MBRST3 AC11 R29 16V
MBRST2 MBRST_3 VCC2E 20% 16V 16V 16V 16V
AA11 T02
2
MBRST1 MBRST_2 VCC2F
AB10 MBRST_1 VCC2G T30
MBRST0 Y10 U01
MBRST_0 VCC2H
DCLK_L DCLK_L C15 Y22

DCLK EVCC0
EVCC1 AB08
LOADB_LZ LOADB_LZ B16 LOADB
C
SACCLK SACCLK AC25 C
SACBUS SAC_CLK
SACBUS AA25 SAC_BUS
SCTRL_L SCTRL_L N03

TRC_L SCTRL Optical Points
TRC_L L01 TRC
AC23 PRG_FUS_EN
Y08 OP1 OP2 OP3 OP4 OP5 OP6 OP7
BI_MODE OP OP OP OP OP OP OP
K02 BI_TOF
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
DMD 0.7XGA DDR
M26
F30
F28
F26
D16
B18
A19
A21
C19
D18
B22
B24
A25
C21
C25
A27
K28
D22
K26
B30
K30
B28
J25
C27
J27
D26
J29
D24
G27
D28
G29
D30
OP8 OP9 OP10 OP11 OP12 OP13 OP14
D D32
D D33
D D34
D D35
D D36
D D37
D D38
D D39
D D40
D D41
D D42
D D43
D D44
D D45
D D46
D D47
D D48
D D49
D D50
D D51
D D52
D D53
D D54
D D55
D D56
D D57
D D58
D D59
D D60
D D61
D D62
D D63
DD[63 :0]
Screw Holes
B B
GND
AC07
AB26
AB24
AB18
AB12
AB06
AA21
AA15
AA09
AA07
U29
V02
Y24
Y18
Y12
U1B
1
P3P3V 5 9 5 9 5 9 5 9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P3P3V A05 P3P3V GND U03 4 8 4 8 4 8 4 8

A11 P3P3V GND T28
C6 C7 A17 R03
0.1U M 0.1U M P3P3V GND 3 7 3 7 3 7 3 7
A23 P3P3V GND P28
A29 P3P3V GND P04 2 6 2 6 2 6 2 6
16V 16V D02 N27
P3P3V GND
H30 P3P3V GND M04 H3 H4 H5 H6
J01 P3P3V GND M02
M30 P3P3V GND L29 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8
C8 N01 L27
P3P3V GND
1
10U C9 C10 V30 L25

0.1U M 0.1U M P3P3V GND
+ W01 J05
P3P3V GND
AC05 P3P3V GND J03
10V 16V 16V AC09 H28
2
P3P3V GND
AC15 P3P3V GND H26
AC21 P3P3V GND F04
AC27 P3P3V GND F02
GND E29
C11 C13
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C12 C14
0.1U M 0.1U M
Benq Corporation
16V 0.1U M 16V 0.1U M DMD 0.7XGA DDR
B02
B08
B14
B20
B26
C05
C11
C17
C23
C29
D08
D14
D20
E27
16V 16V
A A
99.J8677.001 PB6100 ODM
Title
CHIP BOARD

<Size> 48.J8623.S01 S01 0
99.J8677.B12-C3-304-003

5 4 3 2 1
A B C D E
3.3V_D
SDA0
SCL0
GND
SDA
SCL
4 PAGE_5 4
004_DISPLAY
3.3V_D
SDA
SCL
SDA0
SCL0
DRE[7:0] DRE[7:0]
SDA0
SCL0
DRE[7:0] DRE[7:0]
DGE[7:0] DGE[7:0]
DGE[7:0] DGE[7:0]
DBE[7:0] DBE[7:0]
DBE[7:0] DBE[7:0]
V12_D
D HS D HS V12_D
DHS DVS DVS DHS VDD_D
DVS DVS VDD_D
3.3V_D
DCLK DCLK 3.3V_D
3 DCLK D EN D EN DCLK 2V5_D
3
DEN DEN 2V5_D
POWERON POWERON
POWERON RESETZ RESETZ POWERON
RESETZ LAMPLITZ LAMPLITZ RESETZ
LAMPLITZ LAMPLITZ
SCL
SCL SDA
SDA
ECO-MODE
ECO-MODE
GND ECO-MODE
GND
FAN_P
VDD
VDD
3.3V
LAMPEN
PAGE_2 LAMPEN PAGE_3
001_MAIN 002_DMD
V DD
V DD
3.3V
ECO-MODE
FAN_P
LAMPEN
VDD_D
3.3V_D
2V5_D
V12_D
V DD
3.3V
2 2
VDD
ECO-MODE
LAMPEN
LAMPLITZ
VDD_D
3.3V
SDA
2V5_D
3.3V_D
V12_D
SCL
RESETZ
FAN_P
PAGE_4 GND
003_POWER&LAMP&DETECT
Benq Corporation
1 99.J8677.001 PB6100 <OEM/ODM> 1
Title
MAIN BOARD
Size PCB P/N PCB Rev. Document Number R ev.

<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004
Date: Tuesday, October 07, 2003 Sheet 1 of 20

A B C D E
A B C D E
Regect RC1 and RC2 before connect DX660 main board with
INTERFACE board.
SCL SCL
SDA
SDA
014_MEMORY&KEYSTONE VDD
GND
INPUT PAGE_9
VDD VDD
SCL
SDA
4 3.3V 4
RESETn 3.3V 3.3V
KEYSTONE
VDD
POWERON
DECODE
ROMWEn
3.3V 3.3V
ROMOEn
VDD
MCKEXT
SCL
DCKEXT
VDD VDD
VPPEN
SCL
RESET
BHENn
D[0:15]
A[19:1]
012_DECODE SDA
VDD SDA
A0
VDD GND GND
V33 PAGE_11
016_MISC
KEYSTONE
POWERON
DCKEXT
MCKEXT
D[0:15]
A[19:1]
BHENn
ROMWEn
V33
RESET
ROMOEn
D[0:7]
VPPEN
3.3V
A0
LLC1
3.3V LLC2
VY[7:0] VY[7:0]
SDA VY[7:0] VY[7:0]
DCKEXT
ROMOEn
MCKEXT
D[0:7]
D[0:15]
A[19:1]
VPPEN
RESET
ROMWEn
KEYSTONE
A0
BHENn
SCL VUV[7:0] VUV[7:0] POWERON
VUV[7:0] VUV[7:0] POWERON POWERON
CHROMA CHROMA RESETZ RESETZ
CHROMA CHROMA VVS VVS RESETZ
LUMA LUMA VVS VFIELD VFIELD VVS
LUMA LUMA VFILD VPEN VPEN VFIELD DRO[7:0] DRE[7:0]
VPEN VPEN DRE[7:0] DRE[7:0]
CVBS CVBS VHS VHS
BAIN_V GAIN_V
GAIN_V RAIN_V
BAIN_V
CVBS CVBS VHS VCLK VCLK VHS
AVDD
VCLK VCLK DGO[7:0] DGE[7:0]

GND DGE[7:0] DGE[7:0]
3 3
RAIN_V
SCL DBO[7:0] DBE[7:0]

AVDD
V33 SCL DBE[7:0] DBE[7:0]

SDA
SDA D HS
DHS DHS
DVS DVS
SDA V33 DVS D EN
AVDD
GAIN_V
BAIN_V
RAIN_V
SDA DEN DEN

SCL GRE[7:0] GRE[7:0] DCLK
SCL GRE[7:0] GRE[7:0] DCLK DCLK
GGE[7:0] GGE[7:0] Note: To DDP1000 input port
GGE[7:0] GGE[7:0]
GBE[7:0] GBE[7:0]
GBE[7:0] GHS GHS GBE[7:0] LAMPLITZ
GHS GHS LAMPLITZ LAMPLITZ
GVS GVS
GVS GVS Note: Lamp on/off detect signal.
GBLKSPL GBLKSPL
RAIN_C RAIN_C GBLKSPL GFBK GFBK GBLKSPL
RAIN_C GAIN_C GAIN_C RAIN_C GFBK GCLK GCLK GFBK
GAIN_C BAIN_C BAIN_C GAIN_C GCLK GCOAST GCOAST GCLK Note: PW164B RS232 I/O port connect with
BAIN_C VSYNC_C VSYNC_C BAIN_C GCOAST VDD GCOAST PC ( for control ) and Ballast ( for lamp
VSYNC_C VSYNC_C stasus )
HSYNC HSYNC VDD
HSYNC HSYNC ECO-MODE
GND ECO-MODE ECO-MODE
2 PAGE_8 2
013_AFE
FAN_P FAN_P
FAN_P
RESETn
RESETn D[0:7]
D[0:7] CS1n CS1n VDD
CS1n CS0n CS0n CS1n
VDD VDD CS0n CS0n
IRRCVR
key8 key8 VDD 3.3V
AUDIO_MUT
3.3V
AUDIO_VOL
3.3V
CONTROL
PAGE_12 GND 3.3V
IRRCVR
017_KEY
GND
TDO
RXD
TMS
TCK
TXD
IRR CVR
PAGE_10
015_PW166
Benq Corporation
IRR CVR
CONTROL
CONTROL
1 99.J8677.001 PB6100 <OEM/ODM> 1
Title
MAIN BOARD
RXD RXD
RXD TXD TXD Size PCB P/N PCB Rev. Document Number R ev.
TXD
GND
<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004
011_INPUT Date: Tuesday, October 07, 2003 Sheet 2 of 20

A B C D E
5 4 3 2 1
DRE[7:0]
DRE[7:0]
DGE[7:0]
DGE[7:0]
DBE[7:0]
DBE[7:0]
D DAD1000 D
VDD V DD VDD
SR16ADDR0
V12_D SR16ADDR0 SR16ADDR1 SR16ADDR0
V12_D V12_D SR16ADDR1 SR16ADDR1
SR16ADDR2
2V5_D SR16ADDR2 SR16ADDR3 SR16ADDR2
2V5_D 2V5_D SR16ADDR3 SR16ADDR3 MBRST[0:15]
VDD_D SR16MODE0 MBRST[0:15] MBRST[0:15]
VDD_D VDD_D SR16MODE0 SR16MODE0
SR16MODE1 DDP1000_DATA
3.3V_D SR16MODE1 SR16MODE1
3.3V_D 3.3V_D
SR16SEL0
SR16SEL0 SR16SEL1 SR16SEL0
DBE[7:0]
DGE[7:0]
DRE[7:0]
GND SR16SEL1 SR16SEL1
SR16STROBE
SR16STROBE SR16STROBE
SR16OEZ SCTRL-L
SR16OEZ SR16OEZ SCTRL-L
SCTRL-L 3.3V_D 3.3V_D
3.3V_D SCPDI SACCLK VDD

3.3V_D SCPDI SCPDO SCPDI SACCLK SACBUS SACCLK VDD
SCPDO SCPCK SCPDO SACBUS SACBUS
2V5_D 2V5_D SCPCK SCPCK GND
SCPENZ DMDSER
SCPENZ SCPENZ DMDSER DMDSER
GND V12_D V12_D
DCLK-L
DCLK-L TRC-L DCLK-L
3.3V_D 3.3V_D TRC-L TRC-L
LOADB-LZ
C
EXT-ARSTZ LOADB-LZ LOADB-LZ C
EXT-ARSTZ DD[0:63]
IR QZ DD[0:63] DD[0:63]
IRQZ IRQZ
VCC2
VCC2
SCL0 SCL0
SDA0 SCL0
SDA0 SDA0 026_DMD_DAD1000
GND
ECO-MODE ECO-MODE
ECO-MODE
025_DMD_DDP1000_DATA VCC2
VDD_D VDD_D VCC2
BINSEL0 BINSEL0
BINSEL0 BINSEL1 BINSEL1 BINSEL0
3.3V_D 3.3V_D BINSEL1 BINSEL1
COSC COSC EXT-ARSTZ EXT-ARSTZ

FLASH-BUSYZ
COSC MOSC MOSC COSC EXT-ARSTZ CKMTR1 CKMTR1 EXT-ARSTZ

PUM-ARSTZ
MOSC CWINDEX CWINDEX MOSC CKMTR1 MTRSELZ MTRSELZ CKMTR1

CWINDEX CWINDEX MTRSELZ MTRCLK MTRCLK MTRSELZ
MTRCLK MTRCLK
FSD16
B MTRDATA MTRDATA VDD_D B

GND MTRDATA CWTACH CWATCH MTRDATA VDD_D
CWTACH CWTACH V12_D V12_D
DRCGPDZ
DRCGPDZ
GND
PAGE_15 PAGE_13
023_DMD_OSC&FAN 021_DMD_DDP1000
FLASH-BUSYZ
PUM-ARSTZ
FSD16
PAGE_20 PAGR_21
028_DMD_MOTOR 029_DMD_CHIP
2V5_D
3.3V_D
RQ[0:7]
LAMPEN LAMPEN RQ[0:7] RQ[0:7]
DRCGPDZ
FLASH-BUSYZ
PUM-ARSTZ
2V5_D
3.3V_D
FSD16
LAMPEN LAMPEN DQA[0:8]

LAMPLITZ LAMPLITZ LAMPLITZ 2V5_D
LAMPLITZ DQA[0:8] DQA[0:8] 2V5_D
DQB[0:8]
DQB[0:8] DQB[0:8] 3.3V_D 3.3V_D
CFM
CFM CFMN CFM
RESETZ RESETZ CFMN SCK CFMN
RESETZ RESETZ SCK SCK
Benq Corporation
POWERON POWERON POWERON SCLKN
D EN D EN POWERON SCLKN CMD SCLKN
DEN DEN CMD CMD
SIO
D HS D HS SIO PCLKM SIO
DHS Project Code Model Name OEM/ODM Model Name
DVS DVS DHS PCLKM CTM PCLKM
DVS DVS CTM CTM 99.J8677.001 PB6100 <OEM/ODM>
A CTMN A
DCLK DCLK CTMN REFCLK CTMN
DCLK DCLK REFCLK REFCLK Title
GND
VREF-RDRAM MAIN BOARD

VREF-RDRAM VREF-RDRAM GND
From Pixelworks output PAGE_14 PAGE_16 Size PCB P/N PCB Rev. Document Number R ev.
022_DMD_MEMORY 024_DMD_RAMBUS <Size>
48.J8601.S04 S04 99.J8677.B12-C3-304-004 1

5 4 3 2 1
A B C D E
J704 TP246
TP247
1 TP248LAMP-SYNC
LAMP-SYNC
2 LMAPLIT
TP240 TP249 LAMPLIT
G1
V12_D 3
J702 L714 4 TP250
TP251 SCL_F R783 R784
1 1 5
G1
V12_D SCL_F
1
6 TP252 SDA_F 10K 10K
4 TP241 SDA_F 4
2 80 OHM + C828 7 FAN_P OPEN OPEN
2 10U M FAN_P
C824 8
3 TP242 0.1U K 20V
2
3 R711 270
TP243 VDD
4 20D0049108
4 80 OHM L710 2V5_D
3
5 5 TP244 2V5_D
L: ECO-MODE Q706
80 OHM L711 H: Normal 1 ECO-MODE
1
6 TP245
6 80 OHM L712 + C829 C826 2N3904
2
7 22U 0.1U K
7 6.3V
2
G2
8 8
VDD_D
L744
VDD_D
G2
20D0038108 80 OHM
GND VDD
OPEN VDD
L713
VDD
80 OHM
1
1
C821 + C827 + C820 C823
10U M 0.1U K 10U M 0.1U K 3.3V RC3 RC4
20V 20V CP8 10K 10K
2
2
3 UC2 0.1U
3
1 NC VCC 8
SCL 2 7 SCL_F SCL_F
SCL SCL0 SCL1
SDA 3 6 SDA_F SDA_F
SDA SDA0 SDA1
4 GND EN 5
PCA9515DP
R735 0
U3 3.3V R734 0
LD1117-3.3V
3 VIN VOUT 2 3.3V
GND
VO 4
1
3.3V for main board

+ CP3
1
10U M 3.3V
6.3V VDD
2
VDD_D U4 3.3V_D CP1 R5

LD1117-3.3V LAMPLITZ connected to NPN collection pin 0.1U 100KF
3 2 and R6 change to 0 ohm U52
VIN VOUT 3.3V_D
5
74AHC1G08 L: Lamp on
GND
2 2
1
4 3.3V for DDP1000 1 H: Lamp off
C8 VO C9 LAMPLITZ
LAMPLITZ 4
2 3 2 LAMPLIT
LAMPLIT
1
0.1U 0.1U L: Lamp on MMBT2222A

25V Z 25V Z H: Lamp off Q1
3
R7 Q4_C
1
1M
+ C7
22U
25V
2
Generate 10mA and 0 mA to
ballast lamp sync signal
LAMP-SYNC
3.3V_D L: Lamp on To repair lamp light detect signal from ballast before send to DDP1000 and main board.
H: Lamp off
R11 Benq Corporation

100 Project Code Model Name OEM/ODM Model Name
UL1
<OEM/ODM>
5
1 74AHC1G08 99.J8677.001 PB6100 1

3
RESETZ RESETZ 1 Q6 Title

4 R12 2K 1 MAIN BOARD
LAMPEN LAMPEN 2
MMBT2222A Size PCB P/N PCB Rev. Document Number R ev.
2
<Size> 1
3
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
A B C D E
4 4
OPEN
SCL SCL R16 0 SCL0 SCL0 3.3V_D
3.3V_D
3 3
SCL
R18 R19 GND
4.7K 4.7K
TP14 J2
TP15
4
5
6
TP16
SW1 3
4
5
6
2
2240138001 1
1
2
3
20L2021003
1
2
3
SAD
OPEN
SDA SDA R21 0 SDA0 SDA0
SW1 is the switch to choice DDP1000 I2C would be connected with Pixelwork
I2C or not. J2 is the connector to DDP1000 I2C download by DDP1000 composer.
2 2
Benq Corporation
1 99.J8677.001 PB6100 <OEM/ODM> 1
Title
MAIN BOARD

<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
A B C D E
VDD VDD
2
DG3
DG4 DG1
3 3 3
BAV99
BAV99 BAV99
2022014015
1
TP17
G1
L9
4 TP18 2 1 1 2 1 2
4
6 RED_GND TP19 DG6 1N4148 DG5 1N4148 DG2 1N4148

TP27 11 1 RIN_2 TP20 RG21 0 RAIN_C
TP21 RAIN_C
7 GREEN_GND
TP28 12 2 GIN_2 TP22 RG22 0 GAIN_C
TP23 GAIN_C
8 BLUE_GND TP24
TP29 13 3 BIN_2 RG23 0 BAIN_C
BAIN_C
9 PC_5VIN_2 1 2 RG3 75
14 4 TP25 PC-RXD DG7 1N4148 150P J RG4 75
PC-RXD DDC5V_2 CG3 R842 RG5 75
10 VDD 1 2
15 5 PC-TXD DG8 1N4148 VDD
PC-TXD
RG8 4.7K 4.7K 0.1U
5
RG6 75 UH2
RG9 4.7K CG1 R795 0
G2
TP229 RG7 75 2 4 HSYNC

HSYNC
1 2 RG10 4.7K 74AHCT1G14
DG9 TZMC5V1 73.07414.0J0
1 2 RG11 4.7K CG2 R796
3
1
DG713
DG712
DG10 TZMC5V1 2K OPEN

DG13
DG12
DG11
470P K
2
2
U9 R841 CG701 VDD
5 4 0.1U UH702
SDA GND
5
TZMC5V1
TZMC5V1
4.7K
3 3
TZMC5V1
TZMC5V1
TZMC5V1 6 3
1
1
SCL A2 CG4 R797 1K
2 4 VSYNC_C
7 2 74AHCT1G14
WP A1 0.1U 73.07414.0J0
8 1 R798
3
1
VCC A0 2K
AT24C02N-10SI-2.7
3.3V
3.3V
TP280 R721 R722 CONTROL

G1
BEAD 3.3K 3.3K

J820 2 L720 CVBS R705 R706
CVBS
3.3K 3.3K
1
14
3
1
2210278001 C804 2 1 C721 R911 0 2 3
VDD PC-RXD RXD
G2
220P J 220P J
VDD VDD 7
DG701 U711A
BAV99 74LVC125A
2
2 R801 DN706 2
0 DN705
3 3
GND
BAV99 BAV99 3.3V
4
14
TP284
R910 0 6 5 TXD
TP282 PC-TXD
G1
J821
7
3 L721 BEAD LUMA U711B
G1
Y LUMA
74LVC125A
. 1
3
C822 2 1 C722
220P J VDD 220P J
G2 G2
DG702
TP283 BAV99
Benq Corporation
. 2
L722 BEAD CHROMA

G3
C 4 CHROMA
G3
<OEM/ODM>
3
1 2210021551 99.J8677.001 PB6100 1

C803 2 1 C723
VDD Title
220P J 220P J MAIN BOARD
R803
DG703 Size PCB P/N PCB Rev. Document Number R ev.
0
BAV99 <Size>
48.J8601.S04 S04 99.J8677.B12-C3-304-004 1

A B C D E
A B C D E
V33 R60 4.7K V33 DECOE
R61 4.7K
SCL
SCL SDA
SDA
R59
LLC2
LLC1
VDD U12 V33 VDD UA6 LD1117-3.3V AVDD
LD1117-3.3V 3
4 V33 VIN VOUT 2 AVDD 4
3 2
GND
VDD VIN VOUT
1
10K CA20 4
GND
VO + CA19
4
LLC2
LLC1
CA52 VO CA53 CA54 CA55 CA56 CA57 CA58 CA59 CA60 C300 C301 0.1U 22U
XRI
1
25V Z 25V
1
2
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
M12
M10
N14
N13
D13
C14
C13
C12
N11
N10
P13
B14
B13
B12
A13
A12
P11
P12
P10
B11
L10
C6
D6
N3
N2
N1
C4
C3
N9
N4
N5
A5
B5
B6
P2
B2
P9
P5
P4
XTRI
TMS
AMCLK
RTCO
TDO
TDI
TRST
TCK
AMXCLK
TEST19
TEST18
TEST17
TEST16
TEST15
TEST14
TEST13
TEST12
TEST11
TEST10
ASCLK
CE
SDA
SCL
RES
RTS1
RTS0
INT_A
LLC
TEST9
TEST8
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
ALRCLK
LLC2
AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD
M13 FSW XRV D8
LUMA R56 18 RLUM CA61 AI11 J2 C7
LUMA AI11 XRH
GAIN_V CA69 0.047U K K1 A6 CA43 CA44 CA45 CA46 CA47 CA48 CA49 CA50 CA51
GAIN_V AI12 XRDY
0.047U K K2 B7
AI13 XDQ 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
L3 AI14 XCLK A7
CA62 AI1D K3 A8
0.047U K AI1D XPD0
C2 AGND XPD1 B8
CHROMA R57 18 R CHR CA63 AI21 G4 A9
CHROMA AI21 XPD2
CA70 0.047U K G3 B9
CVBS R58 18 RCVBS 0.047U K CA64 AI23 AI22 XPD3
CVBS H2 AI23 XPD4 A10
0.047U K J3 B10
3
CA65 AI2D AI24 XPD5 VUV[7:0] 3
H1 AI2D XPD6 A11 VUV[7:0]
0.047U K E3 C11
BAIN_V CA71 AI31 XPD7 VUV0
BAIN_V F2 AI32 HPD0 D14
0.047U K F3 E11 VUV1
AI33 HPD1 VUV2
G1 AI34 HPD2 E13
CA66 AI3D F1 E12 VUV3
0.047U K AI3D HPD3 VUV4
L2 AGNDA HPD4 E14
B1 F13 VUV5
RAIN_V CA72 AI41 HPD5 VUV6
RAIN_V D2 AI42 HPD6 F14
0.047U K U13 VUV7
D1 AI43 HPD7 G13
SAA7118E ITRI
E1 AI44 ITRI L12
10P J C923
10P J C924
10P J C925
CA67 AI4D D3 K13 VFILD

AI4D IGP1 VFILD
0.047U K P3 L14
EXMCLR IGP0 VVS
M1 AOUT IGPV K14 VVS
R53
R54
R55
M2 K12 VHS
VSSA0 IGPH VHS
J4 VSSA1 ITRDY N12
H3 L13 VPEN
VSSA2 IDQ VPEN
E4 M14 VCLK_A R64 0 VCLK
VSSA3 ICLK VCLK
56
56
56
C1 G14 V Y0
VSSA4 IPD0 V Y1
OPEN AVDD M3 VDDA0 IPD1 G12
K4 H11 V Y2
VDDA1 IPD2 V Y3 R63
H4 VDDA2 IPD3 H14
F4 H13 V Y4 10K
VDDA3 IPD4 V Y5
2 D4 VDDA4 IPD5 J14 2
L1 J13 V Y6
VDDA1A IPD6 V Y7
J1 VDDA2A IPD7 K11
G2 N6 VY[7:0]
VDDA3A CLKEXT VY[7:0]
E2 VDDA4A ADP0 N8
VDD(xtal)
GND
VSS(xtal)
VDDD10
VDDD12
VDDD11
VDDD13
VSSD10
VSSD12
VSSD11
VSSD13
VDDD2
VDDD4
VDDD6
VDDD8
VDDD1
VDDD3
VDDD5
VDDD7
VDDD9
XTOUT
VSSD2
VSSD4
VSSD6
VSSD8
VSSD1
VSSD3
VSSD5
VSSD7
VSSD9
XTALO
XTALI
ADP8
ADP7
ADP6
ADP5
ADP4
ADP3
ADP2
ADP1
LLC2
LLC1 LLC2
LLC1
M5
M9
M4
M8
M6
M7
M11
D7
C8
D5
D9
G11
C5
C9
N7
L11
D10
F11
C10
D11
D12
H12
J11
L5
L9
F12
J12
L4
L8
A4
B3
A2
A3
B4
P6
L6
P7
L7
P8
V33
XTALI
XTAL
V33
1
CA68
Benq Corporation
+
22U
2
25V Project Code Model Name OEM/ODM Model Name

24.576MHZ
1 Y1 99.J8677.001 PB6100 <OEM/ODM> 1
Title
MAIN BOARD
C40 C41 Size PCB P/N PCB Rev. Document Number R ev.
22P J 22P J <Size>
48.J8601.S04 S04 99.J8677.B12-C3-304-004 1

A B C D E
A B C D E
AVDD AVDD_AD
OPEN
PVDD AVDD 0 AVDD_AD
AVDD
V33
R860
1
PVDD
V33
+ C850 C51 C52 C53 C54 C55 C56
1
C77 10U
C574 C573 + CA79 CA80 CB81 CB82 CB83 CB84 16V 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
2
3900P K 39N K 22U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
2
4 OPEN REF_A 25V 4
LD1 80 OHM 68.00173.0F1
GND
R565
VDD UB16 LD1117-3.3V PVDD
RD1 1.5K
GAIN_C SOGIN
3 2 PVDD
VDD VIN VOUT
GFILT 3.3K
GND
RD2 4
VO
1
OPEN 3K CD1 AVDD_AD GVMID
10P J VSYNC_C AVDD_AD C62 + C835 C63 C64 C65 C66 C68
VSYNC_C
1
R47 47 V33 C61 10U
HSYNC
GCOAST 0.1U 16V 0.1U 0.1U 0.1U 0.1U 0.1U
GCOAST
2
GBLKSPL 0.1U
GBLKSPL
25V Z
For Batman DVD noise solution PVDD PVDD
77.62203.0C1
OPEN 77.62203.0C1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
CN4 CN5 OPEN
MIDSCV
CLAMP
VSYNC
GND
GND
GND
HSYNC
GND
GND
GND
VDD
VDD
GND
VD
VD
VD
PVD
PVD
FILT
COAST
33P 33P GBE[7:0]
RN6 47 GBE[7:0]
41 20
8
C882 1.8P J AVDD_AD AVDD_AD GND GND ADBE0 GBE0
42 VD B0 19 5 4
BAIN_C R875 22 GBIN_A C78 GBIN 43 18 ADBE1 6 3 GBE1
3 BAIN_C BAIN B1 3
0.047U K 44 17 ADBE2 7 2 GBE2
GND B2 ADBE3 RN7 47 GBE3
45 VD B3 16 8 1
AVDD_AD 46 15 ADBE4 5 4 GBE4
AVDD_AD VD B4
47 14 ADBE5 6 3 GBE5
GAIN_C R876 22 GGIN_A C79 GGIN GND B5 ADBE6 GBE6
GAIN_C 48 GAIN B6 13 7 2
C883 1.8P J C67 0.047U K 49 12 ADBE7 8 1 GBE7
SOGIN SOGIN B7 GGE[7:0]
1000P K 50 U15 11
GND VDD V33 RN8 GGE[7:0]
51 AD9883AKST-140 10 47
AVDD_AD VD GND ADGE0 GGE0
AVDD_AD 52 VD G0 9 5 4
53 8 ADGE1 6 3 GGE1
RAIN_C R877 22 GRIN_A C80 GR IN GND G1 ADGE2 GGE2
RAIN_C 54 RAIN G2 7 7 2
C884 1.8P J 0.047U K 55 6 ADGE3 8 1 RN9 GGE3
SCL A0 G3 ADGE4 GGE4
SCL 56 SCL G4 5 5 4
SDA 57 4 ADGE5 6 3 GGE5
SDA SDA G5
GVREF 58 3 ADGE6 7 2 GGE6
AVDD_AD AVDD_AD REF BYPASS G6 ADGE7 GGE7
59 2 8 1
SOGOUT
VD G7
DATACK
60
HSOUT
1
VSOUT
GND GND
5
33P
33P
GND
GND
GND
GND
VDD
VDD
VDD
CN2
CN3
C81 47
VD
R7
R6
R5
R4
R3
R2
R1
R0
77.62203.0C1
0.1U 77.62203.0C1 OPEN
4
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
OPEN
GRE[7:0]
ADRE7
ADRE6
ADRE5
ADRE4
ADRE3
ADRE2
ADRE1
ADRE0
2 GRE[7:0] 2
V33
AVDD_AD AVDD_AD
ADCK
BAIN_C R793 330 BAIN_V V33 47 RN10

ADSOG
BAIN_C BAIN_V
V33 GRE0
ADHS
ADVS
1 8
2 7 GRE1
3 6 GRE2
4 5 GRE3
4
3
2
1
RAIN_C R792 330 RAIN_V RAIN_V 1 8GRE4

RAIN_C
RN12 2 7GRE5
47 3 6GRE6
4 5GRE7
GAIN_C R791 330 GAIN_V GAIN_V
GAIN_C
5
6
7
8
5
33P
33P
47 RN11
CN7
CN8
15P K C901
15P K C902
15P K C903
OPEN
77.62203.0C1 OPEN
4
R812 22
GCLK
77.62203.0C1
Benq Corporation
GFBK Project Code Model Name OEM/ODM Model Name
GFBK
GHS
GHS C802 99.J8677.001 PB6100 <OEM/ODM>
1 GVS 1
GVS 33P J
OPEN Title
MAIN BOARD
8
33P

CN6
OPEN <Size> 1
77.62203.0C1 48.J8601.S04 S04 99.J8677.B12-C3-304-004
1

A B C D E
A B C D E
OPEN
U17 3.3V
VPP 3.3V U21
26 CE VPP 13 3 2 3.3V
ROMOEn 28 3.3V 2N3906 Q10 1 8
ROMOEn OE A0 VCC
ROMWEn 11 37 R86 C90
ROMWEn WE VCC
12 C305 VP3 2 7 C94
RESETn
1
ROMWPn RP 0.1U A1 WP 0.1U
14 WP
47 29 D0 0.1U 3 6 25V Z
4 3.3V BYTE D1 D1 1K R87 A2 SCL 4
D2 31
A1 25 33 D2 1K 4 5 SCL
A0 D3 GND SDA SCL
A2 24 35 D3 SDA
A1 D4 SDA
A3 23 38 D4 VP2 AT24C16N-10SI-1.8
A4 A2 D5 D5
22 A3 D6 40
3
A5 21 42 D6 10K R88 1M
A6 A4 D7 D7 Q11
20 A5 D8 44 1VP1 VPPON VPPEN
VPPEN
A7 19 30 D8 2N3904
A8 A6 D9 D9 R89 R90
18 32
2
A9 A7 D10 D10 3.3K
8 A8 D11 34
A10 7 36 D11
A11 A9 D12 D12
6 A10 D13 39
A12 5 41 D13
A13 A11 D14 D14
4 A12 D15 43
A14 3 45 D15
A15 A13 D16
2 A14
A16 1 D[0:15]
A15 D[0:15]
A17 48 46
A18 A16 GND
17 A17 GND 27
A19 16
A[19:1] A18
A[19:1]
AT49BV8192A(T)
FCEn CP5
3.3V 3.3V 0.1U
3 3
25V Z
RA30 RB1
1
3.3K 10K
JP1 UI4
5 CD RESET 1 2 4 RB3 47 RESET RESET
A1 1 26 D2 R330 1K C330
A2 1 26 D3
2 2 27 27 4 NC
A3 3 28 D4 CA30 220P K 74V1G14S
3
A4 3 28 D5 220P UI5
4 4 29 29 3.3V 2 VCC GND 3
A5 5 30 D6
A6 5 30 D7 CI1 NCP302LSN31T1
6 6 31 31
A7 7 32 D8 0.1U
A8 7 32 D9
8 8 33 33
A9 9 34 D10 RB2 47 RESETn RESETn
A10 9 34 D11
10 10 35 35
A11 11 36 D12
A12 11 36 D13
12 12 37 37 OPEN
A13 13 38 D14 VDD
A14 13 38 D15
14 14 39 39
A15 15 40 3.3V 74AHC1G32
15 40 VDD
A16 16 41 3.3V
A17 16 41 A0
17 17 42 42 3.3V 5 VCC A 1 A0
2 A18 18 43 2
A19 18 43 BHENn
19 19 44 44 B 2 BHENn
ROMOEn 20 45
ROMOEn 20 45
ROMWEn 21 46 4 3
ROMWEn 21 46 Y GND
R99 3.3K 22 47
3.3V 22 47
R98 3.3K 23 48 ICEn UI3
D0 23 48 3.3V
24 24 49 49 UI2
D1 25 50
25 50
5 VCC A 1
20L2055050 2 ROMWEn
B ROMWEn
4 Y GND 3
PIXELWORKS SDK FOR TOSHIBA
3.3V 74AHC1G32
CP4
GND
25V Z 0.1U
5
Benq Corporation
UI1 SW3
1 4
2 4 2 3
74V1G14S 6240019001
1 99.J8677.001 PB6100 <OEM/ODM> 1
3
Title
MAIN BOARD

<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
A B C D E
RN18 47
GFBK DCLK W12 R DK 5 4 DCLK

3.3V 3.3V V13 R DV 6 3
A0 DVS DVS
DHS U13 R DH 7 2 DHS
H19 V25 P1 8 1
GCLK GCLK A0 A[19:1] DEN
G20 H17 P2 A1 Y15 R DE
GPENSOG GFBK R101 R102 RESET A1 A2 DEN
GVS J17 GVS GREF H18 RESET E3 RESET A2 N3
G19 F19 2K 2K N4 A3 RN19 47
GHS GHS GBLKSPL GBLKSPL A3
F20 RX1 MCKEXT W13 R1 A4 R19 RRE0 5 4 DRE0
GCOAST GCOAST MCKEXT MCKEXT A4 DRE0
1M F DCKEXT Y13 R2 A5 T20 RRE1 6 3 DRE1 DRE[7:0]
DCKEXT DCKEXT A5 DRE1
T1 A6 R18 RRE2 7 2 DRE2
4 X700 X700 A6 A7 DRE2 RRE3 8 DRE3 4
GRE[7:0] P3 XTALI A7 T2 DRE3 R17 1
GRE0 M20 X701 X701 P4 R3 A8 T18 RRE4 5 4 DRE4
GRE1 GRE0 XTALO A8 A9 DRE4 RRE5 6 DRE5
N19 GRE1 A9 U1 DRE5 U19 3
GRE2 N18 RX2 U2 A10 T17 RRE6 7 2 DRE6
GRE3 GRE2 1M F RXD A10 A11 DRE6 RRE7 8 DRE7
N17 GRE3 RXD C1 RXD A11 R4 DRE7 V20 1
GRE4 N20 TXD D3 T3 A12 RN21 47 47 RN20
GRE4 TXD TXD A12
GRE5 P20 V1 A13 U18 RGE0 5 4 DGE0
GRE6 GRE5 IRR CVR A13 A14 DGE0 RGE1 6 DGE1 DGE[7:0]
P19 GRE6 IRRCVR E4 IRRCVR0 A14 W1 DGE1 V19 3
GRE7 R20 KEYSTONE RK6 0 D2 V2 A15 W20 RGE2 7 2 DGE2
GRE7 IRRCVR1 A15 A16 DGE2 RGE3 8 DGE3
GGE[7:0] OPEN A16 T4 DGE3 W19 1
GGE0 F18 SDA SDA C2 U3 A17 Y20 RGE4 8 1 DGE4
GGE1 GGE0 SCL PORTA0 A17 A18 DGE4 RGE5 7 DGE5
E19 GGE1 SCL B1 PORTA1 A18 Y1 DGE5 V17 2
GGE2 E20 AUDIO_VOL R103 47 AUDIO_VOLA B2 W2 A19 U16 RGE6 6 3 DGE6
GGE2 AUDIO_VOL PORTA2 A19 DGE6
GGE3 J18 AUDIO_MUT R104 2K AUDIO_MUTA A1 W18 RGE7 5 4 DGE7
GGE3 AUDIO_MUT PORTA3 D[0:15] DGE7
GGE4 H20 LAMPLITZ RN23 5 4 C4 F4 D0 RN24 47 47 RN22
GGE4 LAMPLITZ PORTA4 D0
GGE5 J19 CONTROL 6 3 D5 F3 D1 Y19 RBE0 8 1 DBE0
GGE5 CONTROL PORTA5 D1 DBE0
GGE6 J20 VPPEN 7 2 B3 U22D E1 D2 U22C Y18 RBE1 7 2 DBE1 DBE[7:0]
GGE6 VPPEN PORTA6 D2 DBE1
GGE7 K19 8 1 A2 F2 D3 V16 RBE2 6 3 DBE2
GGE7 RN25 47 PORTA7PW166-10TK D3 D4 PW166-10TK DBE2 RBE3 5 DBE3
GBE[7:0] D4 F1 DBE3 U15 4
GBE0 D16 U22A POWERON POWERON 5 4 A3 G2 D5 Y16 RBE4 8 1DBE4
GBE1 GBE0 RESETZ PORTB0 D5 D6 DBE4 RBE5 7
A18 GBE1 VCLK D12 VCLK RESETZ 6 3 C5 PORTB1 Misc D6 G1 Display Port DBE5 V15 2DBE5
GBE2 C17 PW166-10TK 7 2 D6 H1 D7 W16 RBE6 6 3DBE6
GBE3 GBE2 PORTB2 D7 D8 DBE6 RBE7 5
B18 GBE3 VPEN C13 VPEN 8 1 B4 PORTB3 D8 H4 DBE7 W15 4DBE7
GBE4 A19 Graphics Port 47 A4 H3 D9 RN26 47
3
GBE5 GBE4 PORTB4 D9 D10 DRO0
3
B19 GBE5 VVS A14 VVS C6 PORTB5 D10 H2 DRO0 Y12
GBE6 A20 B14 KEYSTONE RD5 0 B5 J1 D11 W11 DRO1 DRO[7:0]
GBE6 VHS VHS PORTB6 D11 DRO1
GBE7 D18 A15 ECO-MODE RW703 2K A5 J2 D12 Y11 DRO2
GBE7 VFIELD VFIELD PORTB7 D12 DRO2
FAN_P R334 47 J4 D13 U10 DRO3
VY[7:0] D13 DRO3
K20 V Y0 D8 R808 47 J3 D14 V10 DRO4
GRO0 VY0 KEY8 D14 DRO4
L17 V Y1 C8 U22B K1 D15 W10 DRO5
GRO1 V Y2 VY1 D15 DRO5 DRO6
L18 GRO2 B7 VY2 DRO6 Y10
L19 V Y3 A7 PW166-10TK M3 W9 DRO7
GRO3 V Y4 VY3 RD WRn DRO7
L20 GRO4 B8 VY4 WR M4 TP4
M18 V Y5 D9 Video Port N2 Y9 DGO0
GRO5 VY5 BHEN BHENn DGO0
M17 V Y6 C9 M1 W8 DGO1 DGO[7:0]
GRO6 VY6 ROMOE ROMOEn DGO1
M19 V Y7 A8 L2 V8 DGO2
GRO7 VY7 ROMWE ROMWEn DGO2
VUV[7:0] L1 RAMOEn U8 DGO3
RAMOE TP5 DGO3
E17 VUV0 B9 D13 K2 RAMWEn Y8 DGO4
GGO0 VUV0 TMS CPUTMS RAMWE TP6 DGO4
C19 VUV1 A9 A6 M2 CS0n Y7 DGO5
GGO1 VUV1 TCK CPUTCK CS0 CS0n DGO5
B20 VUV2 B10 N1 W7 DGO6
GGO2 VUV2 CS1 CS1n DGO6
C20 VUV3 A10 W3 Y5 DGO7
GGO3 VUV3 TDO CPUTDO DGO7
E18 VUV4 D11
GGO4 VUV5 A11 VUV4 R107 0 X702 RD4 0 DBO0
F17 GGO5 VUV5 A13 MODE0 EXTINT E2 KEYSTONE DBO0 V6
D19 VUV6 C12 V3P R105 0 X703 U5 U6 DBO1 DBO[7:0]
GGO6 VUV7 B13 VUV6 R106 0 X704 MODE1 DBO1 DBO2
D20 GGO7 VUV7 B6 MODE2 DBO2 W5
D1 Y4 DBO3
NMI DBO3 DBO4
B15 GBO0 DBO4 V5
2 A16 R108 Y3 DBO5 2
GBO1 1K DBO5 DBO6
C15 GBO2 DBO6 V4
D15 For 164B 10TK Y2 DBO7
GBO3 DBO7
B16 GBO4
A17 GBO5
C16 V25 V25 V25 U61
GBO6 VDD V25
B17 GBO7 V3P V3P V3P 3 2
1 VDD VIN VOUT
1
3.3V C96
GND
1
V25 V25P + C99 C100 + C603

L13 V3P + C95 22U
BEAD 10U M C97 C98 10U M 0.1U 0.1U C601 LM317M 25V
2
2
27 R109 6.3V 0.1U 0.1U 6.3V U16_A
3.3V
2
4.7U Z R602 2K
R603
G18
C10
C11
C14
C18
U20
B12
K18
P18
V14
V11
V18
V12
Y14
Y17
G3
C3
C7
V3P V3P V3P V3P V25 V25 V25 V25 V25 V25 2K
V7
V9
Y6
V3
K3
L3
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VCC10
VCC11
VCC12
VCC13
VCC14
VDD10
Benq Corporation
C101 C102 C103 C104 C105 C106 C107 C108 C109 C110
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
PW166-10TK U22E Power and Ground Project Code Model Name OEM/ODM Model Name
1 99.J8677.001 PB6100 <OEM/ODM> 1
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
V3P V3P V3P V3P V25 V25 V25 V25 V25 V25 Title
MAIN BOARD
C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 Size PCB P/N PCB Rev. Document Number R ev.
D4
D7
U9
U7
U4
B11
A12
G17
K17
P17
D10
D14
D17
T19
U17
U14
U12
U11
L4
K4
G4
W17
W14
W6
W4
<Size> 1
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 48.J8601.S04 S04 99.J8677.B12-C3-304-004
GND Tuesday, October 07, 2003

Date: Sheet 10 of 20
A B C D E
A B C D E
3.3V
4 3.3V 4
3.3V
C121
0.1U
3.3V
U24
C122 7 2
U25 0.1U OE VDD
POWERON 7 2 6 130MHz/41MHz
POWERON OE VDD S0
4 5 RMCK R112 22 MCKEXT
S1 CLK MCKEXT
6 S0 65MHz
4 5 RD CK R113 22 DCKEXT Y2 U24_X1 1
S1 CLK DCKEXT X1
16.257MHZ U24_X2 8 3 L28 Z10
Y3 U25_X1 X2 GND
1 X1
U25_X2 8 3 ICS501 68.00129.0D1
X2 GND R114
16.257MHZ ICS501 820K
R115 L29 Z10
GND C123 C124
68.00129.0D1 10P D 10P D
820K
C125 C126
10P D 10P D
3 3
OPEN
3.3V
U18 G751-2
OPEN
5 A2 SDA 1 SDA
6 2 3.3V
A1 SCL SCL
VDD RK7 0
7 A0
3.3V RK8 0
3 S01 version I2C bus reversed and Pin8 connected to VDD CP6
O.S. new version change to 3.3V RK9
8 0.1U 4.7K
GND
VCC 3.3V
25V Z
U20
5
2
C89 2
4
0.1U 1
KEYSTON_A
4 RK1 0 KEYSTONE
2
VDD 74AHC1G08
3
RK4 OPEN
RK5 OPEN
VDD
7 XFILT
RK3 OPEN
6 5 R93 0 KEYSTON_A
YFILT XOUT
1 ST
2 T2
R95 4 R92 OPEN
R94 YOUT
8 VDD
4.7K
Benq Corporation
3 COM VDD
680K RK2 OPEN
C91 C92 C93 U19
CK1 0.1U Project Code Model Name OEM/ODM Model Name
470N M470N M0.1U
1 99.J8677.001 PB6100 <OEM/ODM> 1
Title
ADI: RK1, RK2, RK3, RK4, R92 OPEN MAIN BOARD
MEMSIC: R93, C91, R94, R95, R92, RK1, OPEN; RK2, RK3, RK4 0ohm
Note: keystone function IC and thermal senser IC, those two component should be placement as closed as possible. Size PCB P/N PCB Rev. Document Number R ev.
<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
A B C D E
VDD
VDD
4 C812 IR receiver circuit 4
R744
TP231 0 0.1U
LED[5:0] RN725 120 OHM TP232 FM-6038LM-5A
LED0 8 1 C811 0.1U U6
LED1 7 2 TP34 VDD TP47
LED2 6 3 240 OHM TP48 J813
LED3 5 4 TP35 TP233 L801 R857 0 TP49
1 IRRCVR2 1
LED4 2 L802 R858 0 2
8 1
GND
VDD
OUT
TP36 3 3
C815
LED5 R22 240 OHM
VS
7 2 4 4
TP37
470P K C816
6 3 10K
5
CN701470P
5 4 20L2021004
3
2
1
TP38 6
8
8
470P K
7
470P
CN702
RN728 120 OHM VDD R15 47 IRV CC IROUT R23 510
8 IRRCVR1
TP39 9 C12
1
1
TP40 10 VDD R813
KEY0 RN726 120 OHM 77.62203.0C1 TP41 11 4.7U Z
KEY1 TP42 12 0
8 1 13
KEY2 7 2 TP43 OPEN
KEY3 TP44 14
6 3 15
KEY4 5 4 TP45 U7
16
5
KEY5 8 1 TP46 TP947
3
KEY6 7 2 TP801 17 TP948 J913 IRRCVR1 1
3
18 TP949 IRRCVR1
KEY7 6 3 IROUT R957 0 1 4 IRR CVR
19 IRRCVR
5 4 2 IRRCVR2 2
20 IRRCVR2
IRV CC R958 0 3
KEY[7:0]
470P
RN727 120 OHM J4 20L2021020 74AHC1G08
3
8
CN704 470P
KEY8 KEY8
R745 20D0049103
C801 0
CN703
470P K In version 2 PCB the power for this block is VDD_D but it
1
is floating. I version 3 schematic we change to VDD net

for this block power source.
77.62203.0C1 77.62203.0C1
3.3V
3.3V
D[0:7] D[0:7]
KEY[7:0] D[0:7] D[0:7]
2 KEY[7:0] 3.3V 2
LED[5:0]
C127 CP7
0.1U 0.1U
U28
20
20
U27
KEY0 2 18 D0 D0 3 2 LED0
VCC
VCC
KEY1 1A1 1Y1 D1 D1 D1 Q1 LED1
4 1A2 1Y2 16 4 D2 Q2 5
KEY2 6 14 D2 D2 7 6 LED2
8 1A4 1Y4 12 8 D4 Q4 9
KEY4 11 9 D4 D4 13 12 LED4
13 2A2 2Y2 7 14 D6 Q6 15
KEY6 15 5 D6 D6 17 16
KEY7 2A3 2Y3 D7 D7 D7 Q7
17 2A4 2Y4 3 18 D8 Q8 19
1 11
GND
CS0n 1G CS1n CLK

19
GND
CS0n 2G
RESETn 1 CLR
Benq Corporation
74AHC244
10
74LVC273
GND
10

1 99.J8677.001 PB6100 <OEM/ODM> 1
Title
MAIN BOARD

<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
A B C D E
2V5_D 3.3V_D
U29E
4 DDP1000 BULK DECOUPLING CAPS DDP1000 DECOUPLING FOR +3.3V DDP1000 DECOUPLING FOR+2.5V 4
2V5_D AC2 P2P5V P3P3V AB21 3.3V_D

3.3V_D 3.3V_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D AB17 AB20
3.3V_D 3.3V_D P2P5V P3P3V
AB16 P2P5V P3P3V AB19
1
C128 C129 C130 C131 C132 C133 C134 C135 AB12 AB7
+ C136 + C137 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U P2P5V P3P3V
10U M 10U M AB10 AA22
6.3V 6.3V P2P5V P3P3V
U22 AA5
2
P2P5V P3P3V
U5 P2P5V P3P3V Y22
T22 P2P5V P3P3V Y5
3.3V_D 3.3V_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D T5 W22
P2P5V P3P3V
R22 P2P5V P3P3V W5
R5 P2P5V P3P3V H22
C138 C139 C140 C141 C142 C143 C144 C145 R1 H5
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U P2P5V P3P3V
M22 P2P5V P3P3V G22
M5 P2P5V P3P3V G5
L22 P2P5V P3P3V F22
L5 P2P5V P3P3V F5
2V5_D K22
3.3V_D 3.3V_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D P2P5V
K5 P2P5V
1
E21 P2P5V GND AF26
+ C146 E20 AF25
10U M C147 C148 C149 C150 C151 C152 C153 C154 P2P5V GND
E19 P2P5V GND AF21
2 6.3V 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U E17 AF16
P2P5V GND
E16 P2P5V GND AF15
E15 P2P5V GND AF11
E12 P2P5V GND AF6
2V5_D 2V5_D E11 AF1
P2P5V GND
E10 P2P5V GND AE25
E8 P2P5V GND AE2
C155 C156 E7 AE1
0.1U 0.1U DDP1000-C
P2P5V GND
E6 P2P5V GND AD24
B15 P2P5V GND AD3
GND AC23
B26 GND GND AC4
B25 GND
3 B19 GND GND P5 3
B17 GND GND N22
B14 GND GND N5
B13 GND GND L26
B11 GND GND L1
B9 GND GND J22
3.3V_D B8 J5
GND GND
B7 GND GND F26
U29D B5 GND GND F1
B2 GND GND E22
A26 GND GND E18
H1 SR16STROBE SR16STROBE A21 E14
3.3V_D R120 R121 R122 SR16STRB S R16OEZ GND GND
SR16OEZ J3 SR16OEZ A16 GND GND E13
10K 10K 10K A11 E9
GND GND
A6 GND GND E5
J1 G1 SR16A DDR3 SR16ADDR3 A2 D23
USBCLK SR16ADDR3 SR16A DDR2 GND GND
AE19 USBDATP SR16ADDR2 H3 SR16ADDR2 A1 GND
AC19 J4 SR16A DDR1 SR16ADDR1 D18
SD A0 USBDATN SR16ADDR1 SR16A DDR0 GND
SDA0 AC22 SDA0 SR16ADDR0 J2 SR16ADDR0 AB22 GND GND D16
R533 R542 SCL0 S CL0 AE24 H4 SR16MODE1 SR16MODE1 AB18 D14
0 OPEN SCL0 SR16MODE1 SR16MODE0 GND GND
SR16MODE0 H2 SR16MODE0 AB14 GND GND D12
AB13 GND GND D10
K2 SR16SEL1 SR16SEL1 AB9 D6
SR16SEL1 SR16SEL0 GND GND
SR16SEL0 K4 SR16SEL0 AB5 GND GND D4
AB23 APLLMD1 AA26 GND GND C24
AC24 APLLMD0 AA1 GND GND C18
F2 MOSCN DMDBIN3 E4 V22 GND GND C17
MOSC MOSC F3 B1 V5 C14
COSC MOSC DMDBIN2 GND GND
COSC AD25 COSC DMDBIN1 C2 T26 GND GND C11
2V5_D PLL-VCCA AE26 D3 T2 C8
L14 CRYSTAL EN PLL_VCCA DMDBIN0 GND GND
G4 CRYSTALEN T1 GND GND C6
120 OHM L3 P22 C5
SR16VCCEN Extra test point request by TI and GND GND
DMDVCCEN L4 GND C3
K1 optical team phase-in at LP2
C157 C158 R124 VCC2EN stage.
VBIASEN K3 P11 GND GND R11
0.1U 0.1U OPEN L2 P12 R12
D RCGPDZ VRSTEN GND GND
DRCGPDZ R24 DIO0 P13 GND GND R13
S CPENZ R23 B23 1 TP33 P14 R14
2 SCPENZ DIO1 TSTPNT3 GND GND 2
P23 B22 1 TP32 P15 R15
DIO2 DDP1000-C TSTPNT2 TP31 GND GND
R25 DIO3 TSTPNT1 D21 1 P16 GND GND R16
SCP DI T24 A23 1 TP30 N11 M11
SCPDI DIO4 TSTPNT0 GND GND
S CPDO T23 N12 M12
SCPDO DIO5 GND GND
SCPCK U26 D2 R490 47 CKMTR1 CKMTR1 N13 M13
SCPCK DIO6 OCLKA GND GND
T25 DIO7 OCLKB E3 N14 GND GND M14
U24 DIO8 N15 GND GND M15
R124 MOSC Configuration V26 P26 N16 M16
DIO9 VSOUTZ FSD 16 GND GND
U23 DIO10 FSD16 N24 FSD16 T11 GND GND L11
U25 DIO11 DMDLD M3 T12 GND GND L12
Install Crstal V24 N2 T13 L13
DIO12 DCLKREF GND GND
W26 DIO13 T14 GND GND L14
Non Install Oscillator
BINSEL0 BINSEL0 V25 D1 PUM-ARSTZ PUM-ARSTZ T15 L15
BINSEL1 DIO14 PUM_ARSTZ EXT-ARSTZ GND GND
BINSEL1 V23 DIO15 EXT_ARSTZ F4 EXT-ARSTZ T16 GND GND L16
W24 DIO16 EXT_ARST E2 A10 GND
MTRSELZ Y26 A15
MTRSELZ DIO17 GND
MTRCLK W25
MTRCLK DIO18
MTRDATA W23 AB24 R733 0
MTRDATA DIO19 DIO31
FLASH-BUSYZ FLASH-BUSYZ Y24 AD26 ECO-MODE ECO-MODE
DIO20 DIO30
Y25 DIO21 DIO29 AC25 OPEN
GND AB26 DIO22 DIO28 AB25
IR QZ Y23 AA23 C WTACH
IRQZ DIO23 DIO27 CWTACH
AC26 CWINDEX
DIO26 CWINDEX P3P3V:AB21,AB20,AB19,AB8,AB7,AB6,AA22,AA5,Y22,Y5,W22,W5,H22,H5,G22,G5,F22,F5
DIO25 AA25
AA24 GND:AF26,AF25,AF21,AF16,AF15,AF11,AF6,AF1,AE25AE2,AE1,AD24,AD3,AC23,AC4,AB22,AB18
DIO24 GND:AB14,AB13,AB9,AB5,AA26,AA1,V22,V5,T26,T2,T1,P22,P5,N22,N5,L26,L1,J22,J5,F26
GND:F1,E22,E18,E14,E13,E9,E5,D23,D18,D16,D14,D12,D10,D6,D4,C24,C18,C17,C14,C11
GND:C8,C6,C5,C3,B26,B25,B19,B17,B14,B13,B11,B9,B8,B7,B5,B2,A26,A21,A16,A11,A6,A2,A1
P2P5V:AC2,AB17,AB16,AB15,AB12,AB11,AB10,U22,U5,T22,T5,R22,R5,R1,M22,M5,L22,L5
P2P5V:K22,K5,E21,E20,E19,E17,E16,E15,E12,E11,E10,E8,E7,E6,B15,
GND:P11,P12,P13,P14,P15,P16,N11,N12,N13,N14,N15,N16,T11,T12,T13,T14,T15,T16,
GND:R11,R12,R13,R14,R15,R16,M11,M12,M13,M14,M15,M16,L11,L12,L13,L14,L15,L16,A10,A15
1 1
Benq Corporation
99.J8677.001 PB6100 <OEM/ODM>
Title
MAIN BOARD
Size P CB P/N PCB Re v. Document Number Rev.

<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004
D ate: Tuesday, October 07, 2003 Sheet 13 of 20

A B C D E
A B C D E
FLDATA[0:15]
U29A U30 3.3V_D
AD12 FLADDR19 D4 G4
FLADDR19 FLADDR18 A19 VDD
FLADDR18 AE13 C3 A18
AF12 FLADDR17 B2
FLADDR17 FLADDR16 A17 FLDATA15
FLADDR16 AF13 E6 A16 DQ15/A-1 G6
AD14 FLADDR15 D6 F5 FLDATA14 3.3V_D
4 FLADDR15 FLADDR14 A15 DG14 FLDATA13 4
FLADDR14 AD13 C6 A14 DG13 G5 3.3V_D
FLDATA0 AE23 AF14 FLADDR13 A6 F4 FLDATA12
FLDATA1 FLDATA0 FLADDR13 FLADDR12 A13 DG12 FLDATA11 C159
AE22 FLDATA1 FLADDR12 AE14 B6 A12 DG11 G3
FLDATA2 AC21 AC15 FLADDR11 D5 F3 FLDATA10 0.1U K
FLDATA3 FLDATA2 FLADDR11 FLADDR10 A11 DG10 FLDATA9
AF23 FLDATA3 FLADDR10 AD15 C5 A10 DG9 G2
FLDATA4 AE21 AC14 FLADDR9 A5 F2 FLDATA8
FLDATA5 FLDATA4 FLADDR9 FLADDR8 A9 DG8 FLDATA7 FLASH +3.3V DECOUPLING CAPS
AD21 FLDATA5 FLADDR8 AE15 B5 A8 DG7 E5
FLDATA6 AC20 AD16 FLADDR7 A2 H5 FLDATA6
AF22 FLDATA7 FLADDR6 AC16 C2 A6 DG5 E4
FLDATA8 AE20 AF17 FLADDR5 D2 H4 FLDATA4
AD20 FLDATA9 FLADDR4 AE16 B1 A4 DG3 H3
FLDATA10 AF20 AD17 FLADDR3 A1 E3 FLDATA2
AD19 FLDATA11 FLADDR2 AF18 C1 A2 DG1 H2
FLDATA12 AC18 AC17 FLADDR1 D1 E2 FLDATA0
FLDATA13 FLDATA12 FLADDR1 FLADDR0 A1 DG0
AE18 FLDATA13 FLADDR0 AE17 E1 A0 NC C4
FLDATA14 AF19 D3
FLDATA15 FLDATA14 NC
AD18 FLDATA15 NC B3
GND H6
FL_OE AD23 B4 RESET GND H1
AD22 3.3V_D
FL_WE
FL_CS AF24 F6 BYTE
FLASH INTERFACE
FL-OEZ G1 A3 FLASH-BUSYZ FLASH-BUSYZ
3
FL-WEZ OE RY/BY 3
A4 WE
DDP1000-C FL-CSZ F1 CE
AM29LV800BB-120 GND:H6,H1
P3P3V:G4
PUM-ARSTZ NC:C4,B3,D3
PUM-ARSTZ
U29B RQ[0:7]
RQ[0:7]
DVS DVS R26 D13 RQ7
D HS VSYNCZ RQ7 RQ6
DHS N25 HSYNCZ RQ6 C12
DCLK DCLK N23 A12 RQ5
VREF-RDRAM D EN WCLK RQ5 RQ4
DEN M23 IVALID RQ4 A13
R125 110F 3.3V_D M24 C13 RQ3
OLACT RQ3 RQ2
VREF-RDRAM E23 SYNCVALID2/DI2 RQ2 A14
N26 C15 RQ1
FSD16 CTRL RQ1 RQ0 DQA[0:8]
FSD16 M26 FLDSYNC RQ0 D15 DQA[0:8]
C160 C161 LAMPLITZ R126 47 P25
0.1U 0.1U LAMPLITZ LAMPSTAT
LAMPEN R127 47 P24 A3 DQA8
LAMPEN LAMPCTRL DQA8
2 B4 DQA7 2
DQA7 DQA6
DQA6 A4
POWERON POWERON E1 B6 DQA5
RESETZ PWRGOOD DQA5 DQA4
RESETZ G3 SYSRSTZ DQA4 D7
A5 DQA3
DQA3 DQA2
DQA2 C7
2V5_D D9 D8 DQA1
RD_VREF1 DQA1 DQA0 DQB[0:8]
D11 RD_VREF0 DQA0 A7 DQB[0:8]
2V5_D B12 RD_AVDD0
B10 A20 DQB8
RD_AVDD1 DQB8 DQB7
DQB7 C19
3.3V_D B18 DQB6
C162 C163 TP9 TDO2 C1 DQB6 DQB5
1 TDO2 DQB5 A19
0.1U 68P J R128 10K TMS2 C23 D17 DQB4
TP10 TDO1 M4 TMS2 DQB4 DQB3
1 TDO1 DQB3 A18
R129 10K TMS1 B24 B16 DQB2
GND TMS1 DQB2
TP11 1 TD1 C22 A17 DQB1
TP12 TRSTZ D5 TDI DQB1 DQB0
1 TRSTZ DQB0 C16
TP13 1 TCK C4
TCK
DDP1000-C RD_SCK
RD_CMD
A22
B20
SCK
CMD
SCK
CMD
Benq Corporation
B3 C20 SIO SIO Project Code Model Name OEM/ODM Model Name
R130 10K ICTSENZ PTSTENZ RD_SIO CFM
A24 ICTSENZ RD_CFM A8 CFM <OEM/ODM>
1 CFMN 99.J8677.001 PB6100 1
AF2 IBMT_RI RD_CFMN C9 CFMN
AD2 C10 CTM CTM Title
IBMT_LT RD_CTM CTMN
K25 A9 CTMN MAIN BOARD
POSTST RD_CTMN U5-C21 R131 39.2F
D19 LSSDEN PCLKM C21 PCLKM
B21 U5-B21 R132 39.2F Size PCB P/N PCB Rev. Document Number R ev.
SCLKN SCLKN
D20 U5-D20 R133 39.2F <Size>
REFCLK REFCLK 48.J8601.S04 S04 99.J8677.B12-C3-304-004 1
RAMBUS, JTAG, CUSTOMER INPUT
A B C D E
A B C D E
4 4
US2 VDD_D
3.3V_D CWINDEXA CWINDEXA 1 5
UY1 A VCC
7 2 L16 120 OHM 3.3V_D 2
OE VDD B
3.3V_D 6 3 4 CWINDEX CWINDEX
S0 CK100M R136 39.2F MOSC GND Y
4 S1 CLK 5 MOSC
C493 74AHC1G32
1 X1
Y5 8 3 L27 Z10 22P J
X2 GND
20MHZ
ICS501 68.00129.0D1
RY1 820K
C166 C167
10P J 10P J
3 3
3P3V
open
R518
0
TP53
TP54 JS1
TP55
R920
VDD_D CWSENSOR
3 3.3V_D
OPDIODE 2
VDD_D 1 0 R927 3P3V
RS5
20L2021003 0
180
RS6 RS7 C921 C909
75K 2K 0.1U
4.7u 1 8
RS1 XIN/CLKIN XOUT
2 VSS VDD 7
10K 3 6
CWINDEXA S1 FRSEL
CWINDEXA Y901 4 S0 SSCLK 5
US1
2 3 2
R918
RS4 RS3 1 5 4
C169 10K 330K OUTPUT V- U902 CY25812SCT
C168 2
0.1U 10P J V+
2
SENSER_A 3 4 2.5VREF 1 0 CK60M R913 39.2F COSC COSC
INPUT+ INPUT-
LMC7225 3P3V
C170 RS2 30MHZ C926
0.1U 6.8K OPEN
C930 27P J 10P J
GND
C910 27P J
Benq Corporation
1 99.J8677.001 PB6100 <OEM/ODM> 1
Title
MAIN BOARD

<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
A B C D E
VDRCG 2V5_D VTERM
RN31 39 RN32 39
5 4 DQB1 DQB2 5 4
VTERM
1
6 3 RQ3 DQB6 6 3
+ C171 7 2 RQ2 DQB3 7 2
R138 R139 R140 150U C172 C173 C174 C175 8 1RN33 39 RQ6 DQB8 8 1
10K 10K 10K 6.3V 0.1U 0.1U 0.1U 0.1U 5 4 RQ0
2
4 RQ1 4
6 3
7 2 RQ4 RN34 39
VDRCG 8 1 RQ7 DQB0 5 4
DQB4 6 3
RDRAM VDD DECOUPLING CAPS DQB5 7 2
DQB7 8 1
U31 CDCR83
REFCLK 2 REFCLK
SCLKN 7 SYNCLKN CLK 20 U15-20 R141 110F CTM
6 3 CTM DQB[0:8]
PCLKM PCLKM VDD RQ[0:7] DQB[0:8]
RQ[0:7]
VDD 9
MULT0 15 16 R142
DRCGPDZ MULT0 VDD
MULT1 14 22 56.2F
MULT1 VDD
NC 19
24 GND:4,5,8,17,21
S0 VDRCG:3,9,16,22 U15-C76 K4R271669D-TCS8
23 S1
13 NC:19 C176 RQ0 G1 J1 DQB8
S2 10P J RQ1 RQ0 NC1 DQB7
GND 4 F2 RQ1 DQB7 J7
12 5 C177 RQ2 F6 H2 DQB6
2V5_D STOPZ PWRDNB GND R144 0.1U RQ3 RQ2 DQB6 DQB5
11 STOPB GND 8 F7 RQ3 DQB5 H6
R143 10K 17 56.2F RQ4 F1 H7 DQB4
GND RQ5 RQ4 DQB4 DQB3
2V5_D 1 VDDIR GND 21 E7 RQ5 DQB3 H1
RQ6 E6 G2 DQB2
RQ6 DQB2
3 10 VDDIPD CLKB 18 U15-18 R145 110F CTMN
CTMN
RQ7 E2 RQ7 DQB1 G6 DQB1
3
G7 DQB0
SIO1 DQB0
J3 SIO1
C178 C179 SIO0 J5 C1 DQA0
0.1U 0.1U SIO SIO0 DQA0
CMD A5 C2 DQA1
CMD CMD DQA1
SCK A3 C6 DQA2
GND SCK SCK DQA2
B1 DQA3 R146 39.2F
CTM DQA3 DQA4
CTM E1 CTM DQA4 B7
CTMN D1 B6 DQA5
CTMN CTMN DQA5
R147 CFM CFM C7 U32 B2 DQA6
2V5_D 10K CFMN CFM DQA6 DQA7
D7 CFMN DQA7 A7
OPEN D2 A1 DQA8 R148 39.2F
3.3V_D VDRCG R149 VREF NC2
CDCR83 (DRCG) 3.3V DECOUPLING CAPS 39.2F A2 D5
VCMOS GNDA
L17 J2 VCMOS GND A6
VDRCG R150 R151 D6 B3
3.3V_D VDDA GND
120 OHM U7-C75 B5 C5 RN35 39
P2P5V GND
1
75F C3 D3 DQA2 5 4
C180 + C181 C182 C183 C184 C185 C186 P2P5V GND DQA0
E5 P2P5V GND E3 6 3
0.1U 10U M 0.1U 68P J 0.1U 68P J 75F 0.1U R152 F3 F5 DQA1 7 2
6.3V 39.2F P2P5V GND RQ5
G5 G3 8 1
2
P2P5V GND
H5 P2P5V GND H3
GND J6
CFMN RN36 39
2 R153 R154 DQA7 5 4 2
75F 75F 2V5_D DQA4 6 3
C187 C188 C189 C190 DQA6 7 2
0.1U 68P J 0.1U 68P J VREF-RDRAM
DQA5 8 1
VTERM R155 VREF-RDRAM

DQA[0:8] DQA[0:8]
36.5F
VTERM
R156 C191 GND:A1,A9,A12,B4,C9,D4,D9
121F 0.1U GND:E4,F9,G4,H4,J1,J9,J12
P2P5V:A4,B9,C1,C4,C12,D8
P2P5V:E9,F4,G1,G9,G12,H9,J4
2V5_D C192 C193 C194 C195 C196 C197

VTERM 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
U33 MIC39100-1.8BS
Benq Corporation
1 3 VTERM
IN OUT
GND1
GND2
1
VTERM
1
+ C198 Project Code Model Name OEM/ODM Model Name

10U M C199 + C200 + C201
2
1 6.3V 0.1U 100U 100U 99.J8677.001 PB6100 <OEM/ODM> 1

2
6.3V 6.3V Title

2
MAIN BOARD
C202 C203 C204 C205 C206 C207
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U Size PCB P/N PCB Rev. Document Number R ev.
<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004
VTERM BULK DECOUPLING CAPS VTERM DECOUPLING CAPS Date: Tuesday, October 07, 2003 Sheet 16 of 20
A B C D E
A B C D E
DD[0:63]
U29C DD[0:63]
ADD[63:0]
P1 ADD63
DD63 ADD62 RN37 RN38
DD62 P2
4 ADD61 ADD38 DD38 ADD54 DD54 4
DD61 R4 1 16 1 16
R3 ADD60 ADD33 2 15 DD33 ADD52 2 15 DD52
DD60 ADD59 ADD36 DD36 ADD53 DD53
DD59 P4 3 14 3 14
R2 ADD58 ADD40 4 13 DD40 ADD48 4 13 DD48
DD57 T3 5 12 5 12
T4 ADD56 ADD37 6 11 DD37 ADD51 6 11 DD51
DD55 U1 7 10 7 10
A25 U3 ADD54 ADD42 8 9 DD42 ADD56 8 9 DD56
D0 DD54 ADD53
DD53 V1
D22 U4 ADD52
D1 DD52 ADD51 22 22
DD51 U2
ADD50 RN39 RN40
DD50 V3
W1 ADD49 ADD43 1 16 DD43 ADD60 1 16 DD60
DD49 ADD48 ADD46 DD46 ADD61 2 DD61
DD48 V2 2 15 15
V4 ADD47 ADD45 3 14 DD45 ADD58 3 14 DD58
DD47 ADD46 ADD41 DD41 ADD63 4 DD63
DD46 W3 4 13 13
Y1 ADD45 ADD49 5 12 DD49 ADD62 5 12 DD62
DGE[7:0] DD45 ADD44 ADD44 DD44 ADD59 6 DD59
DD44 W2 6 11 11
DGE[7:0] W4 ADD43 ADD47 7 10 DD47 ASACCLK ASACCLK 7 10 SACCLK SACCLK
DGE7 DD43 ADD42 ADD50 DD50 ASACBUS 8
F24 A9 DD42 Y3 8 9 ASACBUS 9 SACBUS SACBUS
DGE6 F25 Y2 ADD41
DGE5 A8 DD41 ADD40
D26 A7 DD40 AB1 22 22
DGE4 F23 Y4 ADD39
DGE3 A6 DD39 ADD38 RN41 RN42
3 E25 A5 DD38 AA3 3
DGE2 D25 AA2 ADD37 1 16 ADD21 1 16 DD21
DGE1 A4 DD37 ADD36 ADD28 DD28
C26 A3 DD36 AC1 2 15 2 15
DGE0 E24 AA4 ADD35 ADD27 3 14 DD27 ADD25 3 14 DD25
A2 DD35 ADD34 ADD29 DD29 ADD15 DD15
D24 A1 DD34 AB2 4 13 4 13
DRE[7:0] C25 AD1 ADD33 ADD31 5 12 DD31 ADD18 5 12 DD18
DRE[7:0] A0 DD33 ADD32 ADD30 DD30 ADD19 DD19
DD32 AB3 6 11 6 11
DRE7 J25 AC3 ADD31 ADD32 7 10 DD32 ADD22 7 10 DD22
DRE6 B9 DD31 ADD30 ADD35 DD35 ADD26 DD26
J23 B8 DD30 AB4 8 9 8 9
DRE5 H24 AC5 ADD29
DRE4 B7 DD29 ADD28
G26 B6 DD28 AE3 22 22
DRE3 H25 AD4 ADD27
DRE2 B5 DD27 ADD26 RN43 RN44
H23 B4 DD26 AD5
DRE1 G24 AF3 ADD25 ADD10 1 16 DD10 ADD4 1 16 D D4
DRE0 B3 DD25 ADD24 ADD11 DD11 ADD13 DD13
G25 B2 DD24 AE4 2 15 2 15
E26 AE5 ADD23 ADD14 3 14 DD14 ADD8 3 14 D D8
DBE[7:0] B1 DD23 ADD22 ADD12 DD12 ADD16 DD16
G23 B0 DD22 AC6 4 13 4 13
DBE[7:0] AF4 ADD21 ADD20 5 12 DD20 ADD0 5 12 D D0
DBE7 DD21 ADD20 ADD23 DD23 ADD3 D D3
M25 C9 DD20 AE6 6 11 6 11
DBE6 L24 AD6 ADD19 ADD17 7 10 DD17 ADD5 7 10 D D5
DBE5 C8 DD19 ADD18 ADD24 DD24 ADD7 D D7
L23 C7 DD18 AC7 8 9 8 9
DBE4 K26 AF5 ADD17
DBE3 C6 DD17 ADD16
L25 C5 DD16 AE7 22 22
DBE2 K24 AD7 ADD15
DBE1 C4 DD15 ADD14
2 J26 C3 DD14 AC8 2
DBE0 ADD13 RN45
K23 C2 DD13 AE8
J24 AF7 ADD12 ASCTRL-L ASCTRL-L 1 16 SCTRL-L SCTRL-L
C1 DD12 ADD11 ALOADB-LZ LOADB-LZ
GND H26 C0 DD11 AD8 ALOADB-LZ 2 15 LOADB-LZ
AC9 ADD10 3 14
DD10 ADD9 ATRC-L TRC-L
DD9 AE9 ATRC-L 4 13 TRC-L
AF8 ADD8 ADD2 5 12 D D2
DD8 ADD7 ADD6 D D6
DD7 AD9 6 11
AE10 ADD6 ADD1 7 10 D D1
DD6 ADD5 ADD9 D D9
DD5 AC10 8 9
AF9 ADD4
DD4 ADD3
DD3 AD10 22
AE11 ADD2
DD2 ADD1 ADCLK-L R807 22 DCLK-L
DD1 AF10 ADCLK-L DCLK-L
AC11 ADD0
DD0 C807
C806
DDP1000-C AE12 ADCLK-L 10P J 10P J
DCLK_L ADCLK-L
DMDSER DMDSER G2 AC12 ALOADB-LZ ALOADB-LZ
DMDSERIN LOADB_LZ
Benq Corporation
AC13 ASCTRL-L ASCTRL-L
SCTRL_L ATRC-L
TRC_L AD11 ATRC-L
DCLK_R P3
M1 Project Code Model Name OEM/ODM Model Name
LOADB_RZ
SCTRL_R N1 <OEM/ODM>
1 99.J8677.001 PB6100 1
TRC_R N3
M2 ASACBUS ASACBUS Title
SACBUS ASACCLK
N4 ASACCLK MAIN BOARD
SACCLK
INPUT AND DMD Size PCB P/N PCB Rev. Document Number R ev.
<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
A B C D E
4 The width of net MBRST[0:15] should be larger than 4

3.3V_D 11mils and the distance between two net should be
larger than 11 mils.
3.3V_D
R253 TP217
1K TP218 TP219 MBRST[0:15]
TP220 TP221 MBRST[0:15]
U701
SCPCK 56 79 MBRST15
SCP_CLK OUT15 MBRST14
SCPDI 57 SCPDI OUT14 77
SCPDO 42 74 MBRST13
SCPDO OUT13 MBRST12
SCPENZ 58 SCPENZ OUT12 72
69 MBRST11
OUT11 MBRST10
SR16STROBE 15 STORBE OUT10 67
SR16MODE1 2 64 MBRST9
MODE1 OUT09 MBRST8
SR16MODE0 3 MODE0 OUT08 62
SR16SEL1 4 SEL1
SR16SEL0 5 SEL0
39 MBRST7
OUT7 MBRST6 3.3V_D
OUT6 37
16 34 MBRST5 TP222
SR16ADDR3 A3 OUT5
3.3V_D 3.3V_D SR16ADDR2 17 32 MBRST4
A2 OUT4 MBRST3
18 29
R701 R702
SR16ADDR1
SR16ADDR0 19
A1
A0 DAD1000 OUT3
OUT2
OUT1
27
24
MBRST2
MBRST1 TP223
R725
MBRST0 1K
3 0 open 0 open
45
44
DEV_ID1
DEV_ID0
OUT0 22
3
IRQZ 43 IRQZ
EXT-ARSTZ 59 RESETZ
SR16OEZ 6 VCC2
OEZ
VOFF_RAIL7 78
54 VCC VOFF_RAIL6 73 VCC2
V12_D 68
VOFF_RAIL5 R726
52 V12_SWL1 VOFF_RAIL4 63
L703 51 V12_SWL0 VOFF_RAIL3 38
33 C704 C706
V12_D VOFF_RAIL2 C705 4.7U Z
P12V_FLT 50 28
V12_3 VOFF_RAIL1 10K 0.1U Z 0.1U Z
120 OHM 48 V12_2 VOFF_RAIL0 23
11 V12_1 VOFF 49
C712 C711 C710 C709 C708
0.1U Z 0.1U Z 0.1U Z 0.1U Z 4.7U Z 80 47 V5REG
VBIAS_RAIL7 V5REG
71 VBIAS_RAIL6
70 VBIAS_RAIL5
61 VBIAS_RAIL4 VRST_RAIL7 76
VBIAS 40 75 C707
VBIAS_RAIL3 VRST_RAIL6 0.22U K
1
+ C713 21 36
C715 C714 3.3U VBIAS_RAIL0 VRST_RAIL3
VRST_RAIL2 35
0.1U Z 0.1U Z 35V 9 26
2
VBIAS VRST_RAIL1 VRST

VRST_RAIL0 25
VBIAS_SWL 8 13
2 VBIAS_SWL VRST 2
1
L701 D701
2
22UH MBR0540T1 35V
3.3U C702 C703
+ C701 0.1U Z 0.1U Z
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
VBIAS_LHI 10 12 VRST_SWL
1
VBIAS_LHI VRST_SWL
1
7
14
20
41
46
53
55
60
1
L702
+ C735 22UH
10U
16V
2
Benq Corporation
1 Project Code Model Name OEM/ODM Model Name 1
99.J8677.001 PB6100 <OEM/ODM>
Title
MAIN BOARD

<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
V12_D L19
4 4
V12_D
1
80 OHM
2
+ C231
2
C232 C233 22U C234 C235
0.1U M 0.1U M 25V 0.1U M 0.1U M
2
GND 3 3 3
3 DN11 DN12 DN13
DN14 BAT54SW BAT54SW BAT54SW
BAT54SW
VDD_D
L20
1
ALVDD
VDD_D
1
80 OHM
ALVDD C236 C237
0.1U K VDD_D 0.1U K
R194 R195 R196

ALVDD C238 150 C239 150 C240 150
1
U41 Spare for reversed spin motor 1000P K 1000P K 1000P K
CKMTR1 2 4 R197 39.2F

R198 R199 R200 R201 R202
74V1G14S RX3 OPEN
U42 A8904SLB
3
3 TP57 3
1 RX4 OPEN
1K 1K 1K 1K 1K VBB
15 VDD
BRAKE 11 5 OUTA R203 1.5 TP58 CWY2
BRAKEZ OUTA
16 8 OUTB R204 1.5 TP59 CWY3 20K2002004
EXT-ARSTZ OSC OUTB
EXT-ARSTZ 20 RESETZ 4
MTRSELZ 21 9 OUTC R205 1.5 TP60 CWY1
MTRSELZ CSZ OUTC 3
MTRCLK MTRCLK 22
MTRDATA CLOCK CWCTR CWCTR 2
MTRDATA 23 DATAIN CNTRTAP 10 1
C D2 2 17 CWTACH CWTACH JC1
C WD CD2 DATAOUT
3 CWD
C D1 24 CD1
CRES 12 C241
CST CRES 0.022U K
4 CST GNDA 6
GNDB 7
C242 C243 C244 14 18
3300P K 5600P K 3300P K SECDAT GNDC
13 FILTER GNDD 19
C245 C246 See Motor Timing CAP. Chart
0.22U K 1U K
2 MFILT 2
See Motor Timing CAP. Chart
R206 MFILT1
1.5MF
C247 C248
0.022U K 0.33U Z
Benq Corporation
Include Guard Ring Around
these components on top and
buttom layers
1 99.J8677.001 PB6100 <OEM/ODM> 1
Title
MAIN BOARD

<Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004

A B C D E
A B C D E
DD[0:63]
DD[0:63]
JP2
2 1
4 3
6 5
8 7
10 9
12 11 VDD
14 13 VDD Screw Holes
16 15
4 4
18 17
20 19 BINSEL0 BINSEL0
22 21 BINSEL1 BINSEL1
24 23
3.3V_D 26 25 VCC2
3.3V_D 28 27 VCC2
30 29
SACCLK 32 31 DMDSER
1
SACCLK DMDSER 5 9 5 9 5 9 5 9
SACBUS SACBUS 34 33 LOADB-LZ
LOADB-LZ
SCTRL-L SCTRL-L 36 35
TRC-L DCLK-L 4 8 4 8 4 8 4 8
TRC-L 38 37 DCLK-L
40 39 3 7 3 7 3 7 3 7
DD62 42 41 DD63
DD60 44 43 DD61
2 6 2 6 2 6 2 6
46 45
DD58 48 47 DD59
H3 H4 H5 H6
DD56 50 49 DD57
52 51 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8
DD54 54 53 DD55
DD52 56 55 DD53
58 57
DD50 60 59 DD51
DD48 62 61 DD49
3 64 63 3
DD46 66 65 DD47
DD44 68 67 DD45
70 69
DD42 72 71 DD43
DD40 74 73 DD41
76 75
DD38 78 77 DD39 Optical Points
DD36 80 79 DD37
20L1066080 MARK1 MARK3 MARK5 MARK6 MARK9 MARK10

JP3 OP OP OP OP OP OP
2 1
DD34 4 3 DD35
DD32 6 5 DD33
8 7
DD30 10 9 DD31 MARK11 MARK12 MARK13 MARK14 MARK15 MARK17
DD28 12 11 DD29 OP OP OP OP OP OP
14 13
DD26 16 15 DD27
DD24 18 17 DD25
20 19
22 21
DD22 24 23 DD23 MARK19 MARK20
2 DD20 26 25 DD21 OP OP 2
28 27
DD18 30 29 DD19
DD16 32 31 DD17
34 33
DD14 36 35 DD15
DD12 38 37 DD13
40 39
DD10 42 41 DD11
D D8 44 43 D D9
46 45
D D6 48 47 D D7
D D4 50 49 D D5
52 51
D D2 54 53 D D3
D D0 56 55 D D1
GND 58 57
60 59
MBRST14 62 61 MBRST15
Benq Corporation
MBRST8 68 67 MBRST9
70 69 Project Code Model Name OEM/ODM Model Name
MBRST6 72 71 MBRST7
1 MBRST4 MBRST5 99.J8677.001 PB6100 <OEM/ODM> 1
74 73
MBRST2 76 75 MBRST3 Title
MBRST0 78 77 MBRST1 MAIN BOARD
80 79
20L1066080 <Size> 1
48.J8601.S04 S04 99.J8677.B12-C3-304-004
MBRST[0:15]
MBRST[0:15] Tuesday, October 07, 2003
Date: Sheet 20 of 20
A B C D E

DLP Projector: Service Manual

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DLP Projector: Service Manual

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DLP PROJECTOR

READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

1 42.J8618.001 U/C PC+ABS PB6100 R

2 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2

3 54.J8612.001 BALLAST PHG201G16 PB6100 R

4 60.J8605.001 ASSY Lower Case PB6100 R

5 23.10102.001 BLOWER 12V 50*50*20MM ADDA R

6 60.J8617.001 ASSY LAMPBOX PB6100 R

7 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R

8 60.J8604.001 ASSY R/C PB6100 R

9 55.J8608.001 PCBA REAR IR BD PB6100 2

10 65.J8602.001 ASSY AC INLET+THERM SW PB6100 R

11 55.J5019.001 PCBA THERMAL BD DX850 2

12 55.J5020.001 PCBA EMI BD DX850 2

13 55.J8601.001 PCBA MAIN BD PB6100 2

14 60.J8607.001 ASSY DOOR PB6100 R

15 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI 2

16 65.J8603.001 CW DIA44DEG110 PB6100 PRODISC R

17 55.J5019.001 PCBA THERMAL BD DX850 2

18 55.J8623.001 PCBA CHIP BD PB6100 2

19 65.J7602.001 PL ZOOM PB7200 ASIA R

20 71.08060.000 IC DMD 0.6SVGA 8060-624C 12DDR R

21 31.J8601.001 BADGE AL PLATE PB6100 R

22 60.J1334.001 ASSY CAP LENS SL700X R

23 60.J8603.001 ASSY F/C PB6100 R

24 55.J8611.001 PCBA PFC BD PB6100 2

25 55.J8613.001 PCBA FAN BD PB6100 2

26 65.J5003.001 FOOT ADJ DX850 R

27 44.J0502.005 CTN 415*325*255 PB6100/BENQ VI R

28 47.J8605.001 CUSHION FRONT EPE PB6100 R

29 47.J8606.001 CUSHION REAR EPE PB6100 PB6100 R

30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R

31 50.J0508.503 SIGNAL/C 15/15P 20276 1800MM R

32 50.J1303.501 CABLE RCA Y/Y 1600MM BLK R

33 56.26J86.001 REMOTE CR14AI PB6100 R

34 42.20019.002 BAG PE 250*350 LD FP741/NEC R

35 46.00003.012 CARD WARRANTY 7254E R

36 49.J8601.001 MANUAL USER PB6100/ PB6200 R

37 53.J8601.001 CD MANUAL USER PB6100/ PB6200 R

38 60.J8618.CG1 ASSY Service LAMP 200W/U PB6100 0

39 60.J8621.001 ASSY S2+ EGN 12D PB6100 0

1 55.J8501.001 PCBA MAIN BD PB6200 2

2 42.J8618.001 U/C PC+ABS PB6100 R

3 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2

4 54.J8612.001 BALLAST PHG201G16 PB6100 R

5 55.J5020.001 PCBA EMI BD DX850 2

6 60.J8605.001 ASSY L/C PB6100 R

7 55.J8608.001 PCBA REAR IR BD PB6100 2

8 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R

9 60.J8607.001 ASSY DOOR PB6100 R

10 23.10102.001 BLOWER 12V 50*50*20MM ADDA R

11 60.J8617.001 ASSY LAMPBOX PB6100 R

12 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI 2

13 65.J8603.001 CW DIA44DEG110 PB6100 PRODISC R

14 60.J8621.001 ASSY S2+ EGN 12D PB6100 0

15 55.J8623.001 PCBA CHIP BD PB6100 2

16 71.08060.000 IC DMD 0.6SVGA 8060-624C 12DDR R

17 31.J7601.061 NAME PLATE AL PB6200 R

18 55.J5019.001 PCBA THERMAL BD DX850 2

19 60.J1334.001 ASSY CAP LENS SL700X R

20 60.J8603.001 ASSY F/C PB6100 R

21 55.J8611.001 PCBA PFC BD PB6100 2

22 55.J8613.001 PCBA FAN BD PB6100 2

5 23.10102.001 BLOWER 12V 505020MM ADDA R

7 23.10103.001 FAN 12V 707025AXIAL ADDA R

27 44.J0502.005 CTN 415325255 PB6100/BENQ VI R

8 23.10103.001 FAN 12V 707025AXIAL ADDA R

10 23.10102.001 BLOWER 12V 505020MM ADDA R

29 44.J0501.011 CTN ASSY 35024048 7765P R