1. The ______ format is usually used to store data.

a) BCD
b) Decimal
c) Hecadecimal
d) Octal
View Answer

Answer: a
Explanation: The data usually used by computers have to be stored and represented in a particular
format for ease of use.

2. The 8-bit encoding format used to store data in a computer is ______

a) ASCII
b) EBCDIC
c) ANCI
d) USCII
View Answer

Answer: b
Explanation: The data to be stored in the computers have to be encoded in a particular way so as to be
provide secure processing of the data.

3. A source program is usually in _______

a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
View Answer

Answer: c
Explanation: The program written and before being compiled or assembled is called as a source
program.

4. Which memory device is generally made of semi-conductors?

a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
View Answer

Answer: a
Explanation: Memory devices are usually made of semi conductors for faster manipulation of the
contents.
5. The small extremely fast, RAM’s are called as _______
a) Cache
b) Heaps
c) Accumulators
d) Stacks
View Answer

Answer: a
Explanation: These small and fast memory devices are compared to RAM because they optimize the
performance of the system and they only keep files which are required by the current process in them

6. The ALU makes use of _______ to store the intermediate results.

a) Accumulators
b) Registers
c) Heap
d) Stack
View Answer

Answer: a
Explanation: The ALU is the computational center of the CPU. It performs all the mathematical and
logical operations. In order to perform better it uses some internal memory spaces to store immediate
results.

7. The control unit controls other units by generating ____

a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
View Answer

Answer: b
Explanation: This unit is used to control and coordinate between the various parts and components of
the CPU.

8. ______ are numbers and encoded characters, generally used as operands.

a) Input
b) Data
c) Information
d) Stored Values
View Answer

Answer: b
Explanation: None.
9. The Input devices can send information to the processor.
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
View Answer

Answer: a
Explanation: The input devices use buffers to store the data received and when the buffer has some data
it sends it to the processor.

10. ______ bus structure is usually used to connect I/O devices.

a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
View Answer

Answer: a
Explanation: BUS is a bunch of wires which carry address,control signals and data. It is used to connect
various components of the computer.

11. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
View Answer

Answer: c
Explanation: The I/O devices are connected to the CPU via BUS and to interact with the BUS they’ve a
interface.

12. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
View Answer

Answer: d
Explanation: The time required to access a part of the memory for data retrieval.
13. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
View Answer

Answer: b
Explanation: Virtual memory is like an extension to the existing memory.

14. MFC stands for ___________

a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
View Answer

Answer: b
Explanation: This is a system command enabled when a memory function is completed by a process.

15. The time delay between two successive initiation of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
View Answer

Answer: c
Explanation: The time taken to finish one task and to start another.

1. The decoded instruction is stored in ______

a) IR
b) PC
c) Registers
d) MDR
View Answer

Answer: a
Explanation: The instruction after obtained from the PC, is decoded and operands are fetched and
stored in the IR.

2. The instruction -> Add LOCA, R0 does _______

a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
View Answer

Answer: c
Explanation: None.

3. Which registers can interact with the secondary storage?

a) MAR
b) PC
c) IR
d) R0
View Answer

Answer: a
Explanation: MAR can interact with secondary storage in order to fetch data from it.

4. During the execution of a program which gets initialized first ?

a) MDR
b) IR
c) PC
d) MAR
View Answer

Answer: c
Explanation: For the execution of a process first the instruction is placed in the PC.

5. Which of the register/s of the processor is/are connected to Memory Bus ?

a) PC
b) MAR
c) IR
d) Both PC and MAR
View Answer

Answer: b
Explanation: MAR is connected to the memory BUS in order to access the memory

6. ISP stands for _________

a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
View Answer
Answer: a
Explanation: None.

7. The internal Components of the processor are connected by _______

a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
View Answer

Answer: b
Explanation: The processor BUS is used to connect the various parts in order to provide a direct
connection to the CPU.

8. ______ is used to choose between incrementing the PC or performing ALU operations.

a) Conditional codes
b) Multiplexer
c) Control unit
d) None of the mentioned
View Answer

Answer: b
Explanation: The multiplexer circuit is used to choose between the two as it can give different results
based on the input.

9. The registers,ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
View Answer

Answer: d
Explanation: The Operational and processing part of the CPU are collectively called as data path.

10. _______ is used to store data in registers.

a) D flip flop
b) JK flip flop
c) RS flip flop
d) None of the mentioned
View Answer

Answer: a
Explanation: None.
1. The main virtue for using single Bus structure is ____________
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
d) None of the mentioned
View Answer

Answer: c
Explanation: By using single BUS structure we can minimize the amount hardware (wire) required and
thereby reducing the cost.

2. ______ are used to over come the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
View Answer

Answer: d
Explanation: By using Buffer registers, the processor sends the data to the I/O device at the processor
speed and the data gets stored in the buffer.After that the data gets sent to or from the buffer to the
devices at the device speed.

3. To extend the connectivity of the processor bus we use ________

a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
View Answer

Answer: a
Explanation: PCI BUS is used to connect other peripheral devices which require a direct connection with
the processor.

4. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
a) IB bus
b) M-bus
c) ISA
d) None of the mentioned
View Answer

Answer: c
Explanation: None.
5. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
View Answer

Answer: b
Explanation: SCSI BUS is usually used to connect the video devices to the processor.

6. ANSI stands for __________

a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
View Answer

Answer: a
Explanation: None.

7. _____ register Connected to the Processor bus is a single-way transfer capable.

a) PC
b) IR
c) Temp
d) Z
View Answer

Answer: d
Explanation: The Z register is a special register which can interact with the processor BUS only.

8. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register file
c) Register Block
d) Map registers
View Answer

Answer: b
Explanation: None.

9. The main advantage of multiple bus organisation over single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

10. The ISA standard Buses are used to connect ___________

a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
View Answer

Answer: c
Explanation: None.

1. During the execution of the instructions, a copy of the instructions is placed in the ______
a) Register
b) RAM
c) System heap
d) Cache
View Answer

Answer: d
Explanation: None.

2. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can
execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the
execution of the same instruction which processor is faster ?
a) A
b) B
C) Both take the same time
d) Insuffient information
View Answer

Answer: a
Explanation: The performance of a system can be found out using the Basic performance formula.

3. A processor performing fetch or decoding of different instruction during the execution of another
instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of the mentioned
View Answer

Answer: b
Explanation: Pipe-lining is the process of improving the performance of the system by processing
different instructions at the same time, with only one instruction performing one specific operation.

4. For a given FINITE number of instructions to be executed, which architecture of the processor
provides for a faster execution ?
a) ISA
b) ANSA
c) Super-scalar
d) All of the mentioned
View Answer

Answer: c
Explanation: In super-scalar architecture, the instructions are set in groups and they’re decoded and
executed together reducing the amount of time required to process them.

5. The clock rate of the processor can be improved by _________

a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using overclocking method
d) All of the mentioned
View Answer

Answer: d
Explanation: The clock rate(frequency of the processor) is the hardware dependent quantity it is fixed
for a given processor.

6. An optimizing Compiler does _________

a) Better compilation of the given piece of code
b) Takes advantage of the type of processor and reduces its process time
c) Does better memory managament
d) none of the mentioned
View Answer

Answer: b
Explanation: An optimizing compiler is a compiler designed for the specific purpose of increasing the
operation speed of the processor by reducing the time taken to compile the program instructions.

7. The ultimate goal of a compiler is to ________

a) Reduce the clock cycles for a programming task
b) Reduce the size of the object code
c) Be versatile
d) Be able to detect even the smallest of errors
View Answer

Answer: a
Explanation: None.

8. SPEC stands for _______

a) Standard Performance Evaluation Code
b) System Processing Enhancing Code
c) System Performance Evaluation Corporation
d) Standard Processing Enhancement Corporation
View Answer

Answer: c
Explanation: SPEC is a corporation started to standardize the evaluation method of a systems
performance.

9. As of 2000, the reference system to find the performance of a system is _____

a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
d) None of the mentioned
View Answer

Answer: a
Explanation: In SPEC system of measuring a systems performance, a system is used as a reference
against which other systems are compared and performance is determined.

10. When Performing a looping operation, the instruction gets stored in the ______
a) Registers
b) Cache
c) System Heap
d) System stack
View Answer

Answer: b
Explanation: When a looping or branching operation is carried out the offset value is stored in the cache
along with the data.

11. The average number of steps taken to execute the set of instructions can be made to be less than
one by following _______
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
View Answer

Answer: c
Explanation: The number of steps required to execute a given set of instructions is sufficiently reduced
by using super-scaling. In this method a set of instructions are grouped together and are processed.

12. If a processor clock is rated as 1250 million cycles per second, then its clock period is ________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
View Answer

Answer: d
Explanation: None.

13. If the instruction, Add R1, R2, R3 is executed in a system which is pipe-lined, then the value of S is
(Where S is term of the Basic performance equation)
a) 3
b) ~2
C) ~1
d) 6
View Answer

Answer: c
Explanation: S is the number of steps required to execute the instructions.

14. CISC stands for _______

a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
View Answer

Answer: c
Explanation: CISC is a type of system architecture where complex instructions are grouped together and
executed to improve the system performance.

15. As of 2000, the reference system to find the SPEC rating are built with _____ Processor.
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
View Answer

Answer: b
Explanation: None.

1. The instruction, Add #45,R1 does _______

a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
View Answer

Answer: b
Explanation: The instruction is using immediate addressing mode hence the value is stored in the
location 45 is added.

2. In case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
View Answer

Answer: c
Explanation: In this case the operands are implicitly loaded onto the ALU.

3. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
d) None of the mentioned
View Answer

Answer: b
Explanation: None.

4. The addressing mode which makes use of in-direction pointers is ______

a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
View Answer
Answer: a
Explanation: In this addressing mode, the value of the register serves as another memory location and
hence we use pointers to get the data.

5. In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1] d) EA = 5+[R1] View Answer

6. The addressing mode/s, which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) direct
d) both Indexed with offset and direct
View Answer

Answer: b
Explanation: In this the contents of the PC are directly incremented.

7. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations

a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3
View Answer

Answer: d
Explanation: In case of, auto increment the increment is done afterwards and in auto decrement the
decrement is done first.

8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
View Answer

Answer: a
Explanation: None.
9. The effective address of the following instruction is, MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2].
d) 5*([R1]+[R2])
View Answer

Answer: c
Explanation: The addressing mode used is base with offset and index.

10. _____ addressing mode is most suitable to change the normal sequence of execution of instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
View Answer

Answer: a
Explanation: The relative addressing mode is used for this since it directly updates the PC

1. Which method/s of representation of numbers occupies large amount of memory than others ?
a) Sign-magnitude
b) 1’s compliment
c) 2’s compliment
d) 1’s & 2’s compliment
View Answer

Answer: a
Explanation: It takes more memory as one bit used up to store the sign.

2. Which representation is most efficient to perform arithmetic operations on the numbers ?

a) Sign-magnitude
b) 1’s compliment
c) 2’S compliment
d) None of the mentioned
View Answer

Answer: c
Explanation: The two’s compliment form is more suitable to perform arithmetic operations as there is
no need to involve the sign of the number into consideration.

3. Which method of representation has two representations for ‘0’ ?

a) Sign-magnitude
b) 1’s compliment
c) 2’s compliment
d) None of the mentioned
View Answer

Answer: a
Explanation: One is positive and one for negative.

4. When we perform subtraction on -7 and 1 the answer in 2’s compliment form is _________
a) 1010
b) 1110
c) 0110
d) 1000
View Answer

Answer: d
Explanation: First the 2’s compliment is found and that is added to the number and the overflow is
ignored.

5. When we perform subtraction on -7 and -5 the answer in 2’s compliment form is ________
a) 11110
b) 1110
c) 1010
d) 0010
View Answer

Answer: b
Explanation: First the 2’s compliment is found and that is added to the number and the overflow is
ignored.

6. When we subtract -3 from 2 , the answer in 2’s compliment form is _________

a) 0001
b) 1101
c) 0101
d) 1001
View Answer

Answer: c
Explanation: First the 2’s compliment is found and that is added to the number and the overflow is
ignored.

7. The processor keeps track of the results of its operations using a flags called ________
a) Conditional code flags
b) Test output flags
c) Type flags
d) None of the mentioned
View Answer

Answer: a
Explanation: These flags are used to indicate if there is a overflow or carry or zero result occurrence.

8. The register used to store the flags is called as _________

a) Flag register
b) Status register
c) Test register
d) Log register
View Answer

Answer: b
Explanation: The status register stores the condition codes of the system.

9. The Flag ‘V’ is set to 1 indicates that,

a) The operation is valid
b) The operation is validated
c) The operation as resulted in an overflow
d) None of the mentioned
View Answer

Answer: c
Explanation: This is used to check the overflow occurrence in the operation.

10. In some pipelined systems, a different instruction is used to add to numbers which can affect the
flags upon execution. That instruction is _______
a) AddSetCC
b) AddCC
c) Add++
d) SumSetCC
View Answer

Answer: a
Explanation: By using this instruction the condition flags wont be affected at all.

11. The most efficient method followed by computers to multiply two unsigned numbers is _______
a) Booth algorithm
b) Bit pair recording of multipliers
c) Restoring algorithm
d) Non restoring algorithm
View Answer
Answer: b
Explanation: None.

12. For the addition of large integers most of the systems make use of ______
a) Fast adders
b) Full adders
c) Carry look-ahead adders
d) None of the mentioned
View Answer

Answer: c
Explanation: In this method the carries for each step are generated first.

13. In a normal n-bit adder, to find out if an overflow as occured we make use of ________
a) And gate
b) Nand gate
c) Nor gate
d) Xor gate
View Answer

Answer: d
Explanation: None.

14. In the implementation of a Multiplier circuit in the system we make use of _______
a) Counter
b) Flip flop
c) Shift register
d) Push down stack
View Answer

Answer: c
Explanation: The shift registers are used to store the multiplied answer.

15. When 1101 is used to divide 100010010 the remainder is ______

a) 101
b) 11
c) 0
d) 1
View Answer

Answer: d
Explanation: None.

1. The smallest entity of memory is called as _______

a) Cell
b) Block
c) Instance
d) Unit
View Answer

Answer: a
Explanation: Each data is made up of a number units.

2. The collection of the above mentioned entities where data is stored is called as ______
a) Block
B) Set
c) Word
d) Byte
View Answer

Answer: c
Explanation: Each readable part of data is called as blocks.

3. An 24 bit address generates an address space of ______ locations.

a) 1024
b) 4096
c) 2 48
d) 16,777,216
View Answer

Answer: d
Explanation: The number of addressable locations in the system is called as address space.

4. If a system is 64 bit machine , then the length of each word will be _______
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
View Answer

Answer: b
Explanation: A 64 bit system means, that at a time 64 bit instruction can be executed.

5. The type of memory assignment used in Intel processors is _____

a) Little Endian
b) Big Endian
c) Medium Endian
d) None of the mentioned
View Answer
Answer: a
Explanation: The method of address allocation to data to be stored is called as memory assignment.

6. When using the Big Endian assignment to store a number, the sign bit of the number is stored in
_____
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

7. To get the physical address from the logical address generated by CPU we use ____
a) MAR
b) MMU
c) Overlays
d) TLB
View Answer

Answer: b
Explanation: Memory Management Unit, is used to add the offset to the logical address generated by
the CPU to get the physical address.

8. _____ method is used to map logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
View Answer

Answer: c
Explanation: Segmentation is a process in which memory is divided into groups of variable length called
segments.

9. During transfer of data between the processor and memory we use ______
a) Cache
b) TLB
C) Buffers
d) Registers
View Answer
Answer: d
Explanation: None.

10. Physical memory is divided into sets of finite size called as ______
a) Frames
b) Pages
c) Blocks
d) Vectors
View Answer

Answer: a
Explanation: None.

(MCQs) focuses on “Memory Operations and Management”.

1. Add #%01011101,R1 , when this instruction is executed then _________

a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of R1
c) The addition doesn’t take place , whereas this is similar to a MOV instruction
d) None of the mentioned
View Answer

Answer: a
Explanation: This performs operations in binary mode directly.

2. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then we use
___ symbol before the operand.
a) ~
b) !
c) $
d) *
View Answer

Answer: c
Explanation: None.

3. When generating physical addresses from logical address the offset is stored in _____
a) Translation look-aside buffer
b) Relocation register
c) Page table
d) Shift register
View Answer

Answer: b
Explanation: In the MMU the relocation register stores the offset address.
4. The technique used to store programs larger than the memory is ______
a) Overlays
b) Extension registers
c) Buffers
d) Both Extension registers and Buffers
View Answer

Answer: a
Explanation: In this, only a part of the program getting executed is stored on the memory and later
swapped in for the other part.

5. The unit which acts as an intermediate agent between memory and backing store to reduce process
time is _____
a) TLB’s
b) Registers
c) Page tables
d) Cache
View Answer

Answer: d
Explanation: The cache’s help in data transfers by storing most recently used memory pages.

6. The Load instruction does the following operation/s,

a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
d) None of the mentioned
View Answer

Answer: b
Explanation: The load instruction is basically used to load the contents of a memory location onto a
register.

7. Complete the following analogy :- Registers are to RAM’s as Cache’s are to _____
a) System stacks
b) Overlays
c) Page Table
d) TLB
View Answer

Answer: d
Explanation: None.
8. The BOOT sector files of the system are stored in _____
a) Harddisk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
View Answer

Answer: b
Explanation: The files which are required for the starting up of a system are stored on the ROM.

9. The transfer of large chunks of data with the involvement of the processor is done by _______
a) DMA controller
b) Arbitrator
c) User system programs
d) None of the mentioned
View Answer

Answer: a
Explanation: This mode of transfer involves the transfer of a large block of data from the memory.

10. Which of the following technique/s used to effectively utilize main memory ?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both Dynamic linking and loading
View Answer

Answer: c
Explanation: In this method only when the routine is required is loaded and hence saves memory.

“Instructions and Instruction Sequencing”.

1. RTN stands for ___________

a) Register Transfer Notation
b) Register Transmission Notation
c) Regular Transmission Notation
d) Regular Transfer Notation
View Answer

Answer:a
Explanation: This is the way of writing the assembly language code with the help of register notations.

2. The instruction, Add Loc,R1 in RTN is _______

a) AddSetCC Loc+R1
b) R1=Loc+R1
c) Not possible to write in RTN
d) R1<-[Loc]+[R1].
View Answer

Answer:d
Explanation: None.

3. Can you perform addition on three operands simultaneously in ALN using Add instruction ?
a) Yes
b) Not possible using Add, we’ve to use AddSetCC
c) Not permitted
d) None of the mentioned
View Answer

Answer:c
Explanation: You cannot perform addition on three operands simultaneously because the third operand
is where the result is stored.

4. The instruction, Add R1,R2,R3 in RTN is _______

a) R3=R1+R2+R3
b) R3<-[R1]+[R2]+[R3].
c) R3=[R1]+[R2].
d) R3<-[R1]+[R2].
View Answer

Answer:d
Explanation: In RTN the first operand is the destination and the second operand is the source.

5. In a system, which has 32 registers the register id is ____ long.

a) 16 bit
b) 8 bits
c) 5 bits
d) 6 bits
View Answer

Answer:c
Explanation: The ID is the name tag given to each of the registers and used to identify them.

6. The two phases of executing an instruction are __________

a) Instruction decoding and storage
b) Instruction fetch and instruction execution
c) Instruction execution and storage
d) Instruction fetch and Instruction processing
View Answer
Answer:b
Explanation: First, the instructions are fetched and decoded and then they’re executed and stored.

7. The Instruction fetch phase ends with _________

a) Placing the data from the address in MAR into MDR
b) Placing the address of the data into MAR
c) Completing the execution of the data and placing its storage address into MAR
d) Decoding the data in MDR and placing it in IR
View Answer

Answer:d
Explanation: The fetch ends with the instruction getting decoded and being placed in the IR and the PC
getting incremented.

8. While using the iterative construct (Branching) in execution ____ instruction is used to check the
condition.
a) TestAndSet
b) Branch
c) TestCondn
d) None of the mentioned
View Answer

Answer:b
Explanation: Branch instruction is used to check the test condition and to perform the memory jump
with help of offset.

9. When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded which is
called as ______
a) Branch target
b) Loop target
c) Forward target
d) Jump instruction
View Answer

Answer:a
Explanation: None.

10. The condition flag Z is set to 1 to indicate _______

a) The operation has resulted in an error
b) The operation requires an interrupt call
c) The result is zero
d) There is no empty register available
View Answer
Answer:c
Explanation: This condition flag is used to check if the arithmetic operation yields a zero output.

1. ____ converts the programs written in assembly language into machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
View Answer

Answer: c
Explanation: The assembler is a software used to convert the programs into machine instructions.

2. The instructions like MOV or ADD are called as ______

a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
View Answer

Answer: a
Explanation: This OP – codes tell the system what operation to perform on the operands.

3. The alternate way of writing the instruction, ADD #5,R1 is ______

a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
View Answer

Answer: b
Explanation: The ADDI instruction, means the addition is in immediate addressing mode.

4. Instructions which wont appear in the object program are called as _____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
View Answer

Answer: d
Explanation: The directives help the program in getting compiled and hence wont be there in the object
code.
5. The assembler directive EQU, when used in the instruction : Sum EQU 200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
View Answer

Answer: b
Explanation: This basically is used to replace the variable with a constant value.

6. The purpose of the ORIGIN directive is __________

a) To indicate the starting position in memory, where the program block is to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
View Answer

Answer: a
Explanation: This does the function similar to the main statement.

7. The directive used to perform initialization before the execution of the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
View Answer

Answer: c
Explanation: None.

8. _____ directive is used to specify and assign the memory required for the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
View Answer

Answer: d
Explanation: This instruction is used to allocate a block of memory and to store the object code of the
program there.

9. _____ directive specifies the end of execution of a program.

a) End
b) Return
c) Stop
d) Terminate
View Answer

Answer: b
Explanation: This instruction directive is used to terminate the program execution.

10. The last statement of the source program should be _______

a) Stop
b) Return
c) OP
d) End
View Answer

Answer: d
Explanation: This enables the processor to load some other process.

11. When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
View Answer

Answer: c
Explanation: When the assembler comes across the branch code, it immediately finds the branch offset
and replaces it with it.

12. The assembler stores all the names and their corresponding values in ______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
View Answer

Answer: b
Explanation: The table where the assembler stores the variable names along with their corresponding
memory locations and values.

13. The assembler stores the object code in ______

a) Main memory
b) Cache
c) RAM
d) Magnetic disk
View Answer

Answer: d
Explanation: After compiling the object code, the assembler stores it in the magnetic disk and waits for
further execution.

14. The utility program used to bring the object code into memory for execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
View Answer

Answer: a
Explanation: The program which is used to load the program into memory.

15. To overcome the problems of the assembler in dealing with branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
View Answer

Answer: d
Explanation: This creates entries into the symbol table first and then creates the object code.

 “Subroutines and Nesting”.

1. The return address of the Sub-routine is pointed to by _______

a) IR
b) PC
c) MAR
d) Special memory registers
View Answer

2. The location to return to, from the subroutine is stored in _______

a) TLB
b) PC
c) MAR
d) Link registers
View Answer

3. Subroutine nesting means,

a) Having multiple subroutines in a program
b) Using a linking nest statement to put many sub routines under the same name
c) Having one routine call the other
d) None of the mentioned
View Answer

4. The order in which the return addresses are generated and used is _________
a) LIFO
b) FIFO
c) Random
d) Highest priority
View Answer

5. In case of nested subroutines the return addresses are stored in __________

a) System heap
b) Special memory buffers
c) Processor stack
d) Registers
View Answer

6. The appropriate return addresses is obtained by the help of ____ in case of nested routines.
a) MAR
b) MDR
c) Buffers
d) Stack-pointers
View Answer

7. When, parameters are being passed on to the subroutines they are stored in ________
a) Registers
b) Memory locations
c) Processor stacks
d) All of the mentioned
View Answer

8. The most efficient way of handling parameter passing is by using ______

a) General purpose registers
b) Stacks
c) Memory locations
d) None of the mentioned
View Answer

9. The most Flexible way of logging the return addresses of the sub routines is by using _______
a) Registers
b) Stacks
c) Memory locations
d) None of the mentioned
View Answer

10. The wrong statement/s regarding interrupts and subroutines among the following is/are ______
i) The sub-routine and interrupts have a return statement
ii) Both of them alter the content of the PC
iii) Both are software oriented
iv) Both can be initiated by the user
a) i,ii and iv
b) ii and iii
c) iv
d) iii and iv
View Answer

“Parameter Passing and Stack Frame”.

1. The private work space dedicated to a subroutine is called as ________

a) System heap
b) Reserve
c) Stack frame
d) Allocation
View Answer

Answer: c
Explanation: This work space is where the intermediate values of the sub routines is stored.

2. If, the sub routine exceeds the private space allocated to it then the values are pushed onto
_________
a) Stack
b) System heap
c) Reserve Space
d) Stack frame
View Answer

Answer: a
Explanation: If the allocated work space is exceeded then the data is pushed onto the system stack.

3. ______ pointer is used to point to parameters passed or local parameters of the sub routine.
a) Stack pointer
b) Frame pointer
c) Parameter register
d) Log register
View Answer
Answer: b
Explanation: This pointer is used to track the current position of the stack being used.

4. The reserved memory or private space of the sub routine, gets deallocated when _______
a) The stop instruction is executed by the routine
b) The pointer reaches the end of the space
c) When the routine’s return statement is executed
d) None of the mentioned
View Answer

Answer: c
Explanation: The work space allocated to a sub routine gets de allocated when the routine is completed.

5. The private space gets allocated to each sub routine when _________
a) The first statement of the routine is executed
b) When the context switch takes place
c) When the routine gets called
d) When the Allocate instruction is executed
View Answer

Answer: c
Explanation: When the call statement is executed, simultaneously the space also gets allocated.

6. _____ the most suitable data structure used to store the return addresses in case of nested sub
routines.
a) Heap
b) Stack
c) Queue
d) List
View Answer

Answer: b
Explanation: None.

7. In case of nested sub routines the stack top is always _________

a) The saved contents of the called sub routine
b) The saved contents of the calling sub routine
c) The return addresses of the called sub routine
d) None of the mentioned
View Answer

Answer: a
Explanation: None.
8. The stack frame for each sub routine is present in ______
a) Main memory
b) System Heap
c) Processor Stack
d) None of the mentioned
View Answer

Answer: c
Explanation: The memory for the work space is allocated from the processor stack.

9. The data structure suitable for scheduling processes is _______

a) List
b) Heap
c) Queue
d) Stack
View Answer

Answer: c
Explanation: The Queue data structure is generally used for scheduling as it is two directional.

10. The sub-routine service procedure, is similar to that of the interrupt service routine in ________
a) Method of context switch
b) Returning
c) Process execution
d) Method of context switch & Process execution
View Answer

Answer: d
Explanation: The Sub routine service procedure is same as the interrupt service routine in all aspects,
except the fact that 

on “Accessing I/O Devices”.

1. In memory-mapped I/O ____________

a) The I/O devices and the memory share the same address space
b) The I/O devices have a seperate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
View Answer

Answer: a
Explanation: Its the different modes of accessing the i/o devices.

2. The usual BUS structure used to connect the I/O devices is

a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
View Answer

Answer: c
Explanation: BUS is a collection of address,control and data lines used to connect the various devices of
the computer.

3. In intel’s IA-32 architecture there is a seperate 16 bit address space for the I/O devices?
a) False
b) True
View Answer

Answer: b
Explanation: This type of accessing is called as I/O mapped devices.

4. The advantage of I/O mapped devices to memory mapped is

a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
View Answer

Answer: c
Explanation: Since the I/O mapped devices have a seperate address space the address lines are limited
by amount of the space allocated.

5. The system is notified of a read or write operation by

a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
View Answer

Answer: d
Explanation: It is necessary for the processor to send a signal intimating the request as either read or
write.

6. To overcome the lag in the operating speeds of the I/O device and the processor we use
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
View Answer

Answer: b
Explanattion: The processor operating is much faster than that of the I/O devices , so by using the status
flags the processor need not wait till the I/O operation is done. It can continue with its work until the
status flag is set.

7. The method of accessing the I/O devices by repeatedly checking the status flags is
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None of the mentioned
View Answer

Answer: a
Explanation: In this method the processor constantly checks the status flags , and when it finds that the
flag is set it performs the appropriate operation.

8. The method of synchronising the processor with the I/O device in which the device sends a signal
when it is ready is
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
View Answer

Answer: c
Explanation: This is a method of accessing the I/O devices which gives the complete power to the
devices, enabling them to intimate the processor when they’re ready for transfer.

9. The method which offers higher speeds of I/O transfers is

a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
View Answer

Answer: d
Explanation: In DMA the I/O devices are directly allowed to interact with the memory with out the
intervention of the processor and the transfres take place in the form of blocks increasing the speed of
operaion.
10. The process where in the processor constantly checks the status flags is called as
a) Polling
b) Inspection
c) Reviewing
d) Echoing
View Answer

Answer: a
Explanation: None.

focuses on “Interrupts”.

1. The interrupt-request line is a part of the

a) Data line
b) Control line
c) Address line
d) None of the mentioned
View Answer

Answer: b
Explanation: The Interrupt-request line is a control line along which the device is allowed to send the
interrupt signal.

2. The return address from the interrupt-service routine is stored on the

a) System heap
b) Processor register
c) Processor stack
d) Memory
View Answer

Answer: c
Explanation: The Processor after servicing the interrupts as to load the address of the previous process
and this address is stored in the stack.

3. The signal sent to the device from the processor to the device after recieving an interrupt is
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal
View Answer

Answer: a
Explanation: The Processor upon recieving the interrupt should let the device know that its request is
received.
4. When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
a) i,iv
b) ii,iii and iv
c) iii,iv
d) i,ii
View Answer

Answer: d
Explanation: None.

5. The time between the recieval of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time
View Answer

Answer: b
Explanation: The delay in servicing of an interrupt happens due to the time taken for contect switch to
take place.

6. Interrupts form an important part of _____ systems.

a) Batch processing
b) Multitasking
c) Real-time processing
d) Multi-user
View Answer

Answer: c
Explanation: This forms an imporatant part of the Real time system since if a process arrives with greater
priority then it raises an interrupt and the other process is stopped and the interrupt will be serviced.

7. A single Interrupt line can be used to service n different devices?

a) True
b) False
View Answer

Answer: a
Explanation: None
8. ______ type circuits are generally used for interrupt service lines
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
a) i,ii
b) ii
c) ii,iii
d) ii,iv
View Answer

Answer: a
Explanation: None

9. The resistor which is attached to the service line is called _____

a) Push-down resistor
b) Pull-up resistor
c) Break down resistor
d) Line resistor
View Answer

Answer: b
Explanation: This resistor is used to pull up the voltage of the interrupt service line.

10. An interrupt that can be temporarily ignored is

a) Vectored interrupt
b) Non-maskable interrupt
c) Maskable interrupt
d) High priority interrupt
View Answer

Answer: c
Explanation: The maskable interrupts are usually low priority interrupts which can be ignored if an
higher priority process is being executed.

11. The 8085 microprocessor respond to the presence of an interrupt

a) As soon as the trap pin becomes ‘LOW’
b) By checking the trap pin for ‘high’ status at the end of each instruction fetch
c) By checking the trap pin for ‘high’ status at the end of execution of each instruction
d) By checking the trap pin for ‘high’ status at regular intervals
View Answer
Answer: c
Explanation: The 8085 microprocessor are designed to complete the execution of the current instruction
and then to service the interrupts.

12. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to
non-privileged
a) A hardware interrupt is needed
b) A software interrupt is needed
c) Either hardware or software interrupt is needed
d) A non-privileged instruction (which does not generate an interrupt)is needed
View Answer

Answer: b
Explanation: A software interrupt by some program which needs some cPU service, at that time the two
modes can be interchanged.

13. Which interrupt is unmaskable?

a) RST 5.5
b) RST 7.5
c) TRAP
d) Both RST 5.5 and 7.5
View Answer

Answer: c
Explanation: The trap is a non-maskable interrupt as it deals with the on going process in the processor.
THe trap is initiated by the process being executed due to lack of data required for its completion.Hence
trap is unmaskable.

14. From amongst the following given scenarios determine the right one to justify interrupt mode of
data transfer
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
a) i and ii
b) ii
c) i,ii and iv
d) iv
View Answer

Answer: d
Explanation: None.
15. How can the processor ignore other interrupts when it is servicing one
a) By turning off the interrupt request line
b) By disabling the devices from sending the interrupts
c) BY using edge-triggered request lines
d) All of the mentioned
View Answer

Answer: d
Explanation: None.

his set of Basic Computer Organization Questions and Answers focuses on “Interrupts – 2”.

1. When dealing with multiple device interrupts, which mechanism is easy to implement?
a) Polling method
b) Vectored interrupts
c) Interrupt nesting
d) None of the mentioned
View Answer

Answer: a
Explanation: In this method the processor checks the IRQ bits of all the devices, which ever is enabled
first that device is serviced.

2. The interrupt servicing mechanism in which the requesting device identifies itself to the processor to
be serviced is ___________
a) Polling
b) Vectored interrupts
c) Interrupt nesting
d) Simultaneous requesting
View Answer

Answer: b
Explanation: None.

3. In vectored interrupts, how does the device identify itself to the processor?
a) By sending its device id
b) By sending the machine code for the interrupt service routine
c) By sending the starting address of the service routine
d) None of the mentioned
View Answer

Answer: c
Explanation: By sending the starting address of the routine the device ids the routine required and
thereby identifying itself.
4. The code sent by the device in vectored interrupt is _____ long.
a) upto 16 bits
b) upto 32 bits
c) upto 24 bits
d) 4-8 bits
View Answer

Answer: d
Explanation: None.

5. The starting address sent by the device in vectored interrupt is called as __________
a) Location id
b) Interrupt vector
c) Service location
d) Service id
View Answer

Answer: b
Explanation: None.

6. The processor indicates to the devices that it is ready to recieve interrupts ________
a) By enabling the interrupt request line
b) By enabling the IRQ bits
c) By activating the interrupt acknowledge line
d) None of the mentioned
View Answer

Answer: c
Explanation: When the processor activates the acknowledge line the devices send their interrupts to the
processor.

7. We describe a protocol of input device communication below:

i) Each device has a distinct address.
ii) The BUS controller scans each device in sequence of increasing address value to determine if the
entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following:
a) Programmed mode of data transfer
b) DMA
c) Interrupt mode
d) Polling
View Answer
Answer: d
Explanation: In polling the processor checks each of the device if they wish to perform data transfer and
if they do it performs the particular operation.

8. Which one of the following is true with regard to a CPU having a single interrupt request line and
single interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices is possible.
a) iii
b) i,iv
c) ii,iii
d) iii,iv
View Answer

Answer: a
Explanation: None.

9. Which table handle stores the addresses of the interrupt handling sub-routines?
a) Interrupt-vector table
b) Vector table
c) Symbol link table
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

10. _________ method is used to establish priority by serially connecting all devices that request an
interrupt.
a) Vectored-interrupting
b) Daisy chain
c) Priority
d) Polling
View Answer

Answer: b
Explanation: In Daisy chain mechanism, all the devices are connected using a single request line and
they’re serviced based on the interrupting device’s priority.

11. In daisy chaining device 0 will pass the signal only if it has _______
a) Interrupt request
b) No interrupt request
c) Both No interrupt and Interrupt request
d) None of the mentioned
View Answer

Answer: b
Explanation: In daisy chaining since there is only one request line and only one acknowledge line, the
acknowledge signal passes from device to device until the one with the interrupt is found.

12. ______ interrupt method uses register whose bits are set seperately by interrupt signal for each
device.
a) Parallel priority interrupt
b) Serial priority interrupt
c) Daisy chaining
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

13. ____ register is used for the purpose of controlling the status of each interrupt request in parallel
priority interrupt.
a) Mass
b) Mark
c) Make
d) Mask
View Answer

Answer: d
Explanation: None.

14. The anded output of the bits of the interrupt register and the mask register are set as input of:
a) Priority decoder
b) Priority encoder
c) Process id encoder
d) Multiplexer
View Answer

Answer: b
Explanation: In a parallel priority system, the priority of the device is obtained by anding the contents of
the interrupt register and the mask register.

15. Interrupts initiated by an instruction is called as _______

a) Internal
b) External
c) Hardware
d) Software
View Answer

Answer: b
Explanation

ocuses on “Exceptions”.

1. If during the execution of an instruction an exception is raised then

a) The instruction is executed and the exception is handled
b) The instruction is halted and the exception is handled
c) The processor completes the execution and saves the data and then handle the exception
d) None of the mentioned
View Answer

Answer: b
Explanation: Since the interrupt was raised during the exevution of the instruction, the instruction
cannot be executed and the exception is servied immediately.

2. _____ is/are types of exceptions.

a) Trap
b) Interrupt
c) System calls
d) All of the mentioned
View Answer

Answer: d
Explanation: None.

3. The program used to find out errors is called

a) Debugger
b) Compiler
c) Assembler
d) Scanner
View Answer

Answer: a
Explanation: Debugger is a program used to detect and correct errors in the program.

4. The two facilities provided by the debugger is

a) Trace points
b) Break points
c) Compile
d) Both Trace and Break points
View Answer

Answer: d
Explanation: The debugger provides us with the two facilities to improve the checking of errors.

5. In trace mode of operation is ________

a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete program is scanned
c) There is no effect on the program, i.e the program is executed without rectification of errors
d) The program is alted only at specific points
View Answer

Answer: a
Explanation: In trace mode the program is checked line by line and if errors are detected then
exceptions are raised right away.

6. In Breakpoint mode of operation

a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete program is scanned
c) There is no effect on the program, i.e the program is executed without rectification of errors
d) The program is alted only at specific points
View Answer

Answer: d
Explanation: The Breakpoint mode of operation allows the program to be alted at only specific locations.

7. The different modes of operation of a computer is

a) User and System mode
b) User and Supervisor mode
c) Supervisor and Trace mode
d) Supervisor, User and Trace mode
View Answer

Answer: b
Explanation: The user programs are in the user mode and the system crucial programs are in the
supervisor mode.

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8. The instructions which can be run only supervisor mode are

a) Non-privileged instructions
b) System instructions
c) Privileged instructions
d) Exception instructions
View Answer

Answer: c
Explanation: These instructions are those which can are crucial for the systems performance and hence
cannot be adultered by user programs, so is run only in supervisor mode.

9. A privilege exception is raised

a) When a process tries to change the mode of the system
b) When a process tries to change the piority level of the other processes
c) When a process tries to access the memory allocated to other user
d) All of the mentioned
View Answer

Answer: d
Explanation: None.

10. How is a privilege exception dealt with?

a) The program is alted and the system switches into supervisor mode and restarts the program
execution
b) The Program is stopped and removed from the queue
c) The system switches the mode and starts the execution of a new process
d) The system switches mode and runs the debugger
View Answer

Answer: a
Explanation: None.

 focuses on “Direct Memory Access”.

1. The DMA differs from the interrupt mode by

a) The involvement of the processor for the operation
b) The method accessing the I/O devices
c) The amount of data transfer possible
d) None of the mentioned
View Answer

Answer: d
Explanation: DMA is an approcah of performing data transfers in bulk between memory and the external
device without the intervention of the processor.

2. The DMA transfers are performed by a control circuit called as

a) Device interface
b) DMA controller
c) Data controller
d) Overlooker
View Answer

Answer: b
Explanation: The Controller performs the functions that would normally be carried out by the processor.

3. In DMA transfers, the required signals and addresses are given by the
a) Processor
b) Device drivers
c) DMA controllers
d) The program itself
View Answer

Answer: c
Explanation: The DMA controller acts like a processor for DMA transfers and overlooks the entire
process.

4. After the complition of the DMA transfer the processor is notified by

a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
d) None of the mentioned
View Answer

Answer: b
Explanation: The controller raises an interrupt signal to notify the processor that the transfer was
complete.

5. The DMA controller has _______ registers

a) 4
b) 2
c) 3
d) 1
View Answer

Answer: c
Explanation: The Controller uses the registers to store the starting address,word count and the status of
the operation.

6. When the R/W bit of the status register of the DMA controller is set to 1.
a) Read operation is performed
b) Write operation is performed
c) Read & Write operation is performed
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

7. The controller is connected to the ____

a) Processor BUS
b) System BUS
c) External BUS
d) None of the mentioned
View Answer

Answer: b
Explanation: The controller is directly connected to the system BUS to provide faster transfer of data.

8. Can a single DMA controller perform operations on two different disks simulteneously?
a) True
b) False
View Answer

Answer: a
Explanation: The DMA controller can perform operations on two different disks if the appropriate details
are known.

9. The techinique whereby the DMA controller steals the access cycles of the processor to operate is
called
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing
View Answer

Answer: c
Explanation: The controller takes over the processor’s access cycles and performs memory operations.

10. The technique where the controller is given complete access to main memory is
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode
View Answer
Answer: d
Explanation: The controller is given full control of the memory access cycles and can transfer blocks at a
faster rate.

11. The controller uses _____ to help with the transfers when handling network interfaces.
a) Input Buffer storage
b) Signal echancers
c) Bridge circuits
d) All of the mentioned
View Answer

Answer: a
Explanation: The controller stores the data to transfered in the buffer and then transfers it.

12. To overcome the conflict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
d) None of the mentioned
View Answer

Answer: b
Explanation: The BUS arbitrator is used overcome the contention over the BUS possession.

13. The registers of the controller are ______

a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
View Answer

Answer: c
Explanation: None.

14. When process requests for a DMA transfer

a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) process is temporarily suspended & Another process gets executed
View Answer

Answer: d
Explanation: The process requesting the transfer is paused and the operation is performed , meanwhile
another process is run on the processor.
15. The DMA transfer is initiated by _____
a) Processor
b) The process being executed
c) I/O devices
d) OS
View Answer

Answer: c
Explanation: The transfer can only be initiated by instruction of a program being executed.

ocuses on “Bus Arbitration”.

1. To resolve the clash over the access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
c) Priority access
d) None of the mentioned
View Answer

Answer: b
Explanation: The BUS arbitrator is used to allow a device to access the BUS based on certain parameters.

2. The device which is allowed to initiate data transfers on the BUS at any time is called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller
View Answer

Answer: a
Explanation: The device which is currently accessing the BUS is called as the BUS master.

3. ______ BUS arbitration appproach uses the involvement of the processor

a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
d) All of the mentioned
View Answer

Answer: a
Explanation: In this approach the processor takes into account the various parameters and assigns the
BUS to that device.

4. The circuit used for the request line is a _________

a) Open-collector
b) EX-OR circuit
c) Open-drain
d) Nand circuit
View Answer

Answer: c
Explanation: None.

5. The Centralised BUS arbitration is similar to ______ interrupt circuit

a) Priority
b) Parallel
c) Single
d) Daisy chain
View Answer

Answer: d
Explanation: None.

6. When the processor recieves the request from a device, it responds by sending _____
a) Acknowledge signal
b) BUS grant signal
c) Response signal
d) None of the mentioned
View Answer

Answer: b
Explanation: The Grant signal is passed from one device till the other until the device that has requested
is found.

7. In Centralised Arbitration ______ is/are is the BUS master

a) Processor
b) DMA controller
c) Device
d) Both Processor and DMA controller
View Answer

Answer: d
Explanation: The BUS master is the one that decides which will get the BUS.

8. Once the BUS is granted to a device ___________

a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
d) All of the mentioned
View Answer

Answer: a
Explanation: The BUS busy activated indicates that the BUS is already allocated to a device and is being
used.

9. The BUS busy line is made of ________

a) Open-drain circuit
b) Open-collector circuit
c) EX-Or circuit
d) Nor circuit
View Answer

Answer: b
Explanation: None.

10. After the device completes its operation _____ assumes the control of the BUS.
a) Another device
b) Processor
c) Controller
d) None of the mentioned
View Answer

Answer: b
Explanation: After the device completes the operation it releases the BUS and the processor takes over
it.

11. The BUS busy line is used

a) To indicate the processor is busy
b) To indicate that the BUS master is busy
c) To indiacate the BUS is already allocated
d) None of the mentioned
View Answer

Answer: c
Explanation: None.

12. Distributed arbitration makes use of ______

a) BUS master
b) Processor
c) Arbitrator
d) 4-bit ID
View Answer
Answer: d
Explanation: The device uses a 4bit ID number and based on this the BUS is allocated.

13. In Distributed arbitration, the device requesting the BUS ______

a) Asserts the Start arbitration signal
b) Sends an interrupt signal
c) Sends an acknowledge signal
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

14. How is a device selected in Distributed arbitration ?

a) By NANDing the signals passed on all the 4 lines
b) By ANDing the signals passed on all the 4 lines
c) By ORing the signals passed on all the 4 lines
d) None of the mentioned
View Answer

Answer: c
Explanation: The OR output of all the 4 lines is obtained and the device with the larger value is assigned
the BUS.

15. If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the
BUS based on the Distributed arbitration
a) Device A
b) Device B
c) Insufficient information
d) None of the mentioned
View Answer

Answer: b
Explanation: The device Id’s of both the devices are passed on the lines and since the value of B is
greater after the Or operation it gets the BUS.