2

VHDL 1076.1:
ANALOG AND MIXED-SIGNAL
EXTENSIONS TO VHDL
Ernst Christen *, Kenneth Bakalar* *
* Analogy, Inc., 9205 S. W. Gemini Drive, Beaverton, OR 97008, USA.

** Compass Design Automation, 5457 Twin Knolls Road, Columbia, MD 21045, USA.

ABSTRACT
VHDL 1076.1 is an extension to the well-established VHDL 1076 language to support
the description and simulation of continuous and mixed continuous/discrete systems. We
provide an overview ofthe extended language.

2.1. INTRODUCTION
IEEE VHDL 1076-1993 (The VHSIC Hardware Description Language) is designed for
the description and simulation of digital systems, supporting modeling at abstraction
levels from system level down to gate level. The standard, first approved in 1987 and
later revised and reaffirmed in 1993, has gained wide acceptance in the last few years.
The extension of VHDL to support continuous and mixed continuous/discrete systems
began in 1989 with the intent to include the necessary language changes in the VHDL
revision targeted for the 1993 release. It soon became apparent that the complexity of
the topic dictated the formation of a separate working group. The design of
VHDL 1076.1 began in 1993 under the auspices of the Design Automation Standards
Committee of the Computer Society of the IEEE, authorized under PAR 1076.1 and
supported by the Joint European Silicon Software Initiative (JESSI), the U.S. Air Force
Rome Laboratory, and the employers of participating engineers.
19

A. Vachoux et al. (eds.), Analog and Mixed-Signal Hardware Description Language

© Kluwer Academic Publishers 1997
20 CHAPTER 2

The work is now nearing completion. A language reference manual suitable for
submission to the IEEE balloting process will be completed by March 1997. The
extended language has informally been called VHDL-A; the committee now prefers the
designation VHDL 1076.1 or VHDL-AMS, the later to emphasize its mixed-signal
application.
We begin with a review of the foundations for the VHDL 1076.1 language: the design
objectives, the VHDL 1076 language, and the applicable mathematical theory. Most of
the presentation is devoted to the elements of the extended language. Each language
element is illustrated by a brief example. We conclude with selected examples illustrating
the use of the language for analog and mixed-signal applications.
The presentation assumes that the reader is familiar with the VHDL 1076 language. We
note that the language extensions described in this chapter have not yet been approved
as an IEEE standard, and changes are to be expected.

2.2. FOUNDATIONS
2.2.1. Language Design Objectives
The design objectives [1] for the extended language have been compiled from
requirements submitted by interested parties to the 1076.1 Working Group. They have
been analyzed and the results published [2]. We briefly summarize them here.
The design objectives require the VHDL 1076.1 language to be a superset of VHDL
1076-1993 [3], supporting the hierarchical description and the simulation of continuous
and mixed continuous/discrete systems with conservative and non-conservative
semantics. The language is required to support modeling at a variety of abstraction
levels in electrical and non-electrical disciplines. The systems to be described are lumped
systems (i.e. no partial differential equations), and the solution of the equations
describing the behavior of the system may include discontinuities. Interactions between
the discrete part of a model and its continuous part are to be supported in a flexible and
efficient manner, and support for frequency domain AC and noise simulation must be
provided.

2.2.2. VHDL 1076-1993

As a superset of the VHDL 1076-1993 language, the 1076.1 language design depends on
the existing 1076 language in many ways. This has both advantages and drawbacks. The
VHDL 1076 language [3] provides a firm pragmatic, semantic and syntactic foundation,
including structural and functional decomposition, separate compilation, a powerful
sequential notation and a type system. On the other hand, it presents many constraints
on the design of the 1076.1 language that can be violated only at great peril and with
good reason: its scope and visibility rules, the requirement for declaration before use, the
structure of names, the discrete simulation cycle, among others. The language design
challenge was to judiciously build on this foundation, by re-using as much of the existing
language as possible, and to extend the language only where necessary.
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 21

2.2.3. Theory of Differential-Algebraic Equations

The continuous aspects of the behavior of the lumped systems targeted by VHDL
1076.1 can be described by systems of ordinary differential and algebraic equations
(DAEs) with time as the independent variable. These equations have the form
F(x, dxldt, t) = 0 (1)
where F is a vector of expressions, x is the vector of unknowns in the equations, dxldt is
the vector of derivatives of the unknowns with respect to time, and t is time. There is no
alternative systematization with equivalent power and scope. Most such systems of
equations have no analytic solution, so in practice the solution must be approximated
using numerical techniques.
DAEs have been studied extensively by numerical mathematicians over the past 20
years, and the results summarized in [4] document, among other things, the conditions
under which solutions exist and the numerical properties of various DAE solution
methods. Although there are open issues, the theory is sufficiently mature to rely on,
particularly for the numerical solution of the DAEs.
It follows that VHDL 1076.1 must provide a notation for DAEs, but it does not follow
that the language definition must specify a technique for their solution. To the contrary,
the 1076.1 language can remain neutral with regard to the selection of numerical
methods. The presentation refers to the solution algorithm generally as the analog
solver. It is sufficient for the definition of the language to describe what system of
equations (at each time) is described by the text of a model, and to characterize the
results that the analog solver must achieve. This approach provides generous flexibility
to the implementor in choosing a suitable algorithm for the solution of the equations.
The numerical solution algorithms employed by the analog solver to find the values of
the unknowns cannot in general solve the equations exactly. The values of the
expressions in F(x, dx/dt, t) at a solution point will be nonzero, and simulation results
produced by a VHDL 1076.1 compliant simulator can be portable only within specified
tolerances. Although most algorithms use the concepts of absolute tolerance and relative
tolerance to allow a user to specify the quality of a solution, the details of how these
concepts are used differ from algorithm to algorithm. Some common ground can be
found in the practical advice given to users concerning the selection of the tolerances
(e.g., [4]): select the absolute tolerance according to the value at which a solution
component is essentially insignificant, and select the relative tolerance according to the
number of accurate digits needed in the solution.

2.3. THE 1076.1 LANGUAGE

In the design of the VHDL 1076.1 language we have used the existing VHDL language-
its syntax, semantics, stylistic quirks, unstated principles and definitional style-in
satisfying as many of the design requirements as possible, adding only what is essential
and still missing. Thorough exploitation of the powerful VHDL engine in all of its
aspects has led to some surprising and innovative design choices that set VHDL 1076.1
apart from other continuous system simulation languages.
22 CHAPTER 2

2.3.1. Quantities
The unknowns in the system of DAEs implied by the text of a model are analytic
functions of time; that is, they are piecewise continuous with a finite number of
discontinuities. Numerical solution algorithms simultaneously solve for the values of all
unknowns at certain times determined by the algorithm. None of the existing VHDL
objects get their values in a comparable fashion. For this reason, VHDL 1076.1
introduces a new class of value-bearing object, the quantity, to stand for the unknowns
in the DAEs.
Quantities must have scalar subelements of a floating point type to approximate the
continuous properties of the underlying formalism. A quantity object can appear in an
expression or anywhere else a value of the type is allowed. In the remainder of this
section, we describe the characteristics of scalar quantities. The characteristics of a
composite quantity are simply the aggregation of the characteristics of its scalar
subelements. The behavior of each scalar subelement is independent of the others.
Quantities can be declared anywhere a signal can be declared except in a package. The
following statement declares two quantities qa and qb of type real:
quantity qa, qb: Real;

A quantity can also be declared as an interface element in a port list. A quantity

interface element is called a quantity port, by analogy with signal ports. Interface
quantities support signal flow modeling. They have a mode, similar to the mode of an
interface signal. For instance, here is the entity declaration of a signal flow model of a
two-input adder. It has two interface quantities of mode in and one interface quantity of
mode out:
entity adder is
port ( quantity inl, in2: in Real;
quantity sum: out Real);
end entity adder;

When this model is instantiated each interface quantity is constrained to have the same
value as the quantity with which it is associated in a quantity association.
In addition to explicit quantities the language defines a number of implicit quantities.
Most will be discussed in Section 2.3.9, here we focus on the implicit quantities that are
essential to writing DAEs.
• For each quantity Q the name Q'Dot denotes a quantity of the same type as Q that
represents the derivative of Q with respect to time .

• For each quantity Q the name Q'Integ denotes a quantity of the same type as Q that
represents the integral of Q over time, from time 0.0 to the current time.

Since Q'Dot is a quantity the second derivative of Q with respect to time can be written
as Q'Dot'Dot, and higher order derivatives can be formed following the same pattern.
The notation for higher order integrals parallels the notation for higher order derivatives.
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 23

2.3.2. Tolerance Groups

Support for tolerances in VHDL 1076.1 is based on the notion of tolerance groups. A
tolerance group is a collection of solution elements--quantities and characteristic
expressions of the model (see Section 2.3.4)-that have the same tolerance properties,
i.e. accuracy requirements. Typically, the solution elements in a tolerance group have a
similar value range.
The tolerance group of a solution element is specified in the text of a model containing
that element. The binding of an element within a VHDL design entity can be delayed
until the corresponding component is instantiated. This allows a different tolerance
group binding for each instance of the element.
The tolerance properties of a group are not specified by the definition because different
simulation algorithms characterize tolerance in different ways. For a SPICE-like
simulator, the tolerance properties would include the "reltol" and "abstol" or "vntol"
numbers for the element, its derivatives and its integrals.
A tolerance group is notated within VHDL 1076.1 with a tolerance code of type String.
The tolerance code of a quantity is associated with its declaration, either directly or
indirectly through a declared subtype. For example, the statement
subtype Charge is Real tolerance "toll";

declares a floating point subtype Charge with a tolerance code "toll". Similarly, the
statements
quantity qO: Charge;
quantity ql, q2: Charge tolerance "toI2";

declare a quantity qQ of type Charge with a tolerance code "toll", and two
quantities ql and q2 of a subtype equivalent to Charge except that the tolerance
group has been changed to "toI2". The implicit quantity qQ 'Dot belongs to the same
tolerance group as qQ because it inherits its type and constraints from qQ.

2.3.3. Conservative Systems

Systems with conservation semantics-for example, electrical systems obeying
Kirchhoffs laws-merit separate treatment because they are so commonly encountered.
Special purpose syntax and semantics can provide a simplified notation that reduces the
risk of errors and thereby improves productivity. In VHDL 1076.1, equations
describing the conservative aspects of such a system need not be explicitly notated by
the modeler. Only the so-called constitutive equations remain the modeler's
responsibility.
The description of conservative systems uses a graph-based conceptual model. Take,
for example, an electrical network. Here, the vertices of the graph represent
equipotential nodes in the circuit and the edges represent branches of the circuit through
which current flows. In the language these ideas are expressed by branch quantities,
which are the unknowns in the equations describing conservative systems. There are
two kinds of branch quantities. Across quantities represent effort like effects, through
24 CHAPTER 2

quantities, flow like effects. Table 1 lists these effects for a number of physical
disciplines [5],[6].

Discipline Effort Flow

electrical voltage current

thermal temperature heat flow rate

hydraulic pressure volume flow rate

translational velocity force

rotational angular velocity torque

Table 1: Effort and Flow Effects for Selected Physical Disciplines

The constitutive equations of conservative systems are expressed by relating the across
and through quantities of one or several branches. For example, a resistor has a single
branch, and its constitutive equation (Ohm's law) relates the voltage across (the across
quantity) and the current through the resistor (the through quantity).
A branch quantity is declared with reference to two terminals. A terminal is declared to
be of some simple nature, or of a composite nature with scalar subelements that are of a
simple nature. Each simple nature represents a distinct physical discipline-electrical,
thermal, hydraulic, and so on. As an example, the following statements declare two
subtypes Vol tage and Curren t with their respective tolerance codes, a simple
nature Electrical, two terminals of that nature, and an across and two through
quantities between the two terminals.
subtype Voltage is Real tolerance "voltage";
subtype Current is Real tolerance "current";
nature Electrical is
Voltage across Current through;
te~inal tl, t2: Electrical;
quantity v across il, i2 through tl to t2;

A nature declaration may also declare an array nature or a record nature. The
corresponding declarations parallel those of composite type declarations, and the
sub nature declaration serves a purpose similar to the subtype declaration. The
predefined attribute N' Across denotes the across type of a nature N; in the example it is
Vol tage. Similarly, N'Through denotes the through type of N, in the example,
Current.
The type of a branch quantity is derived from the nature of its terminals. It is a
composite type if the nature of one of its terminals is composite. In the example, the
across quantity v which represents the potential difference between the two terminals is
of type Vol tage and its tolerance code is "vol tage". Similarly, the type of the two
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 25

through quantities il and i2, which represent two parallel branches, is Current, and
their tolerance code is "current".
The two terminals of a branch quantity must have either both scalar natures, or both the
same composite nature, or one a scalar nature and the other a composite nature. In either
case the scalar subelements of both natures must have the same simple nature. The
terminals are called the plus terminal and minus terminal of the branch quantity and the
direction of the branch is plus to minus-in an electrical system, the direc;tion of
positive current flow. The following statements declare an array nature, two terminals
of that nature, and declarations for through quantities for the possible combinations of
scalar and composite plus and minus terminals. Figure 1 shows the resulting quantities
graphically.
nature Electrical_vector is array(Natural range <» of Electrical;
terminal t3, t4: Electrical_vector(l to 5);
quantity i3 through t3 to tl;
quantity i4 through t2 to t4;
quantity i5 through t3 to t4;

t1 t3 t2 t3
plus terminal

i1 i2 i5

minus terminal
t2 t1 t4 t4
Figure 1: Scalar and Composite Branch Quantities
The tolerance group of a branch quantity is determined by its subtype. It can be
overwritten in a subnature declaration or in the declaration of the branch quantity. The
following statements declare a subnature Highvoltage with appropriate tolerance codes,
two terminals of that subnature, and two across and one through quantities:
subnature Highvoltage is Electrical
tolerance "highvoltage" across "highcurrent" through;
terminal t5, t6: Highvoltage;
quantity vhl across ihl through t5 to t6;
quantity vh2 tolerance "voltage" across t5 to t6;

The tolerance groups for the branch quantities vhl and ihl are those defined by the
subnature declaration: they are "highvoltage" and "highcurrent". The tolerance
group for the across quantity vh2 is "vol tage".
A terminal may be declared anywhere a signal declaration is allowed. In particular, a
terminal, like a signal, can be a port of an entity. For instance, the following statement
declares the terminal ports of a diode:
port (terminal anode, cathode: Electrical);

When a model with this port list is instantiated the connection of terminal ports
constructs nodes in the hierarchical description at which Kirchhoff's laws (or their
equivalents in other disciplines) hold. The corresponding conservation equations are
26 CHAPTER 2

automatically extracted from the graph created by the declared branch quantities and
terminals and the association of terminals into nodes.
The declaration of a simple nature creates a reference terminal (a "ground") which is
shared by all terminals with elements of that simple nature. The reference terminal of a
terminal T of nature N is designated N'Reference. If a branch quantity declaration
includes only a single terminal then the minus terminal of the branch quantity is defined
to be the reference terminal of the simple nature of the specified terminal. In other
words, the declaration creates a branch to ground. The declaration of T itself creates two
quantities:
• The reference quantity T'Reference is an across quantity with T and N'Reference as
its plus and minus terminals.
• The contribution quantity T'Contribution is a through quantity whose value is equal
to the sum of all through quantities incident to T (with appropriate sign).

If T is composite, so are T'Reference and T'Contribution, and the rules apply to each
scalar subelement ofT.

2.3.4. Simultaneous Statements

VHDL 1076.1 supplements the sequential and concurrent statements of VHDL 1076
with a new class oflanguage statements for notating differential and algebraic equations.
Simultaneous statements contain ordinary VHDL expressions that can be evaluated in
the ordinary way. However, the interpretation placed on the resulting value and the
effect on the value-bearing objects of the model is novel.
Simultaneous statements can appear anywhere a concurrent signal assignment is
allowed. The basic form is the simple simultaneous statement whose simplified syntax is
[label :1 simple_expression == simple_expression;

For instance, the constitutive equation ofa resistor could be written as i == vir;
where i and v are a through and an across quantity, respectively, representing the
current through and the voltage across the resistor, and r is the resistance value. The
expressions may have composite values, in which case there must be a matching
subelement on the left for each subelement on the right. The expressions may refer to
quantities, signals, constants, shared variables, literals and functions. When the analog
solver has properly established the values of each quantity the matching subelements of
the expressions will be (approximately) equal.
The language defines three additional forms of simultaneous statements.
• The simultaneous procedural statement allows a user to notate DAEs using a
sequential style. This style is more familiar to model writers with experience in one
of the continuous system simulation languages like ACSL [7]. The simultaneous
procedural statement can include any sequential statement of the VHDL language,
except wait statements and signal assignments.
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 27

• The simultaneous case statement and the simultaneous if statement support the
description of piecewise defined behavior. Each contains an arbitrary list of
simultaneous statements in its statement parts, including nested simultaneous case
and if statements. Only the simultaneous statements selected by the case expressions
and chosen by the conditional expressions are considered by the analog solver.

The example of a limiting voltage amplifier shown in Figure 2 brings together many of
the new language concepts: terminal ports, branch quantities, and simultaneous
statements.
entity limiter is
generic (gain: Real := 1.0; limit: Real);
port ( terminal inp, inm: Electrical; -- input terminals
terminal p, m: Electrical); -- output terminals
end entity limiter;

architecture simult of limiter is architecture proc of limiter is

quantity yin across inp to inm; quantity yin across inp to inm;
quantity v across i quantity v across i
through p to m; through p to m;
begin begin
if gain*vin > limit use procedural
v -- limit; variable vout: Voltage;
elsif gain*vin < -limit use begin
v == - limit; vout .- gain * yin;
else v := vout;
v -- gain * yin; if vout > limit then
end use; v := limit;
end architecture simult; elsif vout < -limit then
v .- - limit;
end if;
end procedural;
end architecture proc;

Figure 2: Simultaneous and Procedural Implementation of a Limiting Amplifier

The equations explicitly denoted by simultaneous statements and the implicit equations
that are a consequence of the conservation laws and interconnections are mapped to a
single underlying formalism-the characteristic expression. A characteristic expression
corresponds to one expression in F(x, dx/dt, t). Each simple simultaneous statement has
a collection of characteristic expressions, one for each scalar subelement of the
expression.
The analog solver determines the value of each quantity such that the values of all
characteristic expressions are close to zero and thus solves the DAEs of the model. Each
characteristic expression, like each quantity, belongs to a tolerance group. The default
tolerance group for the characteristic expression of a simple simultaneous statement
whose left hand side expression is the name of a quantity is the tolerance group of this
quantity. If the statement is not in this form but its right hand side expression is the
name of a quantity, then again the default tolerance group of the characteristic
expression corresponding to the statement is that of the quantity. Otherwise, the model
writer must specify a tolerance group as part of the statement. For example, the
28 CHAPTER 2

following statement explicitly specifies the tolerance group for the simple simultaneous
statement describing a resistor:
i == v / r tolerance "toll";
The language definition makes another concession to the realities of practical solution
algorithms. Iterative algorithms assume that during a sequence of iterations only the
quantity values change, controlled by the iterative engine. If a simultaneous statement
includes shared variables or calls to impure functions, and if their values change during a
sequence of iterations for reasons other than changes in function arguments, then the
simultaneous statement must be marked impure. By default, simultaneous statements
are pure, and models that include impure simultaneous statements are potentially
nonportable. Note that a simultaneous statement that includes a call to the impure
function NOW is pure, because time does not advance during iterations: NOW always
returns the same value. It is prudent to avoid statements with side effects in
simultaneous statements, for example assert and report statements, because their effects
are not controlled by the model in an iterative context.

2.3.5. Time and the Simulation Cycle

Synchronization between the analog solver and the VHDL kernel process requires a
common formulation for simulation time that encompasses the requirements for both
continuous and discrete simulation. This demand is met by creating a new definitional
type named Universal_Time, by analogy with Universal_Integer and Universal_Real.
Universal_Time must have sufficient precision to represent each value of the physical
type Time exactly. The representation is required to equal or exceed in precision the
members of the floating point class of types. The simulation cycle is recast using values
of Universal_Time for the kernel variables Tc, which represents the current simulation
time, and Tn, which represents the next time that a driver will become active or a
process will resume. Function NOW is redefined to return the value of the current
simulation time (a value of the type Universal_Time) converted with truncation to the
nearest value of physical type Time. It is overloaded with another function NOW that
returns the value of the current simulation time truncated to the nearest value of type
Real. Similarly, the predefined function S'Last_Event has been overloaded with a Real
valued function that returns the amount of time that has elapsed since the last event
on S.
The VHDL simulation cycle has been augmented to include the execution of the analog
solver. The analog solver executes in each simulation cycle just before the current
simulation time advances. The solver establishes a sequence of solutions to the DAEs
(analog solution points, or ASPs) at suitable intervals between the current digital time
and the time of the next event. The definitions guarantee that the value of a quantity is
always correct when a digital process reads the quantity, and that the value of a digital
signal appearing in a simultaneous statement is always correct whenever the
corresponding expression is evaluated.
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 29

2.3.6. AID and D/A Interaction

If any of a set of specified quantities passes designated amplitude thresholds before the
sequence of ASPs is extended all the way to the time of the next discrete event, the
analog solver will terminate prematurely. For any scalar quantity Q the Boolean signal
Q' Above(level) is TRUE if Q > level and FALSE if Q < level. An event occurs on
Q' Above(level) when the sign of the expression Q - level changes. Threshold crossing
can be used for AID conversions, as shown in the following example of a comparator.
entity comparator is
generic (level: Real := 2.5); threshold
port ( terminal a: Electrical; electrical input
signal s: out Bit); bit output
end entity comparator;

architecture simple of comparator is

quantity v across a; across quantity to ground
begin
s <= '1' when v'Above(level) v > level
else '0'; v < level
end architecture simple;

A digital process that is sensitive to such a signal executes at the exact time of the
threshold crossing, which may have no exact representation in physical type Time. Such
times are called offset times. Any process resuming as a consequence of a delta-delayed
signal assignment in a process executing at an offset time also executes at the same offset
time, and postponed processes execute, as usual, immediately before time advances.
However, any delayed signal assignment occurs at a time exactly representable in
physical type Time, converted by truncation.
If a discontinuity occurs in the solution of the DAEs the underlying mathematical
framework requires that the analog solver be notified. The break mechanism serves this
purpose: a model must generate a kind of pseudo-event at the time of each discontinuity
in the model. A discontinuity will occur if, for example, a quantity is equated to a signal
in a simple simultaneous statement and an event occurs on that signal. There is no
known algorithm that can reliably and efficiently detect and successfully correct for
discontinuities without explicit notification of the time of occurrence. Therefore, the
language includes a break statement that has both a sequential and a concurrent form.
The execution of the break statement creates an event on the implicit BREAK signal; the
signal itself is not visible in the model. The language semantics require the analog solver
to assume a discontinuity whenever the driver of the BREAK signal is active. The break
statement includes a provision for specifying new initial conditions for selected
quantities, to be applied after the discontinuity. The following example demonstrates
the use of a break statement in a simple DIA converter.
entity dac is
generic (vhigh: Real := 5.0); output voltage for s='l'
port ( signal s: in Bit; bit-valued input
terminal a: Electrical); output
end entity dac;
30 CHAPTER 2

architecture simple of dac is

quantity v across i through a;-- branch quantities to ground
begin
if s='O' use
v 0.0; low output
else
v vhigh; high output
end use;
break on s; announce discontinuity
end architecture simple;

A model must include an appropriate break statement if the name of a signal appears in
an expression in a simultaneous statement and an event on the signal causes a
discontinuity. Similarly, a break statement is required if a discontinuity is introduced by
the selection of a different set of simultaneous statements, for example when the value
of the condition in a simultaneous if statement changes. However, break statements are
not needed for discontinuities in one of the predefined quantities S'Ramp or S'Slew (see
Section 2.3.9), even if these quantities appear in expressions in a simultaneous
statement.

2.3.7. Initialization and the Quiescent Point

The solution of a system of DAEs in any continuous interval depends only on the
values of the unknowns at the beginning of the interval [4]. These values must
themselves be a solution of the DAEs and, depending on the initialization scheme, a
number of other equations derived from the original ones [8]. The continuous model
must be initialized using a suitable algorithm before a simulation begins and re-initialized
at each discontinuity.
In the general case, there are many different initial conditions that satisfy the DAEs
because during initialization there are more unknowns than equations (both x and dx/dt
are unknowns during initialization). The selection of a particular member of the set is
dependent on ancillary information, either built-in conventions or user selected.
The 1076.1 language distinguishes between the actual initialization, which extends the
initialization steps defined by VHDL 1076 with similar steps for the continuous
portion of a model, and finding the quiescent point of the model. For a purely
continuous model the quiescent point represents, in the absence of user specified initial
conditions, the DC operating point of the model. This solution is quite important to
analog designers and it is an essential part of frequency domain simulations (see
Section 2.3.8).
The language defines the quiescent point of a model as the state of the solution
immediately before the postponed processes are about to be executed at time 0.0. While
finding the quiescent point the system of equations (1) is augmented, in the absence of
user specified initial conditions, by
dxldt= 0 (2)
Initial conditions are specified with the break statement described earlier, for instance:
break ql => expressionl, q2 => expression2;
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 31

The effect of specifying initial conditions is that suitable equations from the set (2) are
replaced by the initial conditions. For the example they are the equations dq lldt = 0 and
dq21dt = O. This can only happen if q 1'Dot and q2'Dot appear in the text of the model,
because otherwise these equations are not part of (2). Investigations are underway at the
time of this writing to extend the syntax of the break statement to allow for a more
flexible specification of initial conditions.
The kernel process controls the driver of the predefined signal DOMAIN whose type is
the enumerated type DOMAIN_TYPE. During initialization the value of the DOMAIN
signal is set to INITIALIZATION_DOMAIN. When the quiescent point has been
reached the kernel assigns a new value to the DOMAIN signal: TIME_DOMAIN if the
quiescent point has been found on behalf of a time domain simulation,
FREQUENCY_DOMAIN if a frequency domain simulation follows. As a consequence
of this signal assignment the execution of the postponed processes is skipped, and at
least one more delta cycle is executed to update the DOMAIN signal. This makes it
possible to resume a process when the quiescent point has been reached, and to define
different behavior for finding the quiescent point, time domain simulation, and
frequency domain simulation.

2.3.8. Frequency Domain Modeling and Simulation

A designer is often interested in the behavior of a continuous system in the frequency
domain. Many systems whose frequency domain solution is of interest are operating in
a nearly linear region, and special algorithms are available that can compute their
frequency domain response very efficiently. The 1076.1 language includes definitions
that support SPICE-like AC and noise simulations in a portable way, based on the
small-signal model derived from the equations (l).
The small-signal model is defined as the linear term of the Taylor expansion, with
respect to all quantities, of the equations (1) obtained when the value of the DOMAIN
signal is FREQUENCY_DOMAIN, with the partial derivatives evaluated at the
quiescent point. The small-signal model is a linear incremental model [9] described by a
linear system of equations with the increments of the quantities as unknowns.
Therefore, the results of small-signal simulations are only approximations to the true
behavior of a physical system.
The system of equations describing the small-signal model is homogeneous unless the
model specifies special frequency domain stimulus. The language defines two kinds of
source quantities for this purpose. The spectral source quantity specifies stimulus for a
frequency domain AC simulation, the noise source quantity specifies a noise source for
the frequency domain noise simulation. Source quantities must be declared using a
special syntax; their type can be a composite type. The following example shows the
model of a current source. Its value is constant over time, and it also specifies stimulus
for frequency domain AC and noise simulations through the spectral source quantity
~ac and the noise source quantity ~ns.

entity current_source is
generic (dc, ac_mag, ac-phase, ns_mag: Real .- 0.0);
port (terminal p, m: Electrical);
end entity current_source;
32 CHAPTER 2

architecture unlikely of current_source is

quantity i through p to rn;
quantity ~ac: Real spectrum ac_rnag, ac-phase;
quantity ~ns: Real noise ns_rnag;
begin
i == dc + ~ac + ~ns;
end architecture unlikely;

The expressions defining the magnitude for a source quantity or the phase for a spectral
source quantity are general VHDL expressions. In particular, they may include the
names of other quantities, which allows, for example, to define bias dependent noise.
Additionally, these expressions may include calls to the predefined function
FREQUENCY that returns the current simulation frequency. It is the only place where
this function may be called, i.e. the language supports the specification of frequency
dependent stimulus, but not of frequency dependent behavior.

2.3.9. Miscellaneous
VHDL 1076.1 contains a variety of other facilities that we briefly summarize here.
Besides the explicit quantities and the implicit quantities already discussed, the language
defines a number of additional implicit quantities. Most have been defined to simplify
the writing of VHDL 1076.1 models; their functionality is defined by means of an
equivalent block. In the descriptions Q and S represent a quantity and a signal.
• The quantity Q'Delayed(T), where T is a static expression of type Real, implements
an ideal delay, i.e. the value of quantity Q at a fixed interval T in the past. Its type is
that of Q; it can be a composite type.
• The quantity Q'Zoh(T, Initial_Delay), where T and Initial_Delay are static
expressions of type Real, implements a zero order hold with a sampling period T and
a first sampling after Initial_Delay seconds. Its type is that of Q; it can be a
composite type.
• The quantity Q'Ltf(Num, Den) implements a Laplace transfer function with Q as
input, i.e. the ratio of two polynomials in the Laplace variable s, with the numerator
polynomial coefficients specified by Num and the denominator polynomial
coefficients specified by Den. Num and Den must static expressions of the new
predefined type Real_vector. The type of Q'Ltf is that of Q; it must be a scalar
type.
• The quantity Q'Ztf(Num, Den, T, Initial_Delay) implements a z-domain transfer
function with Q as input, i.e. the ratio of two polynomials in z-l, with the numerator
polynomial coefficients specified by Num and the denominator polynomial
coefficients specified by Den. Its sampling period is T, and the first sampling occurs
after Initial_Delay seconds. Num and Den must be static expressions of the new
predefined type Real_vector, T and Initial_Delay must be static expressions of type
Real. The type of Q'Ztf is that of Q; it must be a scalar type.
• The quantity Q'Slew(Max_Rising_Slope, Max_Falling_Slope) follows Q, but its
change over time is constrained by the specified maximum slopes. Max_Rising_Slope
and Max_Falling_Slope must be static expressions of type Real. If
Max_Falling_Slope is not specified it defaults to Max_Rising_Slope; if neither is
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 33

specified the value of Q'Slew is identical to the value of Q at all times. The type of
Q'Slew is that of Q; it must be a scalar type .
• The quantity S'Slew(Max_Rising_Slope, MaxJalling_Slope) where S is a signal ofa·
floating point type follows S, but ramps linearly with one of the specified maximum
slopes from its current value when S has an event to the new value of S.
Max_Rising_Slope and Max_Falling_Slope must be static expressions of type Real.
If MaxJailing_Slope is not specified it defaults to Max_ RisinLSlope; if neither is
specified the value of S'Slew is identical to the value of S at all times. The type of
S'Slew is that of S. A model using S'Slew does not need break statements for the
discontinuities in S'Slew.
• The quantity S'Ramp(Tr, Tf) where S is a signal of a floating point type follows S,
but ramps linearly over the specified rise time Tr or fall time Tf from its current
value when S has an event to the new value of S. Tr and Tf must be static
expressions of type Real. If Tf is not specified it defaults to Tr; if neither is specified
they both default to 0.0, i.e. the value ofS'Ramp is identical to the value ofS at all
times. The type of S'Ramp is that of S. A model using S'Ramp does not need break
statements for the discontinuities in S'Ramp.

Continuous models often need mathematical functions to describe the behavior of a

physical device. Such functions are not part of the 1076.1 language, but are available
through the 1076.2 standardization effort as VHDL packages.
Finally, a necessary condition for the solvability of the system of equations (1) is that
there be as many equations as unknowns. The definition of the 1076.1 language includes
rules enforceable for each design entity that guarantee that this condition is satisfied.

2.4. EXAMPLES
We will demonstrate the use of the VHDL 1076.1 language with examples from a
variety of application areas.

2.4.1. Modeling Infrastructure

The first example builds the infrastructure necessary to model electrical and thermal
devices in the form of two packages, one for each discipline. The packages are shown in
Figure 3.
In Section 2.3.3 we have shown the declaration of a simple nature and an array nature
for electrical applications. Here we expand on what we showed there by including an
alias for the reference terminal in electrical systems; we name it ground for simplicity.
The declaration of package thermal_system completely parallels that of the electrical
package. It reflects that according to Table 1 the across and through quantities in a
thermal model represent temperature and heat flow rate, by declaring subtypes of these
names.
34 CHAPTER 2

package electrical_system is package thermal_system is

subtype Voltage is Real
tolerance "voltage";
subtype Current is Real
tolerance "current";
nature Electrical is
Voltage across
Current through;
alias ground is
Electrical'Reference;
nature Electrical_vector is
array(Natural range <»
of Electrical;
end package electrical_system;
subtype Temperature is Real
tolerance "temp";
subtype Heatflow is Real
tolerance "heatflow";
nature Thermal is
Temperature across
Heatflow through;
alias ground_th is
Thermal 'Reference;
nature Thermal_vector is
array(Natural range <»
of Thermal;
end package thermal_system;

Figure 3: Packages for Electrical and Thermal Disciplines

2.4.2. Quenching Circuit

The next example is a quenching circuit for a superconducting magnet. It demonstrates
the use ofVHDL 1076.1 for a mixed technology application and is shown in Figure 4.
load

thermal
resistances

super- quenching diodes common

conducting with thermal capacity heat sink
magnet for packages
Figure 4: Quenching Circuit for Superconducting Magnet
While the magnet is superconducting it carries a current of several thousand Amperes.
The voltage across the magnet is zero but builds up quickly if superconductivity is lost.
To avoid destruction the magnet is protected by two shunt diodes whose current load is
balanced by a transformer. The diodes are mounted on a common heat sink held at a
temperature of 4 Kelvin.
2.4.2.1. Current Source and Inductor
Current source and inductor are basic electrical device models. They are shown in
Figure 5, assuming that the packages defined in Section 2.4.1 reside in a library
disciplines.
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 35

library disciplines; library disciplines;

use use
disciplines.electrical_system.all; disciplines.electrical_system.all;
entity isrc is entity inductor is
generic (ide: Real); generic (inductance: Real);
port(terminal p,m: Electrical); port(terminal p, m: Electrical);
end entity isrc; end entity inductor;

architecture one of isrc is architecture linear of inductor is

quantity i through p to m; quantity v across i
begin through p to m;
i == ide; begin
end architecture one; v inductance * i'Dot;
end architecture linear;

Figure 5: VHDL 1076.1 Models for Current Source and Inductor

Both models are straightforward. Their entity declarations define one generic and two
terminals with nature Electrical. The architectures declare a branch between the
two terminals. In the current source only the through quantity, i.e. the branch current,
has been declared, while the architecture for the inductor declares both the across and
the through quantity. Finally, each architecture includes a simple simultaneous
statement that describes the behavior of the device.
2.4.2.2. Ideal Transformer with N Windings
This model implements an ideal electrical transformer with an arbitrary number of
windings. We first presume the existence of a package real_aux that has been
compiled into library work and that declares a type Rea l_Ma t r i x as a two-
dimensional array of real numbers and overloads the multiply operator "*,, to
implement a product of a real matrix and a real vector. Using this package the
VHDL 1076.1 implementation of the model of an ideal N-winding transformer is shown
in Figure 6.
The entity includes the declaration of a generic ml that is a matrix containing the self
inductance values on its diagonal and the mutual inductance values on its off-diagonal
elements. The two terminals p and rn are unconstrained arrays; their length will only be
known when the model is instantiated.
The architecture includes the declaration of an across and a through quantity. The
branch quantity declaration forces both terminals to have the same length. Because the
terminals are arrays, both branch quantities are arrays, too, of the same length.
Consequently, the simple simultaneous statement is composite, and its semantics
require that the number of rows in matrix rnl equals the length of v. Finally, the
overloaded multiply operator requires the number of columns in matrix rnl to equal the
length of vector i ' Dot, which is equal to the length of i. The type conversion of
i ' Dot to Real_vector is necessary because the type of i and i ' Dot is
Electrical_vector 'Through instead of Real_vector as required by the
overloaded operator.
36 CHAPTER 2

library disciplines;
use disciplines.electrical_system.all;
use work. real_aux. all;
entity xfrm is
generic (ml: Real_matrix); -- matrix of self/mutual inductances
port (terminal p, m: Electrical_vector);
end entity xfrm;

architecture one of xfrm is

quantity v across i through p to m;
begin
v == ml * Real_vector(i'Dot);
end architecture one;

Figure 6: VHDL 1076.1 Model of an N-Winding Transformer

We note that if the length of the terminals p and m is 1 this model degenerates
functionally to the inductor model shown in Figure 5, as expected.
2.4.2.3. Thermal Resistor and Thermal Capacitor
Similar to the basic electrical device models shown in Section 2.4.2.1 the models for
thermal resistors and capacitors shown in Figure 7 are straightforward. Compared to
their electrical counterparts (not shown) the only difference is in declaring a different
nature for the two terminals.

library disciplines; library disciplines;

use disciplines.thermal_system.all;
entity resistor_th is
generic (r_th: Real);
port (terminal p, m: Thermal);
end entity resistor_th;
use
disciplines. thermal_system. all;
entity capacitor_th is
generic (c_th: Real);
port(terminal p, m: Thermal);
end entity capacitor_th;

architecture one of resistor_th is architecture one of capacitor_th

quantity temp across power is
through p to m; quantity temp across power
begin through p to m;
assert r_th /= 0.0; begin
power == temp / r_th; power c_th * temp'Dot;
end architecture one; end architecture one;

Figure 7: VHDL 1076.1 Models of Thermal Resistor and Thermal Capacitor

2.4.2.4. Diode with Self Heating
The last model for this example implements the protection diodes of the quenching
circuit. It is a diode with self heating. The diode consists of two electrical branches
between its anode and cathode and a thermal branch between its junction and thermal
ground (Figure 8).
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 37

anOde~ cathode electrical

branches

junction ~ ground_th thermal

~ branch
Figure 8: Diode with Self Heating
For the electrical branches Voltage and Current are the across and through types, as
described in Sections 2.3.3 and 2.4.1. For the thermal branch the corresponding types
are Temperature and Heatflow. The VHDL 1076.1 implementation of the model IS
shown in Figure 9.
library disciplines,ieee;
use disciplines.electrical_systern.all;
use disciplines.therrnal_systern.all;
use ieee.math_real.all;
entity diode_th is
generic ( isO: Real := 1.0e-14;
n, area: Real := 1.0;
tau, cjO, phi, rd: Real := 0.0);
port (terminal anode, cathode: Electrical;
terminal junction: Thermal);
end entity diode_th;

architecture one of diode th is

quantity v across id, ic through anode to cathode;
quantity q: Charge; -- junction charge
quantity vt: Voltage; -- thermal voltage
quantity temp across power through ground_th to junction;
constant boltzmann: Real := 1.3806226e-23;
constant electron_charge: Real := 1.602191e-19;
begin
id area * isO * (exp((v rd * id)/(n * vt)) - 1.0);
q tau * id - 2.0 * cjO * sqrt(phi * (phi - v));
ic q'Dot;
vt temp * boltzmann / electron_charge;
power == v * id;
end architecture one;

Figure 9: VHDL 1076.1 Model of a Diode with Self Heating

In the architecture we declare the electrical and thermal branches, two free quantities and
two physical constants. The first simultaneous statement defines the current in the
resistive branch; it depends on the thermal voltage vt. The second and third statements
define the current in the capacitive branch. vt depends on the temperature at the
junction, as shown in the fourth statement, and finally the power dissipated in the diode
becomes the value of the through source that forms the thermal branch.
2.4.2.5. Quenching Test Bench
To complete this example we list in Figure 10 the test bench that describes the system
shown in Figure 4. For simplicity we use direct instantiation for the component
38 CHAPTER 2

instantiation statements. Note the component instantiation statement for the balancing
transformer, which makes it a transformer with two windings.

library disciplines;
use disciplines.electrical_system.all;
use disciplines.thermal_system.all;
use work. real_aux. all;
entity quenching is
end entity quenching;

architecture test_bench of quenching is

te~inal e1, e2, e3: Electrical;
terminal t1, t2, t3: Thermal;
constant ml: Real_matrix(l to 2, 1 to 2) :=
( (1. Oe-4, -1. Oe-4) , (-1. Oe-4, 1. Oe-4) ) ;
begin
iO: entity isrc(one) generic map (idc => 18.0e3)
port map (p => ground, m => e3);
superl: entity inductor (linear) generic map (inductance => 0.03)
port map (p => e3, m => ground);
bal: entity xfrm(one) generic map (ml => ml)
port map (p(l) => e3, m(l) => e1, p(2) => e3, m(2) => e2);
d1: entity diode_th(one) generic map (isO => 1.0e-6)
port map (anode => e1, cathode => ground, junction => t1);
d2: entity diode_th(one) generic map (isO => 1.0e-6)
port map (anode => e2, cathode => ground, junction => t2);
cd1: entity capacitor_th(one) generic map (c_th => 2.0e-5)
port map (p => t1, m => ground_th);
cd2: entity capacitor_th(one) generic map (c_th => 2.0e-5)
port map (p => t2, m => ground_th);
rcs1: entity resistor_th(one) generic map (r_th => 0.08)
port map (p => t1, m => t3);
rcs2: entity resistor_th(one) generic map (r_th => 0.08)
port map (p => t2, m => t3);
sink: entity capacitor_th(one) generic map (c_th => 1.0e-3)
port map (p => t3, m => ground_th);
rad: entity resistor_th(one) generic map (r_th => 1.0e-4)
port map (p => t3, m => ground_th);
end architecture test_bench;

Figure 10: Test Bench for the Quenching Circuit

2.4.3. Bouncing Ball

The next example describes a ball bouncing at a surface with infinite elasticity. It is the
model of a closed system that demonstrates a number of language features:
• The use of a simultaneous if statement to switch between two simple simultaneous
statements
• The use of a concurrent break statement to specify initial conditions
• The use of an implicit signal Q' Above(level) to detect when the ball hits the ground
• The use of a concurrent break statement to handle the discontinuity in the velocity
when the ball hits the ground

The model is shown in Figure 11.

VHDL J076. J: Analog and Mixed-Signal Extensions to VHDL 39

entity bouncer is
end entity bouncer;

architecture ball of bouncer is

quantity v: Real tolerance "velocity";
quantity z: Real tolerance "elevation"; -- above ground
constant g: Real := 9.81; gravity constant in m/s**2
constant air_res: Real := 0.001; -- 11m
begin
z'Dot == v;
if v > 0.0 use
v'Dot -g - v**2*air_res;
else
v'Dot -g + v**2*air_res;
end use;
break v => -v when not z'Above(O.O); when ball hits ground
break v => 0.0, z => 10.0; initial conditions
end architecture ball;

Figure 11: VHDL 1076.1 Model of a Bouncing Ball

The equations describing this system are the equations of motion. Gravity always pulls
towards the surface, while the direction of the force due to air resistance opposes the
direction of motion. This is described by the simultaneous statements in the model.
When the ball hits the ground the velocity changes sign instantaneously, due to the
infinite elasticity of the surface. The model detects the impact using the implicit signal
z' Above(O.O). The condition not z' Above(O.O) becomes True when z crosses
elevation 0.0 from above. The first break statement executes at this time and sets the
initial condition for the velocity v for the next time interval to -v. It also announces a
discontinuity to the analog solver, which will apply this initial condition at t+ of the
discontinuity. Finally, the second break statement describes initial conditions at
time 0.0, to be used when finding the quiescent point.

2.4.4. Silicon Controlled Rectifier

The final example is a simple silicon controlled rectifier (SCR). The model is shown in
Figure 12. The SCR turns on when it is forward biased and the control voltage is larger
than the on voltage. It turns off when the current flowing through the SCR is smaller
than the holding current and the control voltage is smaller than the on voltage. In the
model these conditions are expressed by the value of signal off. Current flow through
the SCR has a diode characteristic approximated by two straight line segments. Current
is flowing when the SCR is on and the voltage across it is larger than vdrop. This
condition is encoded in signal zero_current, whose value controls which of the two
simple simultaneous statements is selected. The break statement announces the
discontinuity that occurs when zero_current changes its value.
40 CHAPTER 2

library disciplines;
use disciplines.electrical_system.all;
entity scr is
generic ( vdrop: Voltage := 0.7; On voltage drop
von: Voltage := 0.7; Turn on voltage
ihold: Current := 0.0; Holding current
ron: Real := 0.le-9); On resistance
port (terminal anode, cathode, gate: Electrical);
end entity scr;

architecture ideal of scr is

quantity vscr across iscr through anode to cathode;
quantity vcontrol across gate to cathode;
signal off, zero_current: Boolean := true;
begin
assert ron /= 0.0;
off <= true when not (vcontrol 'Above (von) or iscr'Above(ihold))
else false when vcontrol'Above(von) and vscr'Above(O.O);
zero_current <= off or not vscr'Above(vdrop);
if zero_current use
iscr 0.0;
else
iscr (vscr - vdrop) / ron;
end use;
break on zero_current;
end architecture ideal;

Figure 12: A Simple Silicon Controlled Rectifier

2.5. CONCLUDING REMARKS

We have given an overview of the VHDL 1076.1 language scheduled to become an IEEE
standard in 1997. We have also shown the use of the language in a number of examples
from a variety of application areas. We believe that the language is flexible enough to
address many if not all of the requirements imposed by continuous and mixed
continuous/discrete simulation problems that are within its scope.

Acknowledgements
The authors would like to thank their colleagues from the 1076.1 Language Design
Committee for their contributions to the design of the extended language.
VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL 41

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[3] "IEEE Standard VHDL Language Reference Manual", ANSI/IEEE
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[4] K.E. Brenan, S.L.Campbell, and L.R.Petzold, "Numerical Solution of Initial-
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