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How Do CNTFETs Work, and Why Are They So Promising PDF
How Do CNTFETs Work, and Why Are They So Promising PDF
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The structure of a carbon nanotube field-effect transistor (CNTFET). (Source: Arvind R. Singh, Shandong University; Reference [1].)
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New technologies require faster processors, smaller integrated circuits, and less power consumption. Technology
advancements such as 5G networks increase the pressure to improve smartphone battery life, spectral e ciency,
and more. One potential solution is the use of carbon nanotube eld-e ect transistors (CNTFETs).
A CNTFET is a nano-scaled device that can provide low-power integrated circuits with high performance and high
power density. Instead of the bulk silicon material used in traditional metal-oxide semiconductor eld-e ect
transistors (MOSFETs), CNTFETs use carbon nanotubes (CNTs) in between the source and the drain of a MOSFET
structure. This enables higher current carrier mobility, enabling CNTFETs to provide a superior drive current density.
The rst simple CNTFET, reported in 1998, was manufactured by depositing single-wall CNTs from solution onto
oxidized silicon wafers. The CNTs were synthesized by laser ablation and Si wafers were prepatterned with gold or
platinum electrodes. Over time, the process has improved. Previously, CNTs were laid down on the weak contacts of
source and drain electrodes. Now, the improved process patterns the electrodes on top of previously laid CNTs.
The contact between metal and nanotubes can be improved by using gold, titanium and carbon with a thermal
annealing step. The thermal processing leads to the formation of titanium carbide (TiC) at the metal/nanotube
interface, signi cantly reducing the contact resistance from several megaohms to approximately 30kΩ.
via charge transfer. The Fermi level is also near the valence band, which makes injection of holes easier. Oxygen
desorption at high temperature adapts the Fermi level near the conduction band, allowing the injection of electrons.
By using thermal annealing, there is no threshold voltage shift when making n-type from p-type (which is not the case
during a bulk doping process).
A back gated n-type nanotube transistor can be achieved by doping the CNT with potassium vapor (see below). The
process can shift the Fermi level of the tube from the valence band edge to the conduction band edge by transferring
the electrons from adsorbed potassium atoms to the nanotube, thus reverting the doping from p- to n-type. An
intermediate state where both electrons and holes are allowed can also be achieved, resulting in ambipolar
conduction and the creation of ambipolar CNTFETs.
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The capability to make n-type CNTFETs is important because it enables the manufacturing of CNT-based
complementary logic circuits.
Low pulverization probability because the carbon nanotubes are one dimensional. This feature allows a device to
operate in the ballistic regime.
The CNT conducts on its surface where all the chemical bonds are saturated and stable. There is therefore no
need for careful passivation of the interface between the nanotube channel and the gate dielectric.
The metal-nanotube contact Schottky barrier represents the active switching element.
Types of CNTFETs
CNTFETs can be classi ed according to di erent criteria. When classi ed by current injection methods, there are two
CNTFET types: Schottky barrier CNTFETs (SB-CNTFETs) that use metallic electrodes to form Schottky contacts, and
CNTFETs with doped CNT electrodes that form Ohmic contacts (similar to the MOSFET design). The contact type
determines the current transport mechanism and CNTFET output characteristics. In SB-CNTFETs, the current means
tunneling of electrons and holes from the potential barriers at the source and drain junctions. The barrier width is
controlled by the gate voltage, which thus controls the current.
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The Ohmic contact CNTFET type uses the n-doped CNT as the contact. The doped source and drain regions behave
just like MOSFETs. The potential barrier is formed at the middle of the channel, and the current is controlled via
modulation of the barrier height (controlling the gate voltage).
CNTFET Design
CNTFETs can be fabricated as a single-wall CNT (SWCNT) channel between two electrodes, a multi-wall CNT (MWCNT),
or a coaxial CNTFET. MWCNT CNTFETs have a complex structure, which limits their potential. The shells can interact
with each other. In addition, only the outer shell e ectively contributes to electrical transport. In coaxial geometry,
the gate contact wraps all around the channel (CNT), thus providing better electrostatics and very good control of
carrier transport. Metal-CNT contact type plays a crucial role in the transistor output characteristics.
There are four typical CNTFET designs: back gate CNTFETs, top gate CNTFETs, wrap-around gate CNTFETs, and
suspended CNTFETs.
Back gate CNTFETs are the earliest design that uses prepatterning parallel metal strips across a silicon dioxide
substrate and SWCNT arranged on top. CNTs together with metal strips (one metal strip source contact and one
drain contact) create a rudimentary eld-e ect transistor. The silicon oxide substrate presents the gate and includes
a metal contact on the back. The metal electrodes are made of metals compatible with silicon, such as titanium (Ti) or
cobalt (Co). Since the side-bonding con guration has the weak van der Waals coupling of the devices to the noble
metal electrodes, this CNTFET type has high contact resistance (≥1 MΩ).
Side view of a CNT arranged on a silicon oxide substrate prepatterned with source and drain contacts.
Top gate CNTFET design requires a more advanced fabrication process compared to the back gate design. SWCNTs
are arranged onto a silicon oxide substrate. Each CNT is located and isolated by using an atomic force or scanning
electron microscope. Then, high-resolution electron-beam lithography is used to pattern source and drain contacts.
The lower contact resistance is achieved via a high temperature anneal step in which adhesion between the contacts
and the CNT is improved. After this step, a thin top gate dielectric is deposited on top of the nanotube using
evaporation or atomic layer deposition. The nal step is placing the top gate contact on the gate dielectric.
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The main di erence between the top and back gate designs is the fabrication process. In the case of the top gate
design, the CNTFET arrays on the same wafer because the gate contacts are electrically isolated from each other. A
higher electrical eld with a lower gate voltage can be achieved in the top gate design due to the thin gate dielectric.
Because of those features, top gate CNTFETs are preferred over the back gate design, despite their complex
fabrication process.
Wrap-around gate CNTFETs (or gate-all-around CNTFETs) have an improved design over the top gate device. In this
design, the entire nanotube volume is gated, while with the top gate design only the CNT closer to the metal gate
contact is gated. This innovation improves the CNTFET electrical performance and reduces the leakage current.
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Suspended CNTFET design avoids placing the CNT over a trench, reducing contact with the substrate oxide and thus
improving device performance. Fabrication methods to suspend the CNT over trenches use catalyst particles that are
transferred onto a substrate.
The drawback of this design is its limited options for gate dielectric (air or vacuum). Moreover, only short CNTs can be
used as nanotubes because the longer ones will stretch in the middle and could potentially touch the metal contact
(creating a short-circuit). While this type of design is not suitable for commercial use, it is convenient for researching
CNTFETs are still a new technology—one with a lot of potential for improvement. Currently, the most popular designs
are back gate and top gate CNTFETs. Some semiconductor companies (such as In neon Technology) have introduced
I-V characteristics
The current-voltage (I-V) characteristic curves represent a transistor’s operating characteristics—the relationship
between the current owing through the device and the applied voltage across its terminals. The gure that follows
illustrates the drain I-V characteristics of CNTFETs. The saturation current at gate-source voltage VGS = 0.5V is
approximately 6μA [2]. Saturation drain current from drain I-V characteristics depends on the temperature. Drain
saturation currents slightly decrease when the CNTFET is cooled down. The curve is also determined by the CNTFET
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Drain current-voltage characteristics of planar CNTFET. (Source: Ram Babu; Reference [2].)
When the gate and the source voltages of SB-CNTFETs increase, the Fermi level of the CNT becomes closer to the
conduction band. The band lowering e ect develops barriers at CNT-metal junction. The electrons with high potential
will cross the barrier and ow into the tube. The current through the nanotube is limited by the thermionic current
component.
When the gate voltage VGS=0V, the current increases linearly with the drain voltage VDS (the thermionic current is
linearly dependent on the drain voltage). Applying positive gate voltage induces a heavy charge on the channel,
signi cantly increasing the tunneling through the barrier compared to the thermionic current component. The
current increases almost quadratically, is highly sensitive to the drain voltage, and is controlled by manipulating the
Conclusions
CNTFETs are up-and-coming devices that provide dense, high performance, and low power circuits. CNTFET is a
rapidly developing technology due to its outstanding electrical characteristics. The large Ion: Io , high current drive,
and carbon nanotube’s other properties increase the possible applications of CNTFETs in the semiconductor
industry. They are the most promising alternative for conventional transistors. It is expected that with the same
power consumption, they will be three times faster than silicon-based transistors.
In comparison to traditional silicon technology creating structures with minimum diameters reaching 90nm, SWCNTs
have diameters between 0.4 and 5nm. Semiconducting SWCNTs have extremely high charge-carrier mobility—higher
than silicon by a factor of 200. CNTs can withstand extremely high current densities of up to 1010A/cm2 (compared to
Semiconducting carbon nanotubes (CNTs) are an ideal substitute for silicon due to their exceptional carrier mobility,
signi cant mean free path, and improved electrostatics at nanoscales. As the one-dimensional transport properties
increase the gate control, simultaneously ful lling gate leakage constraints, they also allow for a more
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comprehensive gate insulator choice. Thus, CNTs can overcome the short channel e ects, and the valence bands and
symmetry of the conduction give these devices the upper hand for additional applications. When applied in CNTEFs,
In theory, CNTFETs have the potential to reach the terahertz regime when compared to standard semiconductor
technologies. Nevertheless, this eld is still at an early stage, and for the time being, researchers should remain
[1] Design and Analysis of CNTFET-Based SRAM. Arvind R. Singh. Shandong University.
[2] Carbon nanotubes field-effect transistors: A review. International Journal of Electronics and Communications, Busi, Ram
Babu. (2010).
[3] https://www.infineon.com/cms/en/about-infineon/press/market-news/2004/128087.html
[4] Vertical scaling of carbon Nanotube Field-effect transistors using top gate electrodes. Applied Physics Letters. May
2002. S. J. Wind et al.
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