This full-text paper was peer-reviewed and accepted to be presented at the IEEE WiSPNET 2017 conference.

Simulation Analysis and Performance Evaluation of

Four Innovative Routers for Network on Chip
Himani Mittal1 and Yogendera Kumar
School of Electrical, Electronics and Communication Engineering, Galgotias University,
Plot no. 2, Sector 17-A, Yamuna Expressway, Greater Noida, 201 301 (UP) India
Email: 1 himanimit@yahoo.co.in

Abstract—Network on Chip (NOC) a new design emerging
offers a promising architectural choice for future systems on
chips. NOC architectures offer a packet switched communication
among functional cores on the chip. NOC architectures also apply
concepts from computer. In our work we analysed the series of
simulation results of four innovative routers. All the results are
useful for design of an appropriate switch for the NOC. This
work reports experimental results based on the simulation of
four innovative routers using verilog in modelsim enviornment.
Performance analysis is also done by comparing their simulation
results. Performance analysis is usually done by simulation at the
Transaction Level – TL or at the Register Transfer Level – RTL.
TL provides smaller simulation time, while RTL provides more
accuracy in results, which is very necessary during the design
phase of a NoC. However, the performance characterization of
a large NoCs by means of RTL simulation is time costly and
requires several hours of computing. The performance evaluation
of a NoC can be also speeded up by doing it directly on hardware
as FPGA instead of using simulation models.
Index Terms—Network on Chip (NoC); Heterogeneous
Reconfigurable Router; First in First out (FIFO) Buffer;
Crossbar Switch; Channel/Control Logic; Performance Analysis,
Low Power, Low Area, Throughput, Latency, Critical time path.
I. I NTRODUCTION
Network on Chip or Network on a Chip (NoC or NOC) is a
communication subsystem on V.L.S.I chip. System-On-Chips
(SoCs) have evolved in term of performances, reliability and
integration capacity. The last advantage has induced the growth
of the number of cores or Intellectual Properties (IPs) in a
same chip. Unfortunately, this important number of IPs has
caused a new issue which is the intra-communication between
the elements of a same chip. To resolve this problem, a new
paradigm was introduced i.e. Network-On-Chip (NoC). Since
the introduction of the NoC paradigm in the last decade,
new methodologies and approaches have been presented by
research community and many of them have been adopted by
industrials. The objective of the works done was to establish
a reliable survey about available designs, simulation or imple-
mentation. An important amount of information was hence
collected which characteristics NoCs dedicated architecture
that will be presented throughout this literature survey. This
survey is built around a respectable amount of references and
it is hoped that it will help realise the model that is to be
designed here.
It is seen that that NOC architecture facilitates reuse at
various levels of system design, thus reducing the time to
design and test. However, NOC research is hot in today’s time.
A higher-level modeling will give us the insight of knowing
more about its architecture. Like in any other network, router
is the most important component for the design of communi-
cation back-bone of a NoC (Network on Chip) system. In a
packet switched network, the functionality of the router is to
forward an incoming packet to the destination resource if it is
directly connected to it, or to forward the packet to another
router connected to it.
In this work we have done simulation analysis and perfor-
mance evaluation of newly designed heterogeneous routers.
The router is the main component that determines the latency,
throughput, reliability and efficiency of the entire network on
chip design.
We would use the tool, Model Sim which has been ex-
tensively used in the research for design and evaluation of
public domain computer network, to evaluate various design
options for NOC architecture, including the design of router,
communication protocol, routing algorithms. In the following,
we give a brief overview of our NOC Routers architecture.
In Section I, we describe how various aspects of our NOC
architecture. Section II presents the literatutre survey. Sec-
tion III gives brief explanation of Router Design I, II, III, IV.
Section IV gives a description for our simulation experiment,
and in Section V some experimental results and corresponding
analyses are presented. Section VI gives comparision results
Finally, we draw some conclusions in Section VII.
II. L ITERATURE R EVIEW
Network-On-Chips (NoCs) have been evolved considerably
in term of performances, reliability and integration capacity. It
is suitable for Dynamically Reconfigurable Multiprocessor on
Chip systems as presented in [4]. The NoC is based on routers
performing online error detection of routing algorithm and
data packet errors. It focuses on adaptive routing algorithms
which allows to bypass faulty components or processor ele-
ments dynamically implemented inside the network. Another
router architecture [7] is based on additional diagonal state
indications and specific logic blocks allowing the reliable
operation of the NoC. In this paper [9], comparision of some
of the topologies such as Mesh, Torus, Binary Tree and
Butterfly Fat Tree (BFT) have been simulated using a Network

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Simulator (NS2) and their performances have been assessed

and compared taking throughput, maximum end-to-end latency
and dropping probability as assessment parameters.
[8] presents the the impact of various error-control schemes
on high reliability against noise, high performance, and low
energy consumption which are key objectives in the design of
on-chip networks and on the tradeoff between them.
It also demonstrates the [3] implementation of a dynami-
cally reconfigurable network on chip router with bus based in-
terface and describes heterogeneous integration of components
in NoCs architecture and includes modeling of reconfigurable
components. It discusses [7] about broad perspective of the
new methods to improve [4], [5] performance and Integra-
tion issues associated with mixed-signal NOC design. [6]
design channel buffers and router crossbars to improve the
performance (latency, throughput) while reducing the power
consumption. In addition, we implement the proposed channel
buffers and crossbar organizations in a concentrated torus
(CTorus) topology which is a dual network without the ad-
ditional area overhead.
The router structure shown here do not support heteroge-
neous data because once a channel starts accepting packets Fig. 1. Router Design I.
from its neighbor (left or right) it will not take any packet
input directly to that channel. So, it will support heterogeneous
data. So in our proposed work we ll do addition of two tag
bits to the packets or flits before storing them in the FIFO to
support heterogeneous data thereby reducing power as well as
area also.

III. ROUTERS D ESIGN I, II, III, IV

In the proposed heterogeneous reconfigurable router [2],

the major change in the architecture of router is channel
architecture. The channel of the router is designed in such
a way that it can store heterogeneous data in comparision of
layered data in original router by adding tag bits. Here the NoC
efficiency can be increased as a function of the possibility to
reconfigure the buffer size according to the requirements of
each channel of the router [3] at run time, without the need
to Oversize buffers to guarantee performance.
Router architecture I Fig. 1 discusses reconfigurable router, Fig. 2. Router Design II.
where the NoC efficiency can be increased as a function of
Router architecture IV Fig. 4 which is the smart reliable
the possibility to reconfigure the buffer size according to the
router based on a a new reliable NoC-based communication
requirements of each channel of the router at run time, without
approach called RKT-NoC, along with its simulation results.
the need to oversize buffers to guarantee performance.
Router architecture II Fig. 2 which is a reconfigurable router IV. S IMULATION R ESULTS
for NoCs applications. In proposed router even if a channel is Simulation refers to the verification of a design, its func-
taking data from its neighbouring channel it will continue to tion and performance. It is process of applying stimuli to
take the packet input at its own channel. a model over time and producing corresponding responses
Router architecture III Fig. 3 have four more directions (NE, from a model. Figures below show the simulation result of
NW, SE, SW) are added. It will now support Eight Directions. reconfiguration-al router. This simulation is performed on
It uses Buffer less storage concept to store the data of four Model Sim PE Student Edition 10.4a.
newly added directions. Data of newly added directions share Fig. 5 shows the simulation waveform of South module.
fifo from their neighbor to store its data. Thus, the architecture In Fig. 6 red circle shows how data is flowing in a
requires less area. heterogeneous data flow.

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Fig. 6. Simulation of Router Design II South channel.

Fig. 3. Router Design III.

Fig. 7. Simulation of Router Design II South F. I. F. O.

Fig. 4. Router Design IV.

Fig. 8. Simulation of Router Design III. South channel.

Fig. 7 shows that South data can be read twice supporting

heterogeneous property of our innovative reconfigurable router
(see Fig. 8).
Fig. 9 shows the simulations of proposed router, it is seen
that all then, N, S, W, E modules send a data packet simulta-
neously and similarly receive the data packets simultaneously.
It is also observed that all the data packets do not make any
Fig. 5. Simulation of Router Design I. South channel.
loopback and bypass as there is no fault present.

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Fig. 9. Simulation of Router Design IV. South channel.

Fig. 11. Design summary of Router Design I.

Fig. 10. Total power dissipation in Router Design I.

Fig. 12. Total power dissipation in Router Design II.

Here it is showimg that the data is input in four directions
and after routing data is out from four directions N, S, E, W
according to XY algorithm.

V. P OWER AND A REA A NALYSIS

Xilinx Power Analyzer (XPA) is a design tool used to
analyze real design data. It is used to calculate power after
design implemented in Xilinx ISE software. It uses the NCD
file output from Place & Route (PAR) step.
Area analysis is also done by Xilinx tool Modelsim. It is
done by synthesising routers and then seeing its synthesis
report (see Figs. 10–18).

VI. C OMPARISION OF F OUR ROUTERS

See Figs. 19–22.
VII. C ONCLUSION
In this work, the advantage of the use of an NoC with
heterogeneous reconfigurable routers instead of homogeneous
ones has been documented and simulated. Using reconfigu-
ration, one can dynamically change the buffer depth to each
channel, in accordance to the necessity of the application at
same performance level. It was tested via simulation & verified
Fig. 13. Design summary of Router Design II.
that to reach the same performance obtained with the recon-
figurable router, the original architecture, i.e. homogeneous
router needs many more buffers.
The new routers, while reaching the same performance than
the original architecture, can obtain a reduction of power

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Fig. 17. Design summary of Router Design IV.

Fig. 14. Total power dissipation in Router Design III.
Parameter Buffer No. Powe Dela Frequenc
s depth of r y y
Sli (W) (ns) (MHz)
ces
Router Varying 28 0.015 10.0 100
Design I.
Router Varying 82 0.02 8.3 120
Design II.
Router Semi 54 0.045 7.1 140
Design Buffer 9
III. less
Router 4 bits 33 0.019 7.03 142
Design 3
IV.

Fig. 18. Performance comparision of four routers.

Fig. 15. Design summary of Router Design III.

Fig. 16. Total power dissipation in Router Design IV.

Fig. 19. Comparision of power dissipation.

consumption though it can be tested via power measuring
software tool that has been prevailed for concept of future
work. Moreover, the reconfigurable router obtains the same
performance of the homogeneous router with a buffer depth
64% smaller.
Moreover, with the new architecture it is possible to recon-
figure the router in accordance with the application, obtaining
similar performances even when the application radically
changes.

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Fig. 20. Comparision of frequency.
Fig. 21. Comparision of delay.
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