VLSI Implementation of Online Digital Watermarking Technique with
Difference Encoding for 8-Bit Gray Scale Images
Annajirao Garimella, M V V Satyanarayana†, R Satish Kumar, P S Murugesh† and U C Niranjan
Manipal Academy of Higher Education, Manipal, India 576119
†
Tata Elxsi, Design & Development Centre, Hoody, Bangalore, India 560048
garimella@ieee.org, rompi_satish@yahoo.com, ucniranjan@yahoo.com,
{satyamv, murugesh}@india.ti.com
Abstract
Digital watermarking is a technique of embedding
imperceptible information into the digital documents. In
this paper, VLSI implementation of Digital Watermarking
technique is presented for 8 bit gray scale images. This
implementation of fragile invisible watermarking is
carried out in spatial domain. The standard ASIC design
flow for 0.13µ CMOS technology has been used to
implement the algorithm. The area of the chip is 3,453 x
3,453 µm2 and the power consumption is 37.6µW.
Index terms: Watermarking, Image Processing, VLSI, ASIC
design
1. Introduction
Watermarking techniques for paper
manufacturing have been in use since late middle ages.
Digitization of our world has expanded this concept of
watermarking to the digital documents viz. text, graphics
and multimedia. A digital watermark is essentially an
imperceptible digital signal or pattern embedded into
multimedia content for authentication and protecting
ownership rights.
Watermarking technique can be implemented in both
spatial domain and frequency domain. In spatial domain,
the lower order bits of the image pixels are replaced with
that of the watermark or adding some fixed intensity value
to an image. In frequency domain, Watermarking can also
be applied in the transform domain, including such
transforms are Fast Fourier, discrete cosine, and wavelet.
In the case of frequency domain, the lower frequency
components can be altered from the original [1], [2].
______________________
†
The authors were presently with Texas Instruments India, on long
term project, where the computational work of this paper has been
carried out.
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The VLSI Implementation of the Watermarking
technique demands the flexibility of implementation both
in the computation and design complexity. This mainly
limits the choice of the watermarking technique.
Spatial domain watermarking offers less computational
overhead compared to that of frequency domain. The
alteration of LSB bit plane of host image with the
watermark (copyright) provides a simple and faster
technique and seems to hold up well under lossy image
compression and selected filtering techniques [2]- [4].
Digital Watermarking has many applications ranging
from document authentication to medical imaging [4] to
satellite image and VLSI Intellectual Property Protection
[5].
1.1. Contributions of our work
To our knowledge, this work gives the first VLSI
Implementation of Digital Watermarking technique. The
above listed reasons are the criteria of selection of spatial
domain watermarking technique. Alteration of LSB bit
plane with the copyright is used as the watermarking
technique for the VLSI implementation for 8 bit gray scale
images.
Section II describes the watermarking algorithm along
with the encryption process of the copyright. Section III
details the extraction of the watermark and image
authentication. Section IV details the 0.13µ CMOS ASIC
design implementation, which features the design flow
from Verilog HDL coding to GDSII and the issues faced
during implementation. Simulation results and conclusion
are presented in Sections V and VI respectively.
2. Incorporating the watermark
Fig. 2 indicates the complete block diagram for the
ASIC implementation of watermarking scheme for 8-bit
grayscale images. Here the spatial domain is considered
for the invisible watermark implementation.
 The copyright file is a text document, and is converted
to ASCII code. This document is encrypted with
Differential Pulse Code Modulation (DPCM) technique.
The encrypted ASCII code is swapped with the least
significant bit (LSB) of the gray scale. Eight bits of each
ASCII code thus replace LSBs of eight consecutive pixels
of the image from left to right. The signal (copyright) is
encrypted before watermarking to enhance security [6].
2.1. Encryption of the watermark
The Differential Pulse Code Modulation (DPCM)
technique can be used to reduce the dynamic range of the
signal to be interleaved or stored. In this technique, the
differential error (which is random or uncorrelated) is
encrypted and interleaved along the first sample. While
extracting the watermark, the original signal can be
reconstructed from the error signal, and the first sample.
The DPCM is a predictive coding technique wherein the
sample xn is expressed as the linear combination of
previous sample xn-1 and error signal en [4].
x n = ρ ⋅ x n −1 + en
where ρ is the predictor coefficient. Considering the
predictor coefficient, ρ as unity,
x0' = x1 − x0
and
x1' = x 2 − x1
...
x n −1 ' or en = xn − xn −1
Thus the encrypting technique used here is difference
encoding.
3. Extracting the watermark
By accumulating the consecutive LSBs of the pixels,
and decrypting, the watermark can be reconstructed. This
watermark is compared with the original watermark signal
for authentication. Thus, the authentication of the
document is established. The watermark, embedded into
the image, can be destroyed by changing all the LSBs of
the pixel values to either ‘0’ or ‘1’.
4. VLSI implementation
The size of the host image considered for the VLSI
ASIC implementation is 200x200 pixel intensity for 8-bit
gray scale images. The watermark is bit stream of the
ASCII coded text file. The size of the watermark is 2048
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bits. Each copyright byte that comes in is subtracted from
the previous byte and the difference value (binary) is used
for watermarking. After the least significant bit of the
image pixel is swapped with the copyright bit, the 8-bit
output watermarked pixel is available as output. The
operation is continued until the 2048 bits of the copyright
signal is watermarked.
Two Single Port CMOS clocked RAMs are used, the
size of the RAM1 being 40,000 bytes and RAM2 being
2,048 bytes. RAM1 is used to load the image data and
RAM2 holds the watermarked output values. Watermark
is a permanent signature and is stored in the 2048 bits
register internally. RAM is not used to store the
watermark as it is volatile and the data stored will be lost
once the power is off. The frequency of the clock is 100
MHz.
The functional description of the pins is given in Table
1. The operation of the chip is as follows. First,
RESET_INTZ signal initializes the RAMs internally.
Then RAM1 is loaded with the image data. START is
provided as the handshake signal for the internal
operations to start. Then BUSY signal goes high and the
(1) active external interface is cutoff except RESETZ,
RESETZ being the master signal for the chip. Then the
watermark is embedded into the image. Once all the
internal computations are completed, READY signal is
asserted. Internally pipeline logic is used for the faster
operation. Same external control signals have been used
for both the RAMs to minimize the external pins. After
the watermarking of the image, first 2048 pixels are
obtained from RAM1 and RAM2. Remaining pixels are
obtained from RAM1 only.
The RTL for the complete design is developed using
(2)
Verilog HDL. The test bench is written in VHDL.
Constraints of the design: 1) Output slew limit on primary
outputs is 20 ps. 2) Input capacitance limit on primary
inputs is 30 pF. On Chip Variation (OCV) margin is 75
††
ps . The code is synthesized using Synopsys Design
Compiler and the simulation of the netlist was carried out
using ModelSim. RTL is simulated and is verified against
gate level simulation (both unit delay modeling and cell
delay modeling). Total time for the entire simulation for
one image is 1.494 ms using ModelSim Verilog. Static
timing analysis was carried out using PrimeTime. The
floorplanning was carried out using Avant! Tools
(Milkyway and Jupiter). After the floorplanning, the .def
is given as input to the Magma's BlastFusion 3.1 for Place
and Route to get the final GDSII. The Signal Integrity
check was carried out using Cadence Celtic. The timing
step will dump out the .sdc files for each corner (PTV),
which can be used for back annotation.
††
OCV margin is the worst-case margin needed to account for On Chip
Variation, which would be generally 20% of the largest insertion delay
in the design.
 CLK RESET_INTZ

RESETZ
BUSY
EZ

WZ READY

START

DATA1_OUT [7:0]
ADDRESS_IN [15:0]

DATA_IN [7:0] DATA2_OUT [7:0]

Figure 1. Pin diagram

RESET INITZ

CLK CLK
RAM1 INITIALIZATION

RESETZ • WZ
40K
ADDRESS_GEN
EZ

RAM1

40K X 8
RAM1 ADDR GEN RAM1 DATA INIT
ADDRESS IN RAM1 ADDR
16
RAM1 DATA

DATA IN 8
SYNC OF
RAM SIGNALS
•
RAM1 WZ
&
WZ
• RAM1 CTRL GEN RAM1_EZ
ADDR
EZ
• CLK ENCODING
8 DATA1 OUT
2048 BIT REG
START DATA
8 BIT REG SELECTION LOGIC
RAM2 EZ 8
DATA2 OUT
SYNC OF RAM2 WZ
RAM SIGNALS
ADDR [10 : 0]
& DATA
CONTROL SIGNAL A[15 : 11]
RAM2 CTRL GEN DATA
GENERATION FOR RAM2
ADDR
RAM1 & RAM2 WZ
EZ 2K X 8
CLK
BUSY
CLK RESET INITZ
RESETZ
READY

Figure 2. Functional Block Diagram

Table 1. Pin details of the chip valid Reset.

Indicates status of Internal logic, Active
PIN FUNCTIONAL DESCRIPTION low. Once the External Reset is sampled,
CLK Clock signal. RESET_INITZ this signal will remain active till all the
External Reset, Active low. Hold it low for RAM locations are initialized with the
RESETZ predefined value ie., 0x00. When this signal
at least two CLK cycles to get sampled as

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 is low, the RAM's are isolated and the value by performing Write operation, this signal
on the DATA1_OUT and DATA2_OUT is to be activated. Once this signal is
should be ignored. activated, the Encoding operation will start.
RAM ENABLE signal, Active low. Active high signal, indicates the Encoding
Read/Write operation will be performed operation is in progress. When this signal is
EZ
only when EZ is active at the rising edge of BUSY active, external access to RAM's are
the CLK. isolated. The data on the DATA1_OUT
Read/Write signal, low being Write and and DATA2_OUT is not valid.
high being Read. Sampled at the rising Active high signal, will be activated for 1
edge of the CLK. If low, the Data on the CLK cycle after the completion of
READY
bus DATA_IN is written to RAM location Encoding operation. Indicates that RAM2
WZ
addressed by ADDRESS_IN bits. If high, contains valid Encoded pixel values.
the value at the location ADDRESS_IN of RAM1 DATA output bus. Original pixel
RAM1 will be displayed on DATA1_OUT value which was stored by the user will be
DATA1_OUT
and RAM2 displayed on DATA2_OUT. output on this bus when a read operation is
[7:0]
Input Address bus, used for Write/Read performed. If the user had not written pixel
operation to/from RAM1 and RAM2. values, then 0x00 will be displayed.
ADDRESS_IN
Internally lower 11 bits are connected to RAM2 DATA output bus. Valid encoded
[15:0]
RAM2 and all the 16 bits are connected to pixel value is output on this bus when a
RAM1. read operation is performed after READY
DATA2_OUT
DATA_IN Data Bus, used to perform write operation signal gets activated and the address less
[7:0]
[7:0] to RAM1 than 2048. If the address is greater than or
Handshake signal, Active high. When the equal to 2048, then data from RAM1
START
loading of image pixel values is completed location is output on this bus.

Design
Block Level Design Requirements and
Specifications
Pseudo Code

T RTL Coding
i
m Synthesis
i
n
g Prelayout Simulation

C Floor Planning
o
n
Timing Driven Placement and optimization
s
t
r Clock Tree Synthesis
a
i
Route Initial and Final
n
t
s Extraction

Hand Off
Export

Figure 3. Typical DSM ASIC design flow

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 The number of nets after synthesis is 9,697 and after
detailed route is 10,809. Critical timing path length is 5.89
ns. The supply voltage to the chip is 1.2V. The total
numbers of pins were 100 and were distributed as follows.
Table 2. Pin distribution
Signal pins
VDD pins
VSS pins
Secondary power pins
(VDDSHV)
VPP pins
Total number of pins 100
Issues faced during implementation: 1) Total 41
antenna violations were observed during route initial stage
of Magma flow. 2) Cell power row straps did not
terminate properly, either the row strap did not terminate
into a power ring or the row strap was left open. 3)
Executed the command at the mantle prompt run
route refine $m –type all to remove opens
and via-via violations. 4) Manually adjusted the pre-route
spacing violations in Magma’s Volcano database.
Figure 4. Complete layout of the watermarking
chip
The ASIC is implemented 0.13µ CMOS 6-metal
(topmost routing layer is metal-6 and bottommost is
metal-1) technology. The 100 pin TQFP package is
selected for the design. The area of the chip is 3,453 x
3,453 µm2 and the power consumption is 37.6µW.
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5. Results
Figures 5 and 6 show the original host “Lena” and
“Peppers”, size of each being 200x200. 2,048 pixels of
the image were used for watermarking. The resulting
images after being watermarked are shown in Fig. 7 and
48 Fig. 8.
26 The performance of watermarking was evaluated by
the criterion, the normalized root mean square error
20
(NRMSE) as defined below [4].
4
¦¦ [ f 0 (i, j ) − f w (i, j )]2
i j
2 NRMSE (%) = × 100 (3)
¦¦ [ f 0 (i, j )]2
i j
From the definition of the NRMSE, it is seen that, the
maxima occurs for the condition when the LSB of all the
pixel values are altered. Here the total no. of pixels
watermarked is 2048. Thus, the equation for the maximum
NRMSE is given as below,
2048
MNRMSE (%) = × 100 (4)
¦¦ [ f 0 (i, j )]
2
i j
The Signal to Noise Ratio (SNR) measures are
estimates of the quality of a reconstructed image
compared with an original image. The Root Mean Square
error is computed as below,
¦¦ [ f 0 (i, j ) − f w (i, j )]2
i j
RMSE = (5)
N
The PSNR in decibels (dB) is computed by using
§ 255 ·
PSNR = 20 log10 ¨ ¸ (6)
© RMSE ¹
There are other definitions for PSNR. Here we are
interested in the relative comparison, not in the absolute
values. The statistical parameters, NRMSE and PSNR are
presented in the Table 3. The sum of squares of the
difference of original and watermarked images is 1026
and 1043 for Lena and Peppers respectively.
6. Conclusion and future strategies
To our knowledge, this work gives the first VLSI
Implementation of Digital Watermarking technique.
Fragile watermarking is implemented in spatial domain.
The watermark is destroyed when the image is
manipulated digitally. Such a watermark is useful in
proving the authenticity of image. If the watermark is still
intact, then the image has not been “doctored”. If the
watermark is being destroyed, then the image has been
tampered with.
This chip can be used as an interface with Digital Still
Cameras for online watermarking.
 Fig. 5 Original Lena (200x200) Fig. 6 Watermarked Lena (200x200)

Fig. 7 Original Peppers (200x200) Fig. 8 Watermarked Peppers (200x200)

Table 3. Statistical analysis

Lena Lena Peppers Peppers
(O) (W) (O) (W)
7. Acknowledgement
Mean 123.6061 122.2413 119.954 118.5065
The authors sincerely thank Texas Instruments, India
Median 128 127 120 119 for providing the computational facilities.
Mode 154 50 96 96
Standard 8. References
47.0388 49.3108 52.9252 53.3547
Deviation
[1] Hal Berghel, “Watermarking Cyberspace,” Communications
Correlation 1 1 of ACM, vol 40, no. 11, Nov. 1997.
NRMSE [2] Hal Berghel, Lawrence O’ Gorman, “Protecting Ownership
16.0156 16.1477 Rights Through Watermarking,” IEEE Computer, July 1996.
(%)
MNRMSE [3] R. G. van Schyndel, A. Z. Tirkel, C. F. Osborne “A Digital
22.6274 22.6274 Watermark,” in Proc. IEEE International Conference on Image
(%)
Processing ICIP-94, 1994, vol 2, pp. 86-90.
MSE 0.02565 0.02607 [4] D. Anand and U. C. Niranjan, “Watermarking Medical
PSNR (dB) 64.0399 63.9685 Images with Patient Information,” in Proc. IEEE/EMBS
Conference, Hong Kong, China, Oct. 1998, pp. 703-706.
O – Original Image W-Watermarked Image [5] A. B. Kahng et al., “Robust IP Watermarking Methodologies
for Physical Design,” Design Automation Conference, pp. 782-
Future strategies include extending these ideas to other 787, 1998.
multimedia documents and alternate watermarking [6] Simon Haykins, “Communication Systems,” Wiley Eastern.
schemes, and for different applications like on-chip
medical image processing and satellite image processing.

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