Session 11A1
A VHDL Based Design Environment
IEEE
Abstract - I n t h i s p a p e r we describe a design
environment t o model and simulate digital c i r c u i t s
described in VHDL. VHDL, VHSIC Hardware Description
Language, i s a state-of-the a r t hardware description
language (HDL) commonly used f o r digital c i r c u i t
description. VHDL f e a t u r e s three levels of abstraction
io describe digital systems, namely, algorithmic o r
behavioral, data f l o w o r RTL (Register Transfer Level),
and structural o r network description. The simulator
presented in t h i s p a p e r can accept behavioral and data
f l o w s t y l e descriptions. The simulator consists of two
primary sections: a front-end of t h e simulator called
aAnalyzer and a back-end called simulation sxecutive.
The analyzer checks f o r the s t a t i c e r r o r s in the in t h e
VHDL input description. The s t a t i c e r r o r s being t h e
syntactical e r r o r s in the input VHDL. The analyzer
consists of: lexical analyzer, s y n t a x analyzer, and
semantic analyzer. The lexical analyzer eliminates a l l
the white s p a c e s from the input description; the s y n t a x
analyzer c h e c k s f o r VHDL syntax, and f i n a l l y the
semantic analyzer perf orms t y p e checking.
simulation executive i s directly implemented through
the semantic action p a r t s of the l e x i c a l analyzer. The
simulator's f ront-endsections, the scanner and t h e
parser, have been implemented using the automated
compiler construction tools LEX and YACC, developed a t
Bell labs. It is a good learning-aid t o understand the
s y n t a x of the VHDL. It r u n s on SEQUENT Balance 8000
running under DYNIX V.3.0.4.5 operating systems.
I . INTRODUCTION
It is a well established f a c t that the computer-aided
design (CAD) tools a r e essential f o r today's complex
VLSI circuits. VHSIC is one of the hardware
description language t h a t is recently developed t o
precisely describe the functional behavior of the
complex VLSI circuits with ease 11-31. Among the
essential tools t h a t a r e necessary t o develop VLSI
circuits around VHDL a r e the simulator and a silicon
compiler. The simulator is used t o verifies the
behavior of the circuits described through VHDL [41.
The silicon compiler then translates the VHDL
functional description into a manufacturable mask file
[51. This paper presents the description of the
simulator. Section 2 of this papers includes an
introduction to VHDL; section 3 provides the
description of the simulator; section 4 deals with the
implementation issues of the simulator; section 5 the
t e s t results; and finally the section 6 includes the
conclusions.
e Proceedings
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for VLSI Circuits
M.C. Vyas, G.N. Reddy
Electrical Engineering
Michigan Technological University
Houghton, Michigan
2. INTRODUCTION TO VHDL
VHDL has been under development for the past few years.
In 1983, the Department of Defense (DoD) initiated the
Very High Speed Integrated Circuits (VHSIC) Program.
I t requested a group of companies (Intermetrics, Inc.,
IBM Corp. and Texas Instruments) t o define a standard
hardware description language 161, suitable f o r the
description of VHSIC hardware. The meeting in August
1984, held in Orono, Maine, attended by representatives
of the DoD, academia, and industry resulted in the
publication entitled "VHDL Language Reference Manual,
version 7.0". A revised version of this called version
7.2 was published in August 1985 [7-111. The VHDL
analysis and standardization group met again in March
1987 and came up with the final version. It is called
the IEEE 1076 standard VHDL [12-131. A study of the
language and current trends in the choice of HDLs
indicates a high probability of i t s increased usage on
The account of its high versatility and flexibility
compared t o other HDLs. According t o Nash and Saunders
[141, "VHDL represents a significant advance in the
state-of-the-art hardware description language and can
be considered the "FORTRAN of the hardware description
languages", in the sense t h a t i t provides the f i r s t
generally accepted standard HDL". A survey of currently
available HDLs shows t h a t VHDL, a s the most powerful
language, is expected t o become the industry a s well
[l-3, 151.
2.1 VHDL Language F e a t u r e s
VHDL features three levels of abstraction t o describe
digital systems. They are, in decreasing order of
abstraction: algorithmic or procedural style, d a t a flow
or Register Transfer Level (RTL) style, and structural
or network description style. Structural descriptions
define "components" and then interconnect "instances"
of these components t o generate another component a t a
higher level of design description. Data flow
descriptions allow behavioral description of the
hardware, indicating the parallelism involved. The
algorithm description allows the modeling of a system
without any regard t o i t s structure. Information on
the present IEEE 1076 VHDL language can be found in
[ 12-13 I.
3. THE SIMULATOR
The complexity of a VLSI circuit makes it normally
impossible f o r
- 1989 Southeastcon
40 1
a designer t o guarantee error-free
 design with known performance under all operating
conditions. Simulation is an effective way of
evaluating a design and is used a t all levels of
design, before the expensive and time-consuming step of
manufacturing s t a r t s . The function of simulation is t o
assist in the verification of hardware designs by
computing how the VHDL-described hardware will behave
in response t o a given input timing sequence. The
simulator presented in this paper consists of two
primary sections:
o The Analyzer
o The Simulation Executive
The structure of the simulator is shown in Figure 1.
The analyzer checks f o r the static e r r o r s in the input
VHDL description. The analyzer flags e r r o r a s and when
there is a syntactical violation of the VHDL grammar.
The simulation executive simulates the
syntax-error-free VHDL description.
VHDL
Printed
Results
I I I r
Figure 1. The Block Schematic of the V H D L Simulator.
3.1 The Analyzer
As indicated earlier, the analyzer checks f o r s t a t i c
e r r o r s caused due t o syntactical e r r o r s in the input
VHDL description. The block schematic of the analyzer
is shown in figure 2. This phase involves the
following steps.
3.1.1 The Lexical Analyzer
The function of the lexical analyzer (also known a s the
scanner) is t o read in a given VHDL t e x t , discard
comments and white s p a c e (tabs, carriage return, line
feed, blanks), and generate a stream of tokens f o r the
next step (syntax analysis). A token is a sequence of
characters having a collective meaning. In VHDL, there
a r e several classes of tokens. They a r e [12-131:
o Keywords, like architecture, block.
o Delimiters, like '<=' (signal assignment), '\=' (not
equal).
o Identifiers, (includes names of variables, signals)
like R, S, COUNT.
o Literals
:decimal literals, like 12, 0.0, 1.OE+6.
:based literals, like 3#11-11#, 16#FF#, 8#7.71#E+2.
:character literals, like ' A ' , I*'.
:string literals, like "setup time is too short".
:Bit string literals, like X"FFF", 0"777", B"111".
The lexical analyzer has been developed using the Bell
lab's automatic lexical analyzer generator, LEX [16].
LEX generates a function which is repeatedly invoked by
the syntax analyzer t o obtain the next token from the
input program. Different classes of tokens such a s
identifiers, keywords, delimiters, and various types of
literals a r e defined in the required format f o r LEX.
The actions t o be taken when different types of tokens
a r e recognized, a r e also specified. In addition, when
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I E r r o r Handler I
I
VHDL i n p u t S t r e a m of t o k e n s I
1, [iexical]L+
[
I I To SE
I Symbol T a b l e 1
Figure 2. The Structure of t h e Analyzer.
an unrecognizable sequence of characters is
encountered, an error-handling routine is invoked. The
actions taken f o r different classes of tokens a r e a s
follows:
o Keywords and delimiters: the token code is returned.
o I d e n t i f i e r s and literals: the entity is installed in
the symbol table and the token code a s well a s the
address of the entity in the symbol table a r e
returned. In case of literals, the value is also
calculated and stored in the appropriate field of the
symbol table.
o White space: No action is taken in the case of white
space. A program listing is generated with the
inclusion of e r r o r messages.
3.1.2 The Syntax Analyzer
The syntax analyzer (also known a s the parser) checks
if the sequence of tokens coming from the lexical
analyzer is grammatically correct. There a r e two major
classes of parsing techniques [171:
o Top-down parsing, which includes predictive, LL(1),
and recursive-descent parsing.
o Bottom-up parsing, which includes operator-precedence
and different types of LR parsing.
Of these methods, look ahead left t o right scanning,
reverse of rightmost derivation parsing (in short, LALR
parsing), which is a class of LR parsing, is used.
This technique is selected because i t is adequate t o
handle the VHDL grammar a s specified in [I21 and
automated tools which generate parsers from a
description of the grammar a r e available f o r this
technique. An LALR parser generator, YACC [I81 is used
t o develop the syntax analyzer.
3.1.2.1 Basic concepts o f syntax-directed translation
A context-free grammar is a quadruple defined a s G =
(N,T,P,S), where N and T a r e disjoint finite sets of
nonterminals and terminals, respectively. P is a
finite s e t of productions; each production is of the
form A -> a , where A is a nonterminal, and a is a
string of terminals and/or nonterminals. S is a
special nonterminal called the s t a r t symbol. For
details, the reader is referred t o [171.
A syntax-directed definition/translation is a
generalization of a context-free grammar. With each
grammar symbol, a s e t of attributes is associated, and
402
 with each production rule, a set of semantic rules a r e
used t o compute the values of the attributes associated
with the symbols appearing in t h a t production. The
grammar and the set of semantic rules form the
syntax-directed definition. A syntax-directed
definition is a high-level specification
syntax-directed translation. If some implementation
details are visible, the scheme is called
syntax-directed translation. Usually, syntax-directed
def inition/translation involves parsing of the input
token stream, building the parse tree, and then
traversing the t r e e a s needed t o evaluate the semantic
rules a t the parse t r e e nodes. However, in special
cases, the evaluation of semantic rules is done during
parsing, without explicit construction of a parse tree,
resulting in a single-pass compiler [171.
In the present simulator the parser is is implemented
using the LALR(1) parser-generator YACC [ B l . YACC
generates a function which repeatedly calls the lexical
analyzer t o get the next token until the end-of-file is
encountered in the input program. This function
detects syntax e r r o r s in the input program, if any.
The input t o YACC consists of:
o A list of tokens
o The precedence and associativity of operators (if
necessary)
o The s t a r t symbol of the grammar
o A list of production rules, possibly embedded with
semantic action(s1 f o r syntax-directed translation.
A list of keywords, delimiters, rules f o r identifiers
and literals, and grammar rules f o r VHDL is provided in
[121.
The functions invoked by the parser t o perform semantic
actions fall into the following categories:
a. Routines t o attach semantic information t o the
symbols such as registers, input, and output lines,
the number of bits declared; f o r memory, the word
size and the number of words etc.
b. Routines f o r pure semantic checks performing
functions like checking f o r illegal access of memory
bits, out-of-range access of register bits, etc.
c. Routines f o r simulation.
3.1.3 The Semantic Analyzer
The semantic analyzer checks the input VHDL description
for semantic e r r o r s and gathers type information about
identifiers and does static type checking 1171. In the
present simulator a s such there is no separate semantic
analyzer rather i t is built into the parser itself.
The semantics of VHDL a s described in [12-131 a r e
incorporated.
3.2 The Simulation Executive
The design of the simulation part is partially deviated
from the established conventional techniques. In
conventional techniques, the analyzer normally
generates an intermediate code and the simulation is
performed on the this code. The intermediate code [171
provides a standard format t o work on f o r other tools
as well. The code is generated by the semantic action
parts of the lexical analyzer. In the present design,
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the generation of intermediate code is bypassed and the
simulation is directly implemented through the semantic
action parts. The semantic actions instead of
generating the intermediate code they implement
simulation executive. During syntax-directed
for translation, a s the sequence of tokens is parsed,
routines f o r simulation a r e invoked. In case of e r r o r s
in the syntax or semantics of the input program
statements, appropriate e r r o r messages are issued. The
syntax checking and simulation thus accomplished. This
technique provides f a s t e r simulation compared t o the
conventional methods.
4. IMPLEMENTATION ISSUES
The various implementation issues have been carefully
considered so t h a t compilation speed is reduced. These
implementation issues a r e discussed in the following
sections.
4.1 System Selection C r i t e r i a
The simulator has been developed and implemented on the
SEQUENT Balance 8000 running DYNIX V.3.0.4.5. This
system was selected because of the following reasons
listed in order of their importance:
a. The goal was t o integrate the VHDL simulator and a
VHDL silicon compiler currently under development on
the same system.
b. Compiler construction tools like LEX [16land YACC
[181 which reduce the design complexity considerably
a r e available on t h i s system.
c. The C programming language was chosen a s the
implementation language. The main reasons are:
o It provides good data structures, control flow
primitives, and a rich s e t of operators.
o Since C is a comparatively small language with
easy access t o machine-level information, i t forms
a good systems programming language.
o LEX and YACC generate routines in this language.
5. TEST RESULTS AND CONCLUSIONS
An VHDL test program has been developed t o t e s t a wide
variety of permissible VHDL syntax. The results of
execution in this t e s t program indicated t h a t the
simulator works correctly. The results of simulation
of two short VHDL programs a r e included in APPENDIX A.
It is found t o be a good educational tool f o r
understanding the syntax of the language. While VHDL
can be used t o simulate a t three levels of abstraction
the present simulator can simulate data flow and
behavioral level descriptions. I t is implemented on
the SEQUENT Balance 8000 running under DYNIX V.3.0.4.5
operating system.
REFERENCES
1. Shahdad, M., R. Lipsett, E. Marschner, K. Sheehan,
H. Cohen, R. Waxman, and D. Ackley. VHSIC Hardware
Description Language, Computer, pp. 94-103,
February 1985.
2. Shahdad, M. An Overview of VHDL Language and
Technology, 23rd Design Automation Conference, pp.
403
 320-326, June 1986. Example -1.
3. Waxman, R. Hardware Design Languages f o r Computer -- i n t e r f a c e d e c l a r a t i o n s
Design and Test, Computer, pp. 90-97, April 1986. e n t i t y ADDER ( s i g n a l A, B, CIN: i n BIT;
SUM, COUT: o u t BIT) is
4. Vyas, M. C. A Compiled-Code V H D L Simulator, M.S. end ADDER;
Thesis in preparation, Michigan Technological
University, Houghton, MI 1988. -- a r c h i t e c t u r e d e c l a r a t i o n s
a r c h i t e c t u r e ONEBIT o f ADDER is
5. Rao, V. A V H D L Silicon Compiler, M.S. Thesis in
preparation, Michigan Technological Univarsity, START: b l o c k (TRUE)
Houghton, MI 1988. begin
A <= n o t A a f t e r Ins;
6. VHSIC Hardware Description Language Request f o r B <= n o t B a f t e r 2ns;
Proposal, Inst. f o r Defense Analysis, Alexandria, CIN <= n o t CIN a f t e r 4ns;
VA, March 1983.
process
7. V H D L Language Reference Manual, Intermetrics, Inc., begin
Bethesda, MD, August 1985. c a s e ( A & B & CIN) is
8. V H D L User's Reference Guide, Intermetrics, Inc., when B"000" => SUM <= 0 after Ins;
Bethesda, MD, August 1985. when B"001" => SUM <= 1 after Ins;
when B"010" => SUM <= 1 after Ins;
9. V H D L User's Guide - A Tutorial, Intermetrics, Inc., when B " O l 1 " => SUM <= 0 after Ins;
Bethesda, MD, August 1985. when B"100" => SUM <= 1 after Ins;
10. V H D L Design Analysis and Justification, when B"101" => SUM <= 0 after Ins;
Intermetrics, Inc., Bethesda, MD, August 1985. when B"110" => SUM <= 0 after Ins;
when B"111" => SUM <= 1 after Ins;
11. V H D L Scenarios, Intermetrics, Inc., Bethesda, MD, end c a s e ; end p r o c e s s ;
August 1986.
process
12. CAD Language Systems Inc. I E E E Standard 1076 V H D L begin
Language Reference Manual, IEEE Press, New York, NY i f ( A & B & CIN) = 0 then COUT <= 0 after Ins;
1988. e l s i f ( A & B & CIN) = 1 then COUT <= 0 after Ins;
13. CAD Language Systems Inc. V H D L Tutorial f o r I E E E e l s i f ( A & B & CIN) = 2 then COUT <= 0 after Ins;
Standard 1076 V H D L , CAD Language Systems Inc., e l s i f ( A & B & CIN) = 3 then COUT <= 1 after Ins;
Rockville, MD June 1987. e l s i f ( A & B & CIN) = 4 then COUT <= 0 after Ins;
e l s i f ( A & B & CIN) = 5 then COUT <= 1 after Ins;
14. Nash, J.D. Bibliography of Hardware Description e l s i f ( A & B & CIN) = 6 then COUT <= 1 after Ins;
Languages, ACM SIGMA Newsletter, 14(1), pp. 18-37, elsif ( A & B & CIN) = 7 then COUT <= 1 after Ins;
February 1984. end i f ; end p r o c e s s ;
15. Aylor, J.H., R. Waxman, and C. Scarratt. VHDL - end b l o c k START;
Feature Description and Analysis, I € € € Design and end ONEBIT;
Test, pp. 17-27, April 1986. MONITOR : A, B, CIN, SUM, COUT;
16. Lesk, M.E. Lex - A Lexical Analyzer Generator, FORMAT : 5 x;
Computing Science Tech. Rep. 39, AT&T Bell Labs, CLKLIMIT : 8ns;
Murray Hill, NJ 1975. STEP : Ins;
DUMP : A, B, CIN, SUM, COUT;
17. Aho, A.V., R. Sethi, and J.D. Ullman. Compilers: 0 0 0 0 0 0
Principles, Techniques and Tools, Addison-Wesley, 10 1 0 0 0 0
Reading, MA., 1986. 20 0 1 0 1 0
18. Johnson, S.C. YACC - Yet Another Compiler 30 1 1 0 1 0
Compiler, CS Tech. Report 32, AT&T Bell Labs, 40 0 0 1 0 1
Murray Hill, NJ 1975. 50 1 0 1 1 0
60 0 1 1 0 1
70 1 1 1 0 1
80 0 0 0 1 1
S i m u l a t i o n Dump:
0 0 0 1 1

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 Example 2.
-- i n t e r f a c e d e c l a r a t i o n s
e n t i t y ADDER ( s i g n a l A, B, CIN: i n BIT;
SUM, COUT : o u t BIT) is
end ADDER;
-- a r c h i t e c t u r e d e c l a r a t i o n s
a r c h i t e c t u r e ONEBIT of ADDER is
START : b l o c k (TRUE)
begin
A <= n o t A a f t e r Ins;
B <= n o t B a f t e r 2ns;
CIN <= n o t CIN a f t e r 4ns;
w i t h ( A & B & CIN) select
SUM <= 0 when B"000" I B " O l 1 " I B"101" I B"110",
1 when B"001" I B"010" I B"100" I B"111";
COUT <= 0 a f t e r I n s when ( A & B & CIN) = 0 else
0 a f t e r I n s when ( A & B & CIN) = 1 else
0 a f t e r I n s when ( A & B & CIN) = 2 else
1 a f t e r I n s when ( A & B & CIN) = 3 else
0 a f t e r I n s when ( A & B & CIN) = 4 else
1 a f t e r I n s when ( A & B & CIN) = 5 else
1 a f t e r I n s when ( A & B & CIN) = 6 else
1 a f t e r Ins;
end b l o c k START;
end ONEBIT;
MONITOR : A, B, CIN, SUM, COUT;
FORMAT : 5 x;
CLKLIMIT : 8ns;
STEP : Ins;
DUMP : A, B, CIN, SUM, COUT;
0 0 0 0 0 0
10 1 0 0 0 0
20 0 1 0 1 0
30 1 1 0 1 0
40 0 0 1 0 1
50 1 0 1 1 0
60 0 1 1 0 1
70 1 1 1 0 1
80 0 0 0 1 1
S i m u l a t i o n Dump
0 0 0 1 1

G . N. Reddy

Presently an Assistant Professor at Michigan

Technological University, in the Department of
Electrical Engineering. Research interests include
VLSI CAD-tools, hardware description languages, fault
diagnosis and fault tolerant design. Currently
working on development of high-performance VLSI CAD
tools using multi-faceted knowledge, hierarchical
layout generation, VHDL tool development, and neural
networks. Member of several professional societies
including IEEE, INNS, IASTAD, and SCS.

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