Using Apache Totem™ for

Power Noise Analysis of

Analog / Mixed-Signal Designs

Copyright ©2009 Apache Design Solutions

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

Introduction

The convergence of advance process technology, increasing levels of integration and

higher operating frequencies pose considerable challenge to IP designers whose
circuits are required to function in variety of conditions. Full-custom and mixed-signal
circuit designers ensure that their circuits will function by simulating for various
operating conditions (PVT, input stimuli, etc). One key aspect for the reliable
operation of these complex circuits is the quality of the voltage supply they receive.
However, the traditional and existing methods of considering power supply variation
and noise is grossly inadequate and do not consider the multiple factors that
contribute to power and ground supply noise. Existing methods do not provide
sufficient capabilities to predict the impact of the fluctuation in the power and ground
supplies on various key circuit parameters like noise margin, clock jitter, and delays.
Additionally, in traditional IC design methodologies, the custom IPs are typically
designed and verified independent of the environment they operate in. However, the
impact of integrating digital and mixed- signal IP blocks in SoCs and ASICs is
considerable in both directions – from the IP to the chip and from the chip to the IP.

The critical area of power noise analysis and reliability verification targeting analog
and mixed signal circuits, both by themselves and in context of the chips they operate
in, have not been adequately addressed by existing solutions. There is a need for an
integrated analysis, verification and optimization solution.

The Totem™ platform from Apache Design Solutions provides a comprehensive

co-simulation framework for analog, mixed-signal, and custom circuit designers. It
analyzes static (IR, EM) and dynamic noise (DvD1) for the power and ground network
at the IP or full-chip level, and the impact of current flow on signal lines (signal EM). It
also provides a comprehensive full-chip solution for modeling and simulating noise
injection, propagation, and coupling through the on-die power grid RLC, substrate RC,
and package RLC networks. Totem operates at the transistor level using standard
industry format data as input and provides results in an easy-to-use, unified
environment.

Defining Power Noise

Power noise results from the simultaneous switching of devices and the inability of
the power delivery network to supply the instantaneous current demand. As large
number of transistors placed close together switch around the same time, they
require charge for their load capacitances. This charge can be supplied by

1
DvD: Dynamic voltage Drop

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 Power and Noise Integrity for
Analog / Mixed-Signal Designs

capacitances on the chip or in the package, or from the battery or regulator. However
the resistance and inductance of the power and ground networks impede this current
flow from the battery/regulators. As the current demand changes with time, the
voltage supply fluctuation (Ldi/dt) causes uncertainty in the operation of the devices.

Simultaneous switching not only causes fluctuations on the power/ground routings

but also introduces noise into the substrate on which the devices are etched. This
noise propagates through the substrate and impacts the operation of other devices
etched on the same substrate. The isolation techniques used to protect sensitive
circuits are often not adequate to protect against such noise.

Power noise not only affects the operation of a device but also has long term circuit
reliability implications. This is true especially for advanced technology nodes where
electromigration is becoming an increasing concern. Therefore, the current flow, both
transient and DC, is an important consideration for power and signal lines.

Impact of Power Noise on Analog, Mixed Signal, and Custom Circuits

With increasing frequency requirements on custom IPs, designers have to manage

clock skew and evaluate more logic in less time. As a result they need to use
aggressive design styles by placing transistors closer together, switching them faster,
and eliminating margins. This not only increases the risks of circuit failures but also
leads to increased switching current requirements, both temporally and spatially,
thereby injecting noise into the power and ground networks, as well as into the
substrate.

For SRAM designs, fluctuations on the power and ground rails of a bit-cell can cause
a ‘state-upset’ thereby changing the logic state of the memory cell. A ‘state-upset’ is
an irrecoverable error and usually increases the overhead for ECC or parity
protection on memories. Power and ground noise can also cause high yield fallout
during memory BIST testing for weak bits.

High-performance IOs such as DDRs and Serdes are especially vulnerable to

simultaneous switching events because they drive a large amount of off-chip loads.
When an IO buffer switches, the current required to charge an off-chip load typically
flows through the power and ground terminals of the buffer. The large current coupled
with poor strapping of the power and ground nets can lead to a large dynamic voltage
drop. This leads to delay push-out causing large jitter through these buffers

Sensitive analog circuits placed close to high frequency digital logic experience noise
through the substrate. Even with isolation mechanisms, the noise is often significant
enough to impact the biasing conditions and operation of these circuits. Wireless
communications ICs integrate analog RF and base-band digital circuits on the same
die. The noise from the latter can affect the small signal operation of the former

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

resulting in functional failures and performance degradation.

Requirements for AMS Power Noise Analysis Flows

The design methodology for today’s SoC is a bottom-up approach. The IPs are
designed and validated independently by one team and the SoC is integrated by a
separate team. This methodology promotes design and IP reuse and also accelerates
the SoC place and route process. However, this flow imposes challenges on the
power noise verification methodology as it requires block/IP level analysis with the
flexibility to model top level connectivity and noise coupling scenarios. Once the block
or IP has been validated, this solution should enable model creation with the ability to
embed IP level design constraints. This model should provide transistor level detail
but allow full-chip level analyses without compromising run-time and capacity needs.

At the full-chip level, the power noise analysis solution should consider one or more
IP models along with other logic, and perform a global power noise simulation
incorporating the package and board effects. The full-chip analysis must provide
feedback to the IP designers about the impact of noise source on their blocks, be it
through the shared power-ground mesh, the substrate, or the coupling from high
energy in specific frequency bands of interest.

Shortcomings of Conventional Approaches

Traditionally, circuit designers have used static voltage drop analysis to identify and
prevent power supply related issues. Static voltage drop analysis provides the ability
to quickly check the general weaknesses in the power and ground network by using
average current consumption of every device and solving Ohms law. However, static
analysis does not consider the impact of capacitance and inductance of the power
ground network on voltage drop. Static analysis can be used to find gross
weaknesses during early design phase; however it does not accurately describe the
true transient nature of the power and ground noise. Neither can it be used to
understand the coupling of noise through the substrate network, nor can it be used to
understand the impact of switching of one block on another. Figure 1 illustrates the
difference between static / DC and
dynamic / transient analysis.

To capture the transient nature of

power and ground noise on circuits,
the design industry has historically
relied on spice or fast-spice
approaches for analysis. Fast-spice
Figure 1: Example of an average current
simulators have some inherent
versus a peak current envelope.
shortcomings when they are used to

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

analyze or validate power-ground noise impact on circuits.

Capacity: Even though fast-spice simulators utilize methods such as model reduction,
model reuse, and current mode modeling they have been unable to keep up with the
growing pace of a power grid’s RLC network complexity.

Usability: The parasitic netlist is typically extracted using a third party extraction
engine and simulated by combining the pre-layout netlist with the post-layout
extraction results. Therefore identifying IR and EM bottlenecks in power-ground
networks cannot be done easily.

Co-simulation: Fast-spice simulators cannot integrate into a full-chip analysis

framework for power and ground noise.

Interactive Fix and Verification: The turn-around cycle for design changes and
analysis usually involves making a layout change followed by extraction of the layout
and then simulation of the design.

To overcome these limitations, the designers use simplified Spice netlists to predict
power noise scenarios or use silicon measurement data from one version of a chip to
define the design methodology for the next generation of the chip. However the
former method is limited in scope and cannot comprehend the full-chip scale and the
nature of substrate noise injection and propagation. The latter approach assumes that
past design techniques and measurements will be good indicators for future designs.
However due to the complexities associated with new processes, design teams either
over-design or work through few revisions of the chip before they get it to work per
specification and at speed.

Totem: An Integrated Platform for Analog, Mixed Signal, and Custom Design
Power Noise Verification and Analysis

The Totem platform from Apache Design Solutions is a transistor-level power/ground

noise analysis and verification platform, addressing static and dynamic power
integrity needs from an early state in the design to sign-off validation. The Totem
platform addresses the verification of IPs designed using a full-custom or
semi-custom approach for both analog and mixed signal designs. This IP validation
methodology allows designers to verify power grid connection problems, identify high
voltage drop causing mechanisms, and isolate electromigration bottlenecks.

Totem also provides signal electromigration simulation capability for full-custom digital
designs with the ability to analyze uni-directional and bi-directional currents for
average, RMS, and peak limits. It provides a unified power noise model creation
capability with temporal and spatial accuracy for transistor currents. These models
can further be integrated into the SoC analysis platform provided by RedHawk™.

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

The Totem platform can be used, though not limited to, on the following types of
designs.

• Embedded memory and IP macros such as SRAM, CAM, TCAM and ROMs
• Memory chips such as DRAMS and Flash memories
• High performance IOs such as Serdes, DDR, PCI-X
• SoC and ASIC designs employing one or more of the above circuits
• Power management ICs
• Custom, high performance digital logic

Input Data Requirements

Totem uses industry standard input data for the IPs including GDSII formatted layout
information, Spice netlist in the DSPF/SPEF format, and test-bench or input vectors in
the Spice format. If the analog or mixed signal design is an IC by itself, the package
layout will be necessary for a full-chip level analysis.

Modeling and Simulation Flow

Once the required input data are available, the first step
is to setup and “pre-characterize” the circuit. The layout
and pre-characterization data are read in along with the
optional package layout or netlist information to perform
the necessary simulations. Next, the weakness and
hot-spot analysis can be done along with interactive
design fixing to isolate and rectify the issues in the
design. Subsequently a multi-state transistor level model
can be written out for SoC level analysis.

The Dynamic voltage drop on the power-grid is defined

by V(t) = i(t)R + Ldi/dt where i(t) is the total
Figure 2: Analysis flow using
instantaneous current (sum of the transient switching
current is(t) and the capacitor current ic(t)) and L is the
on-chip and package self and mutual inductances. Figure 3 shows a schematic
representation of two inverters in a chip, one of which is switching and one of which is
not switching.

Totem is able to perform analysis of large IPs while maintaining the spice level
accuracy. It transforms the “non-linear” nature of the circuit into a “linear” form by
pre-characterizing the current, intrinsic resistance, and device capacitances for each
transistor in the circuit. By solving this “linear” circuit with its proprietary solver
technology, Totem provides the current and voltage information at every wire, via, and
transistor in the circuit.

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

After characterization, the first stage in

simulation process is the extraction of
the power and ground parasitic network.
In this stage, Totem uses an integrated,
high-performance RLC parameter
extraction engine, including Apache’s
proprietary Mesh Pattern Recognition
(MPR), to obtain the parasitics of the
PG network. The extraction is done on
all the power domains in the design and
can selectively include the capacitance
and inductance of the mesh as needed.
Figure 3: Modeling flow in Totem.
Next, every transistor is replaced with
its equivalent, pre-characterized model.
For static/DC analysis, an average or the peak of the device current can be used in
the current sink. For the transient/DvD analysis, the true characterized transient
current profile is used along with the
associated effective transistor
resistance and capacitances. For static
analysis, the DC voltage and current is
computed for every wire and via
starting from the voltage sources to the
transistors. For the transient analysis,
time-domain current and voltage
waveforms are calculated for each
wire and via. The Totem DvD analysis
modulates the transistor current based
on the voltage seen at that transistor
for every simulation time-step to Figure 4: Steps in Totem-MMX simulation.
deliver Spice accurate results at a full
IP or even at the full-chip level.

The electromigration (EM) for the wires and vias are simultaneously determined
based on the currents flowing through the different nodes of the power and ground
mesh. For static analysis, DC or average EM limits are checked. For transient,
average, RMS, and peak EM limits are checked for possible violations. The RMS and
peak EM checking is possible since Totem does a “true” time-domain analysis to get a
waveform of the current flowing in every wire and via in the circuit. Totem supports all
the advanced EM limits and rules. Additionally it provides the designers with access
to the Totem data-base to obtain current flow and associated routing topology
information for every wire and via. This information is needed if the designers want to
write their own EM rules.

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

Using Totem-MMX to Debug and Fix Power Noise Issues

The Totem platform offers advanced capability to view, debug, and fix power noise
violations, and to identify the EM bottlenecks in the design. Totem GUI provides
cross-probing of violations with the layout and interactively analyze the fixes made to
the design. The main features of the Totem GUI include

• Comprehensive P/G net layout viewer

• Built-in GDS viewer to cross probe with EM/IR maps
• Metal EM, IR and current map
• Transistor based IR, current, decap, and resistance map
• Cross-probing violations with 3rd party layout viewers

Totem’s layout view enables the user to customize their environment to view different
metal layers in the design. The Totem layout view can also be combined with a GDS
view where the complete layout of the design along with the base layers can be
imported and viewed for concurrent display. Figure 5 shows a sample screen of the
Totem GUI with the cross-probing between IR drop view and layout view.

Figure 5: Totem multi-pane view of layout and IR violations for debug

The Totem GUI also provides a powerful ‘what-if’ capability where the user does not
need to commit fixes in the layout environment before verifying the fixes in the Totem
platform. Interactive fixes can be made by modifying, adding or removing metal or via
geometries in the design. Once the modification is done in the Totem GUI, an

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

incremental extraction is performed and the design is re-analyzed. This interactive

‘what-if’ capability provides the IP designer the ability to make sure that the proposed
changes indeed fixes the violations.

The Totem debug platform shares its capabilities with the RedHawk SoC platform.
The violations that are seen at the IP level can also be viewed and cross-probed at
the SoC level, therefore giving the SoC designer a unified platform for IP and SoC
co-analysis and validation.

Model Creation for SoC Level Power Noise Analysis

Totem provides the user not only the capability to

analyzes and validate the power noise issues at the
IP level but also the ability to generate models that
can be used for SoC or top-level power noise
validation. Totem is used to perform block/IP level
design analysis by incorporating top level
connectivity and noise coupling scenarios. Once
the block or IP has been validated, a detailed model
can be generated for top level analysis. The
detailed Totem model captures the layout and
circuit behavior of the IP, and can be used
seamlessly in a top level analysis. It also provides
the capability to embed design constraints in the Figure 6: Totem model creation with

model that can be checked during the top level embedded design constraints.

analysis. The flow for embedding design constraints

in a Totem model is shown in Figure 6.

Figure 8: Different states captured in Totem model.

In addition, Totem model can store unlimited number of ‘states’ or operational modes
with different electrical signature for each of the states. Figure 7 shows the switching

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

current profile for a memory. The model captures the different modes like “read”,
“write”, etc., and associates the appropriate current and other parameters with each
state. In the top level analysis one or more of these states can be switched to
simulate different operating modes of the chip. For analysis of large SoC designs with
IPs, Totem can create optimized models that can trade-off precise transistor level
modeling details with higher capacity and run-time benefits.

Full-chip Power Noise Analyses for Mixed Signal Designs

Totem models can be used for full-chip analysis

of mixed signal design without compromising
accuracy and runtime. It can simultaneously
simulate the switching behavior of standard
cells and the analog and custom blocks using
the Totem models. This helps designers to
verify the top level connections to the analog
and custom blocks under various coupling
scenarios. It also helps assess the impact from
the switching of mixed-signal blocks on shared
or coupled power and ground networks.

Mixed-signal designs are typically divided into Figure 8: Full-chip analysis of mixed signal
two categories, namely, Large Digital/Small design.
Analog and Large Analog/Small Digital designs.
Totem can seamlessly model and simulate
these two types of designs based on the LEF/DEF of digital blocks and the Totem
physical models of the analog circuits. Figure 8 shows a sample analysis of a Large
Digital/Small Analog SoC design with the usage of Totem models for the Small Analog
IPs.

Signal Line Reliability Analysis Modeling and Flow

Totem provides a single platform approach to analyze power line and signal
interconnect EM in a design. Power EM analysis is performed as part of static and/or
dynamic analysis. Signal EM analysis, which is performed in a separate run, checks
for average, RMS, and peak current densities in all signal wires and vias. Totem
signal EM analysis provides text-based reports and graphical maps.

Totem Signal EM pre-characterizes the switching currents for transistors that are
connected to the signal nets and uses it to model the RMS, average and peak
currents on a signal net. Once the currents are captured, the value is compared
against the specific current limits specified in the technology file. The EM limits can be
specified in the technology file as a dependent on physical parameters including the

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

width of the wire, length of the wire, size of via,

and temperature of the die. The EM limits can
also be specified as a polynomial dependant on
width or length to support advance process
nodes.

The main inputs for Totem Signal EM flow is the

GDS of the layout, the simulation test bench,
and the DSPF of the design. Spice simulation is
run on the design using the test-bench and
captures currents for all the transistors
connected to signal nets. Once the currents are
Figure 9: Totem Signal EM flow. captured the signal net information from the
GDS is extracted and the accurate current
through the different nodes on the signal nets
are estimated. Then the estimated currents on the signal nets are compared to the
EM current limits for each segment of wire. The Totem Signal EM flow is outlined in
figure 9.

Figure 10: Totem Signal EM analysis and debug flow.

Based on the EM percentages calculated for each segment, the Totem GUI can
display the design on a net by net basis for easy debug. The signal EM map can also
be cross-probed with other third party layout viewers. A complete analysis and debug
flow for Totem signal EM capability is shown in Figure 10.

Copyright © 2009 Apache Design Solutions, Inc.

 Power and Noise Integrity for
Analog / Mixed-Signal Designs

Summary

Totem platform from Apache Design Solutions continues on the tradition of RedHawk
by providing full-chip capacity and quick turn-around time for analyzing power noise
and reliability challenges of today’s and future analog and mixed signal designs. It
provides Spice like accuracy that has been correlated to silicon measurements. By
using its integrated, highly flexible GUI and layout driven simulation and debug
capabilities, designers can identify issues with their design and explore fixes within
the same environment. It brings in noise generation (switching digital and analog
circuits), noise propagation (package, on-die PG mesh), and noise impact (timing,
functionality, EM, layout changes) analyses inside the same platform, enabling the
highly integrated designs in the newer technology nodes to function per specification
and at speed.

Copyright © 2009 Apache Design Solutions, Inc.