SSN College of Engineering

Department of Computer Science and Engineering

UCS1401 – Computer Organization and Architecture

Tutorial

Draw the memory interface diagram with two numbers of 4K x 8 EPROM chips and
one 8K x 8 RAM chip. Assume the address bus size of the processor as 16 bit.
Allocate lower address ranges for EPROM. Also specify the address ranges of
memory ICs.
(10 Marks)

Submit your design in form of images (photo) / Doc/ docx / Pdf

Deadline of submission : 20 / 04 / 2020 : 3:00PM