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dead time in both turning on and off modes, four modes will the current path, otherwise the current will pass through q 1
occur during switching period as shown in Fig. 2(a): and the body diode of q2. When –vw2 + vC becomes larger
For vi>0, at the time interval I, q1 is turned on and q3 is than input voltage source (i.e. -vw2 + vC>vin), the body diode
turned off. During this mode, the capacitor C is charged. of q2 is turned off and the capacitor C is discharged. The
At time interval II, q3 is turned on while q1 has not still proposed safe commutation strategy is depicted in Fig. 3.
been off due to non-ideal characteristics of switches. Hence,
two voltage loops will be formed, (i) The first loop contains For buck out of phase mode, if vi>0, q1 and q4 otherwise
the input voltage, vi, the secondary side of coupled q2 and q3 are modulated. For vi>0, q1 and q4 are modulated
transformer and capacitor, and (ii) The second loop consists in this structure while q2 and q3 are fully on. If iLf + iLk>0,
of the coupled transformer and capacitor. Therefore, a then q2 and the body diode of q1 will provide the current
sudden change in capacitor voltage occurs which results in path. But if iLf + iLk<0, the current will pass through q3 and
current spikes in the bidirectional switches. the body diode of q4. For vi<0, the same method should be
At time interval III, q1 is turned off and q3 is turned on. In used as shown in Fig. 3.
this mode, the capacitor C is discharged. The safe commutation strategy for boost out-of-phase
At time interval IV, q3 is turned off before q1 is turned on mode is on contrary with Fig 3 where q1 and q4 are fully on
due to non-ideal characteristics of the switches. In this time when the input voltage is negative. Also q2 and q3 are fully
interval, the series connection of output filter inductor and on when the input voltage is positive.
Boost In-Phase Buck Out-of-Phase
primary side of the coupled transformer results in a sudden VO Vi
Vi
change in inductor current. Therefore a voltage spike on VO
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Cf
1 Due to the capacitor, ESR, ΔILR dominates ΔILC . Hence,
2 fC RL
(16)
vCR
L ( D).(1 D)T
Where, fc and RL are cutoff frequency and load resistance, I LR (25)
respectively. ε is a constant between 0.5 and 0.8 [7].
4. Voltage and Current Stress of Switches: The maximum
3. Input Filter Design: In some applications like voltage voltage of bidirectional switches, are as follows:
sag/swell compensators the switches, q1 and q2 at input side 2Vi
can be used for bypass mode of compensator [29]. However, Vs1max Vs2 max 2(Vi VLm ) (26)
(D 1) 1
in order to attenuate the switching harmonics in the converter
The RMS current values of two switches are calculated in
input current, an input filter is of great importance [30]. The
(27) and (28).
input LC filter has become very critical in its design and must 1 PO
be designed not only for conducted electromagnetic interface I s1 rms 1 DIi (27)
1 D Vi
(EMI) but also for system stability. The equivalent circuit of 2 (1 D) 1 PO
I s2 rms D (i 2 i L f ) D ( ) (28)
the input filter is also shown in Fig. 4. The voltage vC is the (1 D)( 1) Vi
sum of the voltage across the equivalent series resistance D. Proposed -Z-Source Converter versus Other Z-Source
(ESR) and the reactance of the capacitor. Topologies
Lf RL 1. -Z-Source Converter In Comparison With Previous
Rd Topologies: Table. I indicates the boost factor, currents and
Vin Switching
Cf
Cd Converter
voltages of utilized components in the proposed topology,
conventional converter [6] and the quasi-Z-source AC-AC
Fig. 4. Input LC filter.
converter presented in [17]. Ii, IL1, IL2, ILm and Vi are the RMS
values of input, inductor, Lm currents and input voltage,
The voltage developed across the capacitance is: respectively. Po is output power. Is,max and, Vs,max are RMS
D.(1 D) values of current and voltage stresses of switches, respectively.
vCC IC
C1.T (17) It is obvious from this table that the proposed topology uses
Also, the voltage across the ESR is developed as: less components in comparison with conventional AC-AC Z-
vCR IC .( ESR) (18) source converter [6] and the same number of elements in
Hence, comparison with the topology presented in [15], considering
vC vCC vCR (19) the input LC filter for the proposed -Z-source converter.
The input filter can affect the stability of the switching Also, the boost factor of the proposed converter is higher and
converter. In order to avoid this to happen, the output has wider range of control due to the use of coupled
impedance of the input filter should be lower than the open transformer. Voltage and current stress in all three topologies
loop input impedance of the converter, i.e.: are nearly the same considering both buck and boost modes of
Zin Zof (20) operation.
Fig. 5 shows the output voltage gains versus the duty cycle,
.(Vin )2 L D, with variable turn ratios of . This figure depicts that
PO C ( RL RS ).( ESR) there are three operation regions: (i) When duty cycle is
( RL RS ) ( ESR) (21)
smaller than γ Γ -1 , the output voltage is boosted and in-phase
γΓ
Where is the converter efficiency, Vin is the maximum
with the input voltage, (ii) when duty cycle is gG -1 < D < 2(gG -1) ,
input voltage, PO is the output power in watts, L is the input gG 2g G -1
inductor in henrys, C is the filter capacitor in farads, RL is the the output voltage is boosted out of phase with the input
inductor series resistance in ohms, RS is the source resistance voltage, and (iii) when duty cycle is 2(γΓ -1) <D<1 , the output
in ohms, and Rd is equivalent series resistance (ESR) in ohms. 2γ Γ -1
If additional damping is required it can be done by voltage is bucked and out-of-phase with the input voltage.
increasing Rd or RL [see Fig.4]. Also, the efficiency comparison in boost in-phase operation
If parallel damping was necessarily required, Rd and Cd can mode of the proposed converter with previous topologies [6,
be calculated as follows: 17 and 28] is obtained within experimental results in the
Rd
L
, 4C Cd
experimental results section. As it is shown in this section, the
C (22) efficiency of the proposed converter is higher than previous
The input filter, L, is designed as follows. Considering the topologies.
inductor current ripple developed by vCR to be I LR :
vCR
I LR ( ) D.(1 D)T (23)
L
Also, the inductor ripple current developed by, ΔILC is as
follows:
vCC T
I LC ( )( )
2L 4 (24)
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Conventional
Quasi-Z- From equalization of (30), for 1 nT , the turn ratio of -
source Proposed -Z-
converter in
converter in source converter
structure will be 1<γΓ <2 . It is obvious from (29) that, increasing
[6]
[17] nT results in higher voltage gain. Although this feature is
Vo 1 D 1 D
1 D B natural for most of the transformer-based power electronic
Vi 1 2D 1 2D 1
1 D(1 ) converters, but it is a drawback for required some voltage
1
VC1 1 D D
Vi 1 2D 1 2D gains, making the converter impracticable. The equation of
1 D
(10) shows that the voltage gain of -Z-source converters
VC2 1 D 1 D B -
1 D(1
1 increases while decreasing the transformer turn ratio. γ Γ is
Vi 1 2D 1 2D 1
)
within the narrow range of (1,2]. Fig. 7 shows that the current
Po Po
IL1 &IL2
Vi Vi - passing through both transformer structures are nearly the
Po same. Although smaller transformer turns results in higher
ILm - - Vi nH/t2 of the transformer core but this feature is more practical
Ii
Po Po Po in larger voltage gains [27]. This is because, for tight coupling
1 DVi Vi 1 DVi
of the transformer, especially at low voltage side, the number
PO
I s1 max 2
Vi (1 D)
of turns should be large enough. This results in even larger
2 Po 2 Po
Is-max turns in the transformer high voltage side. For example instead
(1 D)Vi (1 D)Vi 2 (1 D) 1 PO
I s2 max 2 .
(1 D)( 1) Vi of nT=3 in T-structure, a turn ratio of ngamma=1.33 can be used.
2Vi 2Vi 2Vi Hence, less turn ratio in gamma results in more practical
Vs-max
1 2D 1 2D (D 1) 1 topology. It makes the transformer design easier and reduces
construction cost remarkably [31 and 32].
Coupled Transformer Current (A)
20
15 Gamma Z-Source Converter
Gamma=1.3
Gamma=1.4 15 Trans Z-Source Converter
10
Gamma=1.5
Voltage Gain
5 Gamma=1.6
10
0
5
-5
[6] and [17]
0
-10
1 1.2 1.4 1.6 1.8 2
-15 Turn Ratio
0 0.2 0.4 0.6 0.8 1
Duty Cycle (D) Fig. 7. Current passing through coupled transformer in both T and
Fig. 5. Output voltage gain versus duty cycle with variable ratio of . structures.
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RLoad-LLoad 60Ω-100mH
Figures. 9-10 (a) and (b) show the voltage across the
switches q1 and q2, q3 and q4 in boost mode, respectively. The
problem of voltage spikes has been solved properly after using
safe commutation strategy. Figures. 9-10 (c) and (d) show the
input current flowing through q1, q2, q3 and q4 switches in
boost mode, before and after using safe commutation strategy,
respectively. It is clear from the figures that safe commutation (a) (b)
strategy has prevented the current spikes thoroughly.
(c) (d)
(a) Fig. 10. Voltage and current of q 3 and q4 before and after safe commutation
strategy for boost mode. a) vq3-q4 before safe commutation strategy, ( 1v / div ),
b) vq3-q4 after safe commutation strategy, ( 10 1v / div ), c) iq3-q4 before safe
commutation strategy, ( 10 1A / div ), d) iq3-q4 after safe commutation strategy,
( 1A / div ).
100
Gamma Z-source
Efficiency (%)
Modified Quasi [28]
(b) 90
Fig. 8. Experimental results, (a) input and output voltages, ( 1v / div ), boost in-
80
phase mode D=0.3, (b) input and output voltages, ( 11v / div ), buck out-of-
Quasi Z-source [17]
phase mode D=0.7. 70
IV. CONCLUSION
A novel single phase AC-AC Z-source converter based on
-structure of coupled transformer is proposed in this paper.
(a) (b) A novel safe commutation strategy is also employed. The safe
commutation strategy is a significant improvement as it makes
it possible to avoid voltage and current spikes on the switches.
The operation principal, steady state analyses and parametric
design are presented in detail. The output and input voltages
share the same ground in the proposed converter. Transformer
ratio is controlled in a small range of 1<γΓ <2 . The gain factor
increases while reducing the transformer ratio. This exclusive
feature results in a practical converter for some voltage gains.
(c) (d) The input LC filter design is also provided to attenuate the
Fig. 9. Voltage and current of q1 and q2 before and after safe commutation
strategy for boost mode. a) vq1-q2 before safe commutation strategy, ( 1v / div ),
switching harmonics that are presented in the converter input
b) vq1-q2 after safe commutation strategy, ( 10 1v / div ), c) iq1-q2 before safe current. Experimental results are also provided to verify the
commutation strategy, ( 10 1A / div ), d) iq1-q2 after safe commutation strategy, validity of the proposed structure. The boosted in-phase and
( 1A / div ). bucked out-of-phase output voltages, the current passing
through the switches and the voltage across them are shown
before and after using safe commutation strategy within
experimental results
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