IRF530

Data Sheet February 2002

14A, 100V, 0.160 Ohm, N-Channel Power Features

MOSFETs • 14A, 100V
[ /Title These are N-Channel enhancement mode silicon gate
• rDS(ON) = 0.160Ω
(IRF53 power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a • Single Pulse Avalanche Energy Rated
0,
specified level of energy in the breakdown avalanche mode • SOA is Power Dissipation Limited
RF1S5 of operation. All of these power MOSFETs are designed for
30SM) applications such as switching regulators, switching • Nanosecond Switching Speeds
/Sub- convertors, motor drivers, relay drivers, and drivers for high • Linear Transfer Characteristics
ject power bipolar switching transistors requiring high speed and
• High Input Impedance
(14A, low gate drive power. These types can be operated directly
from integrated circuits. • Related Literature
100V,
- TB334 “Guidelines for Soldering Surface Mount
0.160 Formerly developmental type TA17411.
Components to PC Boards”
Ohm,
N- Ordering Information Symbol
Chan- PART NUMBER PACKAGE BRAND D
nel IRF530 TO-220AB IRF530
Power
MOS- G
NOTE: When ordering, use the entire part number.
FETs)
/Autho S

r ()
/Key-
words Packaging
(14A, JEDEC TO-220AB
100V,
0.160 SOURCE
DRAIN
Ohm, GATE
N-
DRAIN (FLANGE)
Chan-
nel
Power
MOS-
FETs,
Inter-
sil
Corpo-
ration,
TO-
220AB
, TO-
263AB

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
©2002 Fairchild Semiconductor Corporation IRF530 Rev. B1
 IRF530

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

IRF530 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 14 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 10 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 56 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD 79 W
Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.53 W/oC
Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS 69 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 150oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 100 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = 95V, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 150oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON) MAX, VGS = 10V 14 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±500 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 8.3A, VGS = 10V (Figures 8, 9) - 0.14 0.16 Ω
Forward Transconductance (Note 2) gfs VDS ≥ 50V, ID = 8.3A (Figure 12) 5.1 7.6 - S
Turn-On Delay Time td(ON) VDD = 50V, ID ≈ 14A, RG ≈ 12Ω, RL = 3.4Ω - 12 15 ns
Rise Time tr MOSFET Switching Times are Essentially - 35 65 ns
Independent of Operating Temperature
Turn-Off Delay Time td(OFF) - 25 70 ns
Fall Time tf - 25 59 ns
Total Gate Charge Qg(TOT) VGS = 10V, ID = 14A, VDS = 0.8 x Rated BVDSS - 18 30 nC
(Gate to Source + Gate to Drain) Ig(REF) = 1.5mA (Figure 14)
Gate to Source Charge Qgs Gate Charge is Essentially Independent of - 4 - nC
Operating Temperature
Gate to Drain “Miller” Charge Qgd - 7 - nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 600 - pF
Output Capacitance COSS - 250 - pF
Reverse Transfer Capacitance CRSS - 50 - pF
Internal Drain Inductance LD Measured from the Modified MOSFET - 3.5 - nH
Contact Screw on Tab To Symbol Showing the
Center of Die Internal Devices
Measured from the Drain Inductances - 4.5 - nH
D
Lead, 6mm (0.25in) from
Package to Center of Die LD
Internal Source Inductance LS Measured from the Source - 7.5 - nH
Lead, 6mm (0.25in) From G
Header to Source Bonding LS
Pad
S

Thermal Resistance Junction to Case RθJC - - 1.9 oC/W

Thermal Resistance Junction to RθJA Free Air Operation - - 62.5 oC/W

Ambient - - - -

2
©2002 Fairchild Semiconductor Corporation IRF530 Rev. B1
 IRF530

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET Symbol - - 14 A
Showing the Integral D
Pulse Source to Drain Current (Note 2) ISDM - - 56 A
Reverse P-N Junction
Diode
G

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 14A, VGS = 0V (Figure 13) - - 2.5 V
Reverse Recovery Time trr TJ = 25oC, ISD = 14A, dISD/dt = 100A/µs 5.5 120 250 ns
Reverse Recovery Charge QRR TJ = 25oC, ISD = 14A, dISD/dt = 100A/µs 0.17 0.6 1.3 µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, starting TJ = 25oC, L = 530µH, RG = 25Ω, peak IAS = 14A (Figures 15, 16).

Typical Performance Curves Unless Otherwise Specified

1.2 15
POWER DISSIPATION MULTIPLIER

1.0
12
ID, DRAIN CURRENT (A)

0.8
9

0.6

6
0.4

3
0.2

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

10
ZθJC, TRANSIENT THERMAL IMPEDANCE

1 0.5

0.2
0.1 PDM

0.05
0.1
t1
0.02
t2
0.01
NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
0.01
10-5 10-4 10-3 10-2 0.1 1 10
t P, RECTANGULAR PULSE DURATION (s)

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

3
©2002 Fairchild Semiconductor Corporation IRF530 Rev. B1
 IRF530

Typical Performance Curves Unless Otherwise Specified (Continued)

10 3 25
OPERATION IN THIS
VGS = 7V
AREA MAY BE VGS = 10V
LIMITED BY rDS(ON) VGS = 8V
20

ID, DRAIN CURRENT (A)

10 2
ID, DRAIN CURRENT (A)

PULSE DURATION = 80µs

10µs DUTY CYCLE = 0.5% MAX
15
100µs
10 VGS = 6V
1ms
10
10ms VGS = 5V
1
5
TC = 25oC
TJ = 175oC VGS = 4V
SINGLE PULSE 0
0.1
0 10 20 30 40 50
1 10 10 2 10 3
VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

25 100

IDS(ON), DRAIN TO SOURCE CURRENT (A)

PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX VGS = 8V DUTY CYCLE = 0.5% MAX
VDS ≥ 50V
20 VGS = 7V
ID, DRAIN CURRENT (A)

VGS = 10V 10
15
VGS = 6V

10 175oC 25oC
1
VGS = 5V
5
VGS = 4V

0 0.1
0 1 2 3 4 5 0 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

1.5 3.0
PULSE DURATION = 80µs PULSE DURATION = 80µs
rDS(ON), ON-STATE RESISTANCE (Ω)

DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX

NORMALIZED ON RESISTANCE

VGS = 10V, ID = 14A

1.2 2.4

0.9 1.8

0.6 1.2

VGS = 10V
0.3 0.6

VGS = 20V
0 0
0 12 24 36 48 60 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
ID, DRAIN CURRENT (A) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE

4
©2002 Fairchild Semiconductor Corporation IRF530 Rev. B1
 IRF530

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25 1500
ID = 250µA VGS = 0V, f = 1MHz
NORMALIZED DRAIN TO SOURCE

CISS = CGS + CGD

1.15 1200 CRSS = CGD
BREAKDOWN VOLTAGE

COSS ≈ CDS + CGD

C, CAPACITANCE (pF)
1.05 900

CISS
0.95 600

0.85 300 COSS

CRSS
0.75 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180 1 10 102
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

10 100
PULSE DURATION = 80µs PULSE DURATION = 80µs
ISD, SOURCE TO DRAIN CURRENT (A)
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
VDS ≥ 50V
gfs, TRANSCONDUCTANCE (S)

8 25oC

10
6
175oC

4 175oC 25oC
1

0 0.1
0 5 10 15 20 25 0 0.4 0.8 1.2 1.6 2.0
I D , DRAIN CURRENT (A) VSD , SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20
ID = 14A

VDS = 50V
VGS, GATE TO SOURCE (V)

16
VDS = 20V

12
VDS = 80V
8

0
0 6 12 18 24 30
QG , GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

5
©2002 Fairchild Semiconductor Corporation IRF530 Rev. B1
 IRF530

Test Circuits and Waveforms

VDS
BVDSS

tP
L VDS
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS 0

0.01Ω tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
VDS
90% 90%
RL

+ 10% 10%
VDD 0
RG
-
90%
DUT
VGS 50% 50%
PULSE WIDTH
10%
0
VGS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

VDS
CURRENT (ISOLATED
REGULATOR SUPPLY) VDD

Qg(TOT)
SAME TYPE VGS
12V AS DUT Qgd
0.2µF 50kΩ
BATTERY Qgs
0.3µF

D VDS

G DUT 0

Ig(REF) S
0 IG(REF)
VDS
IG CURRENT ID CURRENT
SAMPLING SAMPLING 0
RESISTOR RESISTOR

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

6
©2002 Fairchild Semiconductor Corporation IRF530 Rev. B1
TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™ FASTr™ PACMAN™ SuperSOT™-3
Bottomless™ FRFET™ POP™ SuperSOT™-6
CoolFET™ GlobalOptoisolator™ Power247™ SuperSOT™-8
CROSSVOLT™ GTO™ PowerTrench® SyncFET™
DenseTrench™ HiSeC™ QFET™ TinyLogic™
DOME™ ISOPLANAR™ QS™ TruTranslation™
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E2CMOS™ MicroFET™ Quiet Series™ UltraFET®
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FAST® OPTOPLANAR™ Stealth™
STAR*POWER is used under license

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PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In This datasheet contains the design specifications for
Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4
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