2016 IEEE Region 10 Symposium (TENSYMP), Bali, Indonesia

Optimum selection of Inductor as a current limiter in

AC power systems
Dr. Swati Devabhaktuni1, Dr. Hari Shankar Jain2, Kiran Kumar Pamera3
Department of Electrical and Electronics Engineering
Vardhaman College of Engineering, Hyderabad-501218 (India)
swatikjm@gmail.com1

Abstract— Current limiting reactors, CLR, are introduced in
power networks to limit short circuit levels. The inductance of
the size of the current limiting reactor is based line capacity and
inductance. This paper discusses statistical route to optimize
design margin available. With a view to assign a statistical rating
to the inductor, simulations have been conducted with 100
randomly selected switching instants and fault introduced at
10% of the line length. The switching instants have been
distributed over half period (10ms) of a 50Hz AC cycle.
Statistical mean and standard deviation are arrived based on
these results and minimum and maximum short circuit current
for one standard deviation are considered as optimal statistical
ratings for the system, covering faults in this range.
The PSCAD and MATLab based simulations are carried out to
for this study which suggests practical and cost effective
approach for selection of such Current Limiting Reactors (CLR).
Keywords—Current Limiter, Circuit Breaker, Short Circuit,
Current Limiting Reactor (CLR), Rate of rise of fault current,
Power semiconductor, Power systems , Statistical mean and
deviation etc
I. INTRODUCTION
The short circuits are main cause of concern in AC power
systems. High current flows through the system, in event of a
short circuit demanding high short circuit rating of the circuit
breakers and other system components to ensure system
reliability. Incorporating high current rated equipment/ system
components makes the system costlier.
only for brief short circuit period. The authors have suggested
an optimal location, near source, to cover all line faults. In a
different work, ref. [4] use of Current Limiting Capacitive
Reactor (CLCR) is similarly discussed for such applications.
The techno-economic comparison of two current limiting
reactance is discussed in ref.[5], concluding that the selection
shall be application/requirement specific.
While it is important that, an optimally sized current limiting
reactance need to be introduced in the system for controlling
the fault current for the duration of the fault. For lower
probability of peak short circuits, the current rating of this
equipment may or may not be necessarily equivalent to the
peak short circuit rating of the power system. The system
designers may reliably assign a practical or a statistical rating
to economize on capital costs of the power system.
This paper focuses and suggests method to determine such
statistical rating for reducing the overall cost of the system,
by selecting a statistical optimum rating for the current
limiting element. To determine probable short circuit currents
authors have used PSCAD simulation and a 200kM
transmission line model with system parameters of
220kV/1000MW. The optimal rating of the inductor is
calculated using an iterative MATLab code.
II. SYSTEM MODEL

Several methods have been investigated and reported in the
literature to contain power system short circuit currents. The
method proposed in ref. [1-3] suggests an additional, in
circuit, inductive reactance as a current limiter. Although
placing a series inductor in the circuit provides necessary
control, wrong location of this Current Limiting Reactor
(CLR) would nullify the effort. In ref. [1] optimal location are
considered and experimented in Brazilian power systems.
Identically in ref. [2] appropriate placement of CLRs to reduce
the fault currents is discussed for different arrangements of
HV substations.
To suggest the optimum value of the CLR a simulation model
has been prepared and experiments conducted with the help of
PSCAD Ver-4.6. The elements considered for the simulation
included a Master breaker, a CLR, an Auxiliary breaker for
CLR, the fault initiation CB and the Load. The considered
system model and single line diagram, SLD, is as shown in the
Fig.1

An intermittent or fault specific placement of CLRs has been

suggested and discussed in ref. [3] to retain line capacity and
to control short circuit levels. In this work a bypass circuit
breaker (auxiliary CB) is suggested across the current limiting
reactor during normal operations. The reactor is introduced Figure 1 SLD for the modeled system

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 2016 IEEE Region 10 Symposium (TENSYMP), Bali, Indonesia

In Figure.1, an inductor is used as a current limiter in series The PSCAD Model, consisting of various circuit elements and
with the transmission line. An auxiliary breaker is connected the fault switch is as shown in Figure.3.
in parallel with the current limiter. When there is no fault in
the system auxiliary CB is closed bypassing the CLR. When
the fault is introduced into the system the over current sensor
senses the fault triggering the auxiliary CB to open. Open
status of auxiliary CB introduces CLR in series with
transmission line. This activity is carried out with in nearly
10ms (1/2 cycle). The master breaker opens at appropriate
time (2-3 Cycles).

The system impedance is given by:

(1) Figure.3 PSCAD MODEL for CLR Scheme.

Where, Z=System impedance; R= Resistance of the system;

X = generator inductance and X = CLR impedance
For Generator voltage, Vg , the reduced fault current is thus
given by:
Simulation results with and without CLR for various fault
location (% of line length from source) are shown graphically
in Figure. 4.

(2)

The phasor diagram of the CLR system is as shown in the

Figure.2.

Figure 2 Phasor Diagram

Figure 4 Simulation results, with and without CLR.

A trip signal for master circuit breaker is normally generated
by the protection scheme during faults. In this scheme the
protection system generates two trip signals adequately timed
so as to cause tripping of auxiliary breaker prior to master
breaker. For efficient control use of Solid state auxiliary
circuit breaker, power semiconductors, is encouraged to
expedite opening, operating times within 1/4th cycle.
For this simulation model, the source impedance parameters
are assumed as 10% of the load parameters. CLR is taken as
20% of the load parameters. Line capacitance of 10.45 micro-
farads is also included. The system parameters/kM, calculated
and used for the model are tabulated below, in Table.1.
Above results demonstrate benefits of using CLR, as with
CLR the rate of rise of current decreases appreciably,
confirming stable system operation under fault conditions.
Conventionally designed CLR having short time current rating
equivalent of assigned system fault ratings (e.g., 40kA, 50kA,
63kA etc.), the cost of the AC power system is bound to be
higher, while the statistical chances of attending this fault
level would be very small (about 2%) during the life of the
system. To maximize the usage and to optimize the CLR
costs, following method is proposed in this paper.

Table 1 Transmission Line parameters

III. SOLUTION

ELEMENT Rs Ls C As the fault initiation are likely to be random in nature for

both the fault location and event of fault. Random fault
Transmission Line 3.6801 0.096 10.45 initiation instants have been chosen in the study along with
Load 48.4 0.115 -
three different fault locations. Through PSCAD software
simulation for 100 random values of the fault, times in
Source 4.84 0.012 - between 0.1 - 0.11sec, have been chosen and experimented.

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 2016 IEEE Region 10 Symposium (TENSYMP), Bali, Indonesia

Peak Fault Current and average rate- of- rise of currents are
recorded. Peak currents and frequency of occurrence for a
peak current are plotted.
IV. RESULTS AND DISCUSSIONS
Using the equations (1) and (2), the optimum value of the
reactance calculated for the line is 3.45Ω. Table.2 indicates
the effect of the optimum CLR on peak fault current in the
system.

Table 2 Comparison between currents with and without CLR

Simulation
Current (kAp)
Condition
Without
41.872
CLR
With CLR 30.2
Figure 5 Peak current v/s frequency of occurrences.

It is importantly observed during these experiments that for

Simulations have been repeated using optimal parameter of
considered 40kA system, the peak currents recorded were
CLR at 10% of the length of the transmission line to predict
always below 40kA. It has been found that the range of the
the support available from the proposed scheme. The current
fault current for these 100 experiments lies between 3.98kA to
waveform at the optimum value of CLR is shown in Figure.7.
37.884kA. The recorded data has been analyzed with the help
The fault is simulated for 5 Cycles, 0.1 to 0.2msec here.
of MATLab and a histogram has been generated, Figure.5.

Statistical analysis of the simulation results show the mean

and the standard deviation for the random switching
experiments without CLR are 23.16kA and 11.04kA,
respectively, Figure.6.

Figure 7 Current waveforms during short circuits.

Reduced rate- of- rise of fault current reduces the mechanical

stress on system components and the Circuit breakers, also
increases the insulation life of the entire system. The variation
of the rate- of- rise of current with CLR and without CLR is as
Figure 6 Statistical distributions of peak currents during random shown in Figure.8.
switching.

The mean value in such distribution refers to the location of

parameter of highest occurrence. The standard deviation on
other hand describes the fringes and lower probability
occurrences. The area enclosed by the limits µ-3σ and µ+3σ is
very close to unity which means that the probability of
occurrence beyond these limits are very small and can be
neglected for all practical situations. It is observed, and is
proven through this study that assigned 40kA fault levels are
not reached in simulation although theoretically the system
has a limit of 40kA. As the maximum hazard values are
covered in the area between µ-σ and µ+σ the optimum value Figure 8 Estimated Rate of Rise of fault currents.
of the inductor for the considered system shall be 30.2kA,
instead of 40.0kA for a system with CLR. This current rating As highest occurrence observed during experiments with CLR
is the recommended statistical-optimum for the CLR. is at 20.9kA, 30.2kA rated equipment (with one sigma margin)
is most appropriate for considered application having 40kA as
assigned system rating.

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 2016 IEEE Region 10 Symposium (TENSYMP), Bali, Indonesia

V. CONCLUSIONS research findings are published in more than 25 research papers. She was a
member in IEEE and MIE in IE(India) .

In this work the statistical optimum current rating for a series
current limiting reactance is determined and suggested using
sizable number of random samples. Authors find that
reduction up to 25% in current rating of the equipment is
possible and safe. Experiments conducted using PSCAD
simulations are able to accurately determine fault currents for
various system conditions.
Future work envisaged, include experimental verification of
the predictions, work relating to use of power semiconductor
devices for auxiliary breakers and fast (¼ cycle) micro-
controller based protection schemes.
Hari Shankar Jain completed his graduation in
electrical engineering from Madhav Institute of
Technology and Science (Jiwaji University, Gwalior)
and doctorate in electrical engineering from Indian
Institute of Technology, Bombay. He joined BHEL in
year 1974 and retired on superannuation in 2012 as
ED R&D. At present he is Dean (Research &
Development) at Vardhaman College of Engineering
at Hyderabad. He has published more than 25 papers in national and
international journals and has equal number of patents to his credit. He has
been conferred the National Design Award-2003 by National Design and
Research forum(NDRF) for his contribution in indigenizing the gas insulated
substation for the country and has secured gold medal for excellence in
technical writing from BHEL. He is a senior member of IEEE and has
represented India on CIGRE committee on electrical materials (SC-D1).

Kiran Kumar Pamera is pursuing Post Graduation

VI. ACKNOWLEDGEMENTS from Geethanjali College of engineering and technology
with specialization in POWER ELECTRONICS. He has
completed graduation from Vardhaman College of
The Authors are thankful to the Management of Vardhaman Engineering in ELECTRICAL ELECTRONICS
ENGINEERING. Presently he is working as a Junior
College of Engineering, Hyderabad for their kind permission Research Fellow in Department of EEE at Vardhaman
to publish this work. They also extend their grateful thanks to College of Engineering, Hyderabad (TS).
the staff of EEE department for their support in simulation and
processing of this work.

VII. REFERENCES

[1] J.Amon F,P.C.Fernandez, E.H.Rose,A.D´Ajuz,A.Castanheira, “Brazilian

Successful Experience in the Usage of Current Limiting Reactors
forShort- Circuit Limitation”,Technical Colloquium.
[2] HereshSeyedi, BarzanTabei,” Appropriate Placement of Fault Current
Limiting Reactors in Different HV Substation Arrangements”, Circuits
and Systems, 2012, 3, 252-262
[3] Swati Devabhaktuni, H.S. Jain,P.Kiran Kumar,”Current Limiting
Reactor support to retain short circuit ratings of Circuit Breakers and the
Power Systems”,SWITCHCON-2016,P.N0- 164-168.
[4] Swati Devabhaktuni, H.S. Jain,P.Kiran Kumar,”A study on RC element
based current limiter in AC Power Systems”, 978-1-4673-9939-
5/16/$31.00 ©2016 IEEE,Pg.No:3172-3176.
[5] Swati Devabhaktuni,H.S.Jain,P. Kiran Kumar,”A Comparitive study of
CLR and CLCR as Current Limiters in AC Power Systems”,IEEE-
International Conference On Computation Of Power,
Energy,Information And Communication– 2016.
[6] Swati Devabhaktuni, H.S.Jain, V.Pramod Kumar, “Retrofitting and
upgradation of EHV substations and transmission lines : A review of
control, protection & communication systems”,IEI-All india seminar on
retrofitting- 2016, pp 8-13.

VIII. AUTHORS

Swati Devabhaktuni is a Professor in the

department of electrical and electronics Engineering.
She is a member of R&D team and at Vardhaman
College of Engineering. She has been awarded PhD
from JNTU, Hyderabad. Dr. Swati has a passion for
teaching. She has been teaching both PG and UG
courses for the last 12 years. She has authored one
textbook and published five conference proceedings. In addition to teaching,
Dr. Swati has been actively doing research on solar cells, power systems. Her

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