Inverter Fault-Identification for
VSI Motor Drives
A. Gaeta, G. Scarcella, G. Scelba, S. De Caro, A. Testa
Φ
Abstract – The paper presents an identification procedure
able to detect open circuit failures in voltage source inverters.
The procedure is suitable to equip fault tolerant electric motor
drives and in principle only requires the measurement of the
DC link current as it accomplishes a reconstruction of the
inverter output phase currents from the DC link current
measurement, thus eliminating the need of conventional
current sensors. However, if they are present at the cost of
minimal modifications the PWM technique, response times as
short as one switching period can be obtained. Compared to
other technical solutions found on past literature, the proposed
approach considerably reduces the required computational
effort. Simulations and experimental tests are presented to
confirm the consistence of the proposed approach.
Index Terms— Current Measurement, Failure Diagnosis,
Reliability, Space Vector Pulse Width Modulation, Variable
Speed Drives.
I. INTRODUCTION
T HREE poles, six switches, Voltage Source Inverters
(VSI) are the normal equipment for three phase
electrical motor drives. However, more complex inverter
structures featuring extra power switches, or additional
poles, have been developed in the past to obtain fault
tolerant electric motor drives [1]. In these systems, a
suitable procedure is implemented, able to detect the
occurrence of a failure, to identify the damaged power
switch and the nature of the malfunctioning, as well as to
reconfigure the structure of the inverter [2]÷[6]. The
response time of the failure detection procedure is an
important aspect to ensure the required service continuity of
a reconfigurable electric motor drive and is crucial in HF
injection-based sensorless motor drives. In these last, a
power switch failure has effects not only on the motor power
supply, but also on estimation of the rotor position the
injection of the HF signal also influenced by the failure.
On standard sensored drives and open circuit failure
detection and identification can be accomplished in several
tens of milliseconds, without affecting drive operations.
On the contrary, on sensorless drives, an open circuit failure
may remarkably alter the signal injection and so the rotor
position estimation in few milliseconds, due to the high
Φ
This work was partly supported by the Project: “Optimization and
Control of Electrical Drives for Fault Tolerant and Ride-Through
Operation”, sponsored by the Italian Ministry of Education and Research,
PRIN 2008.
A. Gaeta, G. Scarcella, G. Scelba are with University of Catania, Viale
Andrea Doria 6, 95125 Italy (e-mail: alberto.gaeta@dieei.unict.it)
A. Testa S. De Caro are with University of Messina, Viale Ferdinando
Stagno D’Alcontres 31, 98166 Sant’Agata (ME) (e-mail:
testa@ingegneria.unime.it).
978-1-4244-9303-6/11/$26.00 ©2011 IEEE
413
frequency nature of the injected signals [7].
Failure detection is generally accomplished according to
measurement of the inverter phase currents or voltages,
through additional sensors. However, extra sensors increase
the cost and complexity of any motor drive for industrial
applications. A possible way to obtain information about the
phase currents through a reduced number of current sensors
is represented by a reconstruction of such currents from the
DC link current, based on the sequence of the inverter states
[8]. Only a single current sensor is therefore needed to
reconstruct the three phase currents, moreover it can be
implemented through a simple and inexpensive circuitry.
Unfortunately, this approach fails in some working
conditions. In fact, at low modulation indexes and when
two-phase voltages feature the same duty cycle an incorrect
reconstruction of the phase currents is obtained. As this
drawback largely prevents any practical application, more
sophisticated techniques have been proposed using either
special filters, modifications of PWM patterns, or state
observers [9]÷[12]. However, although they are suitable to
reconstruct the phase currents for normal control purposes,
they hardly can be exploited to detect motor or power switch
failures.
This paper proposes a failure-identification procedure able
to detect open circuit power device failures, in voltage
source inverters, by using a reduced set of current sensors. In
particular, with a single current sensor on the DC link, a
procedure able to detect open circuit failures is carried out,
suitable to equip conventional or sensored, vector controlled
industrial motor drives. Failure detection times are lower
than two switching periods, thus suitable to permit a fast
inverter structure reconfiguration and to avoid any system
shutdown, especially in case of HF injection-based
sensorless motor drives. The proposed procedure does not
require modifications of the switching patterns during the
healthy operation of the drive and can be also exploited to
reduce the number of current sensors in conventional
industrial motor drives. If compared to previously developed
approaches, the proposed technique considerably reduces the
computational effort, leading to easy and inexpensive
practical implementation.
II. OPEN CIRCUIT FAILURE DETECTION AND
IDENTIFICATION
The actual state of a three-phase inverter can be described
by a sequence of binary digits to indicate if each leg output
is connected to the higher (1) or to the lower (0) DC rail.
Considering all possible combinations, a three-phase inverter
can generate only six active voltage vectors and two zero
vectors as depicted in Fig. 1. When an inverter power device
Sx x=1,2…6 (Fig. 2), is affected by an open-circuit failure,
the real sequence of voltage vectors applied to the load can
differ from the commanded one, depending on the direction
of the current in the failed leg.
3
3
V DC
Fig. 1. Voltage space vector representation for three leg VSI.
Fig. 2. Fault Tolerant three phase VSI.
As an example, if the leg current is positive (flowing from
the inverter to the load), only the upper power device of the
leg (S1, S2 or S3) will take part to current conduction: when
the upper device is active, it will carry the leg output current,
while when inactive the current will be conducted by the
lower diode of the same leg (D2, D4 or D6); therefore, under
the hypothesis of positive leg current, the leg output voltage
is imposed by the state of the upper device of the leg.
Consequently, an open-circuit failure to the lower device (S2,
S4 or S6) will not affect the inverter operation as long as the
leg output current will remain positive.
Obviously, the occurrence of a failure of the upper power
device, when the leg output current is positive, will cause the
current to be carried by the lower diode of the leg,
independently of the gate signals. The failed leg output
voltage will be tied to the lower dc bus rail, causing the
positive leg current to suddenly decrease up to zero if no
action is rapidly taken [12].
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Similar considerations can be applied to the case of a
negative leg current. In fact, as soon as the leg current is
negative, only the lower device and the upper diode of the
leg take part to the current conduction, and an open-circuit
failure to the upper device will not alter normal operation.
On the other hand, a failure of the lower device will connect
the output of the affected leg to the higher dc rail,
compromising the capability of the leg to generate a
modulated voltage and causing the negative leg current to
suddenly increase.
A) Failure Detection
For a wye connected system, like that shown in Fig. 2, in
normal operations, the DC link current is zero during
inverter zero states (S1-S3-S5 or S2-S4-S6), because all the
phases are short-circuited each other. However, under open
circuit failure conditions, the DC-link current is not zero
during a commanded zero state, because the actual state of
the inverter is rather an active state. As shown in Fig. 3, in
case of a failure of an upper device, the state of the failed leg
is (0) while is (1) if the failed device is the lower one.
Healthy System
Fig. 3. Failure on S3: CH1) VaN [100V/div.], CH2) VbN [100V/div.], CH3)
VcN [100V/div.], CH4) iDC [0.5A/div.], Time [20µs/div.].
In particular, a unique output current combination
corresponds to each state of the inverter represented in Fig.
1. These combinations can be detected through a measure of
the DC link current. During a commanded zero state, the
faulty DC-link current is equal to minus the absolute value
of the current in the affected leg. In this way, by measuring
the DC link current and using a threshold comparator, it is
possible to detect an open-circuit failure of the upper devices
(S1-S3-S5) during a commanded (111) state or of the lower
devices (S2-S4-S6) during a (000) state. The threshold should
be suitably selected in order to avoid false detections, due to
the presence of an unavoidable minimal DC-link currents,
common mode currents, sensor noises, etc [3]. In addition,
the DC-link measurement can be used to detect inverter earth
faults according to [2]. The DC-link current measured during
a commanded zero state will be always positive in case of
earth leakage currents, while it will be negative in case of an
open-circuit fault.
In the following, it is assumed that in the inverter a power
device is affected by an-open-circuit failure only if it is
conducting current, or in the previous PWM period Ts it has (010), (001) in case of failure of one of the upper devices, or
been conducting current. Moreover, the analysis neglects the the sequence (011), (101), (110) in case of failure of a lower
case of multiple contemporary faults and diode failures as device as described in TABLE II.
well. The failure detection time may vary depending on the For example, if S3 is the failed device, the DC-link
particular modulation strategy used. In particular, if a current, measured during commanded (010) state, should be
symmetric PWM switching pattern is used, the maximum below the threshold because the actual inverter state is (000)
delay time is equal to two PWM sampling periods. Such a and the state of the affected leg is (0), independently of its
value is obtained as the worst case occurring when an open gate signals. However, such a procedure is incomplete
circuit failure happens just after the end of a zero state DC- because the absolute value of the measured DC link current
link current measurement. This delay can be reduced by during an active test state, can fall below the threshold even
using an asymmetric PWM switching pattern, as the adjacent if the power device under test is not damaged. It must be
zero states modulation shown in TABLE I. This strategy emphasized that, after that a failure has occurred, sudden
allows to reduce the detection delay to one sampling period, variations will appear also on the output currents of the
at expenses of increased switching losses, due to the healthy legs, as represented in Fig. 4. Such variations will
additional commutations required. increase/decrease the amplitude of the healthy currents,
which have equal/opposite sign respect to the faulty current.
Table I TABLE I: Switching pattern of the adopted SVM technique Therefore, during the unavoidable time delay required by
fault identification, healthy currents with the same sign with
Sector Switching Pattern respect to the faulty current will become larger while healthy
V1 V2 V7 V0
I currents with opposite sign will become smaller, making the
(100) (110) (111) (000)
identification procedure more difficult. A critical situation
V3 V2 V7 V0
II
(010) (110) (111) (000)
arises when two measured DC-link current are below the
V3 V4 V7 V0
identification threshold, and cannot be solved just applying
III small duration active state tests. A possible solution could be
(010) (011) (111) (000)
V5 V4 V7 V0 to prolong the duration of each active test state until a
IV possible fault is identified. The time duration enlargement
(001) (011) (111) (000)
V5 V6 V7 V0 should allow current amplitude to increase up to exceed the
V detection threshold if the device is not failed. In this way a
(001) (101) (111) (000)
V1 V6 V7 V0 second DC- link current measurement, performed at the end
VI
(100) (101) (111) (000) of the longer active test state, will eliminate any uncertainty.
The main disadvantage of this approach is that each an
If a continuous failure monitoring is required, a third limit enlarged active test state should last more than:
is that both zero states must be present in each PWM period
and with a time duration sufficiently high to allow a correct tenlarged >= 2*Threshold*(3*L/2)/VDC
DC-link current measurement. In fact, each zero state should
last at least: tmin = td + tacq where tacq is the time required by where VDC is the DC-bus voltage and L represents the
current sampling and td is the time delay required to allow inductive component of the load.
the DC-link current settling [1], [2]. This limits the An alternative solution is to exploit the presence of
maximum fundamental amplitude of the motor voltages to redundant hardware, used for inverter reconfiguration after a
(1-2*tmin/Ts)Vsmax. Moreover, if an open-circuit fault happens fault, in order to retrieve additional information useful for
when the current direction in the leg makes the inverter fault identification. As an example, assuming the availability
operating normally, the fault detection is not effective. of a fourth leg connected to each of the inverter output by
However, if the inverter is properly designed and assembled, means of three couples of anti-paralleled GTO, as
the possibility that a power device fails while it does not represented in Fig. 2, after a possible fault identification, the
carry any current, is very low. These considerations apply to active state is extended using the following sequence:
the power section (gate drivers, power devices) of the - both gate signals of the leg under test are set to the low
inverter. In addition, unforeseen open-circuit state of power logic level, thus disabling the leg;
devices can also be caused by failures of digital components - the proper GTO couple is activated in order to connect
of the inverter. These occurrences are not necessarily related the fourth leg in parallel with the leg under test;
to current conduction across the affected device. In this case, - the same active test state is applied using the fourth leg
the fault detection can be accomplished by feeding back to instead of the leg under test.
the control unit the actual devices driving voltages, in order If the measured DC-link current exceeds the identification
to allow an immediate detection of failures of digital threshold, the power device under test is the failed one,
components. otherwise, the device is healthy and the current in the leg
under test is physiologically below the threshold. If a fast
B) Failure Identification fault detection and identification is mandatory, long active
After that a failure has been detected a failure test states may be avoided by properly exploiting the
identification procedure must be performed, to identify the information regarding the inverter output currents. If the
failed device. A straightforward method to identify the failed amplitude and sign of the inverter output currents are known,
device is to apply the additional active states sequence (100), it is possible to predict which fault can be detected.

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 Table II
Additional
Fault Phase currents Detectable Faults Fault Detection Fault identification
states
(ia>imin,ib<imin,ic<imin) S1 After (111) state
Contemporary with fault
(S1, S3, S5) (ia<imin,ib>imin,ic<imin) S3 current Not required
detection
(ia<imin,ib<imin,ic>imin) S5 measurement
(ia>imin,ib>imin,ic<imin) S1,S3 After (111) state (100),(010) S1 after (100) curr. meas.
(S1, S3, S5) (ia>imin,ib<imin,ic>imin) S1,S5 current (100),(001) S3 after (010) curr. meas.
(ia<imin,ib>imin,ic>imin) S3,S5 measurement (010),(001) S5 after (001) curr. meas.
(ia<-imin,ib>-imin,ic>-imin) S2 After (000) state
Contemporary with fault
(S2, S4, S6) (ia>-imin,ib<-imin,ic>-imin) S4 current Not required
detection
(ia>-imin,ib>-imin,ic<-imin) S6 measurement
(ia<-imin,ib<-imin,ic>-imin) S2,S4 After (000) state (011),(101) S2 after (011) curr. meas.
(S2, S4, S6) (ia<-imin,ib>-imin,ic<-imin) S2,S6 current (011),(110) S4 after (101) curr. meas.
(ia>-imin,ib<-imin,ic<-imin) S4,S6 measurement (101),(110) S6 after (110) curr. meas.

Fig. 4. Fault detection and identification at the same time. Fig. 6. Fault detection and identification using two additional test states.

As a consequence, it is possible to eliminate the
uncertainties of the fault identification procedure and to
reduce the number of the required active test states from
three to one, as shown in Fig. 5, to two, (Fig. 6), or even to
zero (Fig. 4). For example, if a fault to an upper power
device has been detected, only legs with sufficiently large
positive currents may be affected by the fault. Therefore legs
with small or negative currents, which are responsible for
indeterminations of the fault identification procedure, can be
immediately excluded before applying the active states test.
By supposing that a fault to an upper power device is
detected, if the two leg currents are positive and sufficiently
large, only two active states are required to properly identify
the failed device (Fig. 6).
Fig. 5. Fault detection and identification using one additional test state.
If the failed device is identified when the first active test
state is applied, the identification procedure is stopped (Fig.
5). If only one leg current meets the above criteria, the
identification procedure is not necessary, because only one
leg may have caused the fault detection and the fault can be
immediately identified when detected (Fig. 4). By
considering that, in the case of wye connected load, it is not
possible that all the three currents have contemporary the
same sign, it is clear that applying three active test states for
fault identification is a waste of time, if the inverter output
current information is available.
III. PHASE CURRENTS RECONSTRUCTION FROM
DC-LINK SENSOR
Information about the inverter output currents can be
obtained by using additional current sensors or can be
reconstructed using the same DC-link sensor required for
fault detection and identification. In the latter case, in order
to assure a continuous output currents reconstruction, each
active state within a PWM period should last enough time to
allow proper active state current measurement. Two phase
currents can be measured in each Ts, and the third can be
calculated by using the constraint imposed by the wye load
connection. Such measurement are used in the control only
at the end of the next zero state (000), in order to discard any
possible wrong measurement due to the fault, as shown in
Fig. 7. Time duration of the active states become small when
the reference output voltage vector is located near the origin

416
of the state space plane of Fig 1, or when it is near to the the start-up of the machine. The results indicated in Figs. 9
boundary between two adjacent sectors. In the first case both and 10 show the behavior of the drive when an open circuit
the active vectors that are used to synthesize the reference fault occurs in S1, and when ias>0, ibs<0,and ics>0. As it is
vector, are too small to allow a correct DC-link current possible to note in Fig. 9, the fault situation occurs during
measurement, while in the second case only one of the active the inverter state (1,1,1), after the currents measurement.
vectors is too small. The system is not aware of the fault till the (1,1,1) inverter
state is again applied. In fact, a DC-link current higher than
the detection threshold is detected only in the latter state.
TABLE III: VSI Motor Drive Data
Rated Power 20HP Lm 0.076
Rated Voltage 460V J 0.1kgm2
Rated Frequency 60Hz F 0.02Nms
Rated Speed 1760 rpm Pole Pairs 2
Rs 0.2761Ÿ DC bus Voltage 796 V
Lls 0.0022 H Switching Frequency 10kHz
Llr’ 0.0022 H Dead Time 1µs

Since two power devices in the upper side of the inverter

are conducting contemporary, additional inverter states are
Fig. 7. Phase current reconstruction time sequence. necessary to identify which of these devices is failed. The
In this paper, in order to allow a continuous phase current first additional state (1,0,0) provides the solution because
reconstruction from the DC-link current measurement, active during this state the DC link current is zero. When the failed
vectors that are not enough long are suitably extended to device is identified, the inverter is reconfigured in order to
allow a proper current measurement. The distortion of the disable the broken leg and restoring the functionality of the
reference voltage, caused by such a modification of the drive.
switching pattern, is compensated by applying the
complementary active state. This is, referring to Fig.1, the
active state which has same direction but different sign, as
shown in Fig. 8. From the inverter output voltage point of
view, the increment of the duration of the active state and the
introduction of the complementary state is equivalent to the
application of a zero state. Consequently, the full ability in
reconstructing the phase current using the DC-link sensor is
obtained at the expenses of a reduced maximum inverter
output voltage.

Fig. 9. Current measurements and phase currents update.

The effects of this transient on the motor variables are

Fig. 8. Fault detection and identification using two additional test states.
IV. SIMULATION RESULTS
The digital behavior of the fault identification procedure
has been tested by means of numerical simulations. In
particular, the proposed method was applied to a three-phase
fault tolerant VSI motor drive using the same topology of
Fig. 2, main technical characteristics are indicated in Tab.III.
The effectiveness of the method has been evaluated during
displayed in Fig. 10. Since the identification procedure lasts
less than Ts, a limited influence on the machine operation is
observed. As shown in Fig. 11, a similar analysis has been
conducted in case of an open circuit fault occurring in S5.
Differently from previous case, here the fault identification
time is increased due to the use of a second additional test
state to identify the failed device. Being S5 the failed device,
the first additional test state only confirm that S1 is not
affected by a fault. Even in this condition, the power system
is rapidly reconfigured after fault identification, and the
effects on the machine are displayed in Fig. 12.

417
 after a fault, correctly detected by the developed procedure,
is performed without any change in the motor current and
assuring the continuity of drive operations.

Fig. 10. Current measurements and phase currents update.

Fig. 13 Operation before fault: CH1) ia at motor terminal[1 A/div.], CH2) ia

at inverter terminal [1 A/div.], CH3) id [1 A/div.], Time [10ms/div.].

Fig. 11. Current measurements and phase currents update.

Fig. 14 Operation after a fault to A-leg, (A-leg gate signals disabled and
freewheeling diodes healthy): CH1) ia at motor terminal[1 A/div.], CH2) ia
at inverter terminal [1 A/div.], CH3) id [1 A/div.], Time [10ms/div.].

Fig. 12. Current measurements and phase currents update.

V. EXPERIMENTAL RESULTS
The proposed procedure has been experimentally tested,
using a three-phase VSI motor drive topology with the
characteristics of the system used for the simulations. Figs.
Fig. 15 Operation after a fault to A-leg, (A-leg gate signals disabled and
13-16 show the behavior of the system before and after a freewheeling diodes healthy): CH1) ia at motor terminal[1 A/div.], CH2) ia
switch fault. As it is possible to see the voltage modulation at inverter terminal [1 A/div.], CH3) id [1 A/div.], Time [10ms/div.].

418

Fig. 16 Fault transient on leg A, (A-leg gate signals disabled and free-
wheeling diodes healthy): CH1) ia at motor terminal[1 A/div.], CH2) ia at
inverter terminal [1 A/div.], CH3) id [1 A/div.], CH4) TRIAC1 signal
[5V/div.], Time [10ms/div.].
VI. CONCLUSIONS
With the aim to improve the fault tolerant capability of
electrical motor drives, this paper has presented a new
technique able to detect and identify open circuit faults of
the power devices in VSIs. According to the proposed
method, standard current sensors can be eliminated and
response time of failures identification is greatly reduced.
Furthermore, compared to other failure-identification
solutions, the proposed approach reduces the computational
efforts. Simulations and experimental tests are presented to
confirm the consistence of the proposed approach.
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VIII. BIOGRAPHIES
Alberto Gaeta was born in Lentini (SR), Italy, in 1980. He received the
M.S. degree in electronic engineering from the University of Catania, Italy,
in 2008. He is working on his Ph.D. in Electrical Engineering through
collaboration with CePTIT of Misterbianco (CT) and with Dept. of
Electrical Electronics and Systems Engineering of University of Catania.
His fields of interest are electric machinery and electric drives with
particular attention to the research and optimization of sensorless control
techniques.
Giuseppe Scarcella received the M.S. degree in 1995 and the Ph.D. degree
in 1998 both in electrical engineering from the University of Catania.
During 1998, he was Visiting Researcher at the University of Wisconsin,
Madison. Since 1999 he is at the University of Catania where, currently, he
is an Associate Professor in the areas of electrical machines, power
electronics and drives. He has authored or co-authored over 100 technical
papers and three patents. He has achieved two IEEE awards, respectively
obtained in the year 2000 for the best paper published in the IEEE
Transactions on Power Electronics, and in 1998 as the third prize paper
presented at the IEEE-IAS Annual Meeting. Both papers were on sensorless
control of ac motor drives. His research interests include sensorless control
of electrical drives, digital modulation techniques, and electromagnetic
compatibility.
Giacomo Scelba was born in Caltagirone (CT), on January 1, 1976. He
received the M.S. and Ph.D. degrees in electrical engineering from the
University of Catania, Catania, Italy, in 2002 and 2005, respectively. In
2004, he was a Visiting Student at Rockwell Automation Standard Drives
Development, Mayfield Heights, OH. He is currently a Researcher in the
Department of Electric, Electronic Engineering and Computer Science,
University of Catania. His current research interests include sensorless
control, digital signal processing, and ac drive control technologies.
Salvatore De Caro was born in Frankfurt am Main, Germany. He received
the M.S. degree in electronic engineering from the University of Messina,
Messina, Italy, in 2000, and the Ph.D. degree in electrical engineering from
the University of Catania, Catania, Italy, in 2004. He is currently a
researcher in the area of power electronics at the University of Messina. His
major research interests include power converters, power devices, and EMI.
Antonio Testa was born in Catania, Italy, in 1962. He received the Degree
in electrical engineering from the University of Catania, Catania, Italy, in
1988. During 1989–1990, he was the recipient of an SGS-Thomson Grant.
From 1990 to 1998, he was an Assistant Professor of Electrical Drives and
Power Electronics in the Department of Electrical, Electronic, and Systems
Engineering, University of Catania. He is currently a Professor of Electric
Machines and Power Electronics at the University of Messina, Messina,
Italy. During 1991, he was a Visiting Researcher at the University of
Wisconsin, Madison. His major research interests are in the fields of
sensorless control of electrical drives, advanced digital control systems,
power converters, power devices, and electromagnetic compatibility.