SRN PES University, Bangalore UE14EC303 PES (Established under Kamataka Act No. 16 of 2013) December 2016: END SEMESTER ASSESSMENT (ESA) B.TECH. V SEMESTER UE14EC303- VLSI Design If the Boolean function of a complex gate is X = (4+ B)C + DEF (GH +1) then ) Write the circuit diagram using CMOS to implement the expression given above Time: 3 Hrs ‘Answer All Questions Max Marks: 100 )] Waite the Threshold Voltage (Va) expression (NMOS or PMOS). Write all the | 05 parameters involved in Va calculation along with default value (if applicable). Determine pullup to pulldown ratio (ZpwZpd) for an NMOS Inverter driven by another | 05 nMOS Inverter. Inverter is constructed using enhancement driver and depletion load nMOSFET. y | Caleulate Ip and Vps for Vip= -1V, pnCox=200A/V? for the below shown circuit | 05 structure. The value 200 represents resistance in ohm i.e., R=200 ohm. bv 4.5V Vo 200 ) | Titustrate enhancement NMOS transistor operation using relevant diagrams with standard | 5 layer encoding and mention the voltage conditions. @) | Write the symbolic diagram of 1 bit CMOS Shift Register Cell. 05 ) | Explain al types of contact cuts with respect to their requirement in layout. Write lambda | 0° based design rules for contact cut used for metall to poly or metall to diffusion layer. ) | For the function F=aeb-+e write the stick diagram (only monochrome). 05 @ | Explain the fabrication of enhancement NMOS transistor with relevant figures using 05 standard encoding for layers. ) | Explain the following 05 1. Need for Scaling 2. Scaling models 1 | Find the scaling factors for the below mentioned parameters for combined (in terms of a, | 05 8) scaling model. Write all the steps required to arrive at the final scaling factor . 1. Saturation current 2. Switching Energy 3._Power dissipation per unit area Define the standard unit of delay t using the concept of sheet resistance and standard | 05 unit of capacitance. Write the expression for +. Evaluate the value of for Sum, 2 um, 1.2 um technologies using the table given at the end. i) 05SRN [ ii) If the output of the above complex gate ie., X is driving a load of 20Cg units, what will be the worst-case rising delay and falling delay in t units? Assume that all NMOS and PMOS transistors are of same size . consider the resistance of PMOS channel (Rp ) is 2 times of the resistance of NMOS channel (Rn). 2) ‘Explain Dynamic Manchester carry chain circuit for 4 Dit addition with relevant circuit. 05 b) Explain area / floor plan optimization with a relevant diagram showing the proper placement of components in array multiplier °) ‘Write Carry Save Adder addition flow/block diagram using 3:2 reduction and 7:2 reduction. Give an example for 3:2 carry save addition. 05 ® Explain Baugh-Wooley Multiplier with relevant expression and example. a) Explain Funnel Shifter operation using Pass transistor based circuit and table showing the operation and offset. 05 b) Explain operation of ‘C’MOS based static and dynamic latches with circuit diagram. 05 °) 1) What is the minimum clock period at which the following circuit can be operated correctly? The parameters of the components are as follows. Inverter: tpd = 200ps, tod = 100ps, 2-input NOR: tpd = 200ps, ted = 150ps Deflop: tpeq = 200ps ted = Ops, Setup time = 300 ps, Hold time = 100 ps. meh Hees ew LS Il) The circuit can be optimized by removing the pair of inverters and connecting the Q output of the left register directly to the D input of the right register. If the clock period could be adjusted appropriately, would the optimized circuit operate correctly? If yes, explain the adjustment to the clock period that would be needed. IfNo, justify your answer. 05 Explain the Max -Delay and Min-Delay constraints with relevant expressions and waveforms with reference to Flip Flop based design. “Typ wen capacance val fr MOS es Copaciance Tee pF 10a ate vs race) Tse 2 72pm ‘Gus w damsel 4+ dm § 0 16 Go ion (ev) 1 @25 178 @2y 375 029 Pobilleen to abst 04 G1) 06 C07) 06 GOH Metal Up sbeonte 03 ors) 033 (0H) 033 aD Meal2 to esate 02 (a0 017 @@2) 017 @O) Mant 2 metal} ta @ as (0) 05 aD Mata 21 pion 03 (G75) 03 (0038) _ 03 OOH “ype het resoaces , of MOS liye for 5 yt, and Orbit 2 punt and TZ jo etasloies tae Bohm por guar Sim ‘Ors Orb 2 pm Mat 003 006 008 ison oe atvy?® oso 0s BS Side a = = Polyion 15910015930 1s900 sransistr canoe wt ax" 2x10" vane ehumel asxiot —asxiot asx tot