Tanner Tools

Tutorial

School of Engineering, Built Environment and

Information Technology
Department of Electrical, Electronic and Computer
Engineering

Microelectronics Group

Compiled by Jannes Venter

©Copyright reserved, University of Pretoria

Table of contents

INTRODUCTION 2
Introduction to the Microelectronic design and manufacturing process 2

Emphasis on software and EDA in the design process 3

Explanation of Tanner packages included as available to UP 3

GETTING STARTED 3
Installation 3

A BRIEF TUTORIAL: DESIGN OF AN ANALOGUE DIFFERENTIAL

AMPLIFIER 4
Software that is included in this tutorial 4

Introduction to S-Edit 6
Navigating the workspace 7
Setting up the S-Edit environment 7
Schematic and symbol modes 7
Creating a primitive module 7
Netlisting schematics 15

Introduction to T-Spice and W-Edit 19

Basic netlist simulation and waveform viewing 19
Tips and tricks 23

Introduction to L-Edit 24
Physical description of NMOS and PMOS devices 24
Creating the amplifier layout 25

Device extraction – L-Edit to T-Spice 32

Layout versus schematic (LVS) verification 33

Conclusion 35

AN ADVANCED TUTORIAL: DIGITAL DESIGN AND TANNER PLACE AND

ROUTE 36
Copying standard cell schematics into an S-Edit workspace 36

Writing a .tpr netlist for routing purposes 37

Using SPR in L-Edit 38

1
Introduction
Introduction to the Microelectronic design and manufacturing
process
Today is marked by a consumer driven society always pushing the limits of technology to
facilitate a lifestyle emphasizing easy of use and an always-connected philosophy. No
other field in engineering is as much under this continuous performance pressure than
solid-state circuit development and the field of microelectronics. The field of
microelectronics is the main implementation layer, where high density integration of
huge systems can be made possible.

One of the most successful technologies is CMOS, where both NMOS and PMOS
devices can be fabricated on the same die by using dual wells, or single wells within a
doped substrate. The processing steps used in standard CMOS foundries can be found in
many texts. As inputs to an IC to be fabricated, the foundry requires a layout description,
which contains the physical layout of the devices, using the applicable layers, and
basically all information necessary for them to accommodate the design in their foundry.

The design process of most CMOS microelectronic projects, which follows the same
principle in other technologies (BiCMOS, bipolar etc.), can be summarized by:
• Conceptual design on systems level (top down design of block diagrams,
MATLAB prototyping, etc.)
• Breakdown of the system into smaller subsystems
• Hand-and-paper drafts of ideas on how to realize the subsystems
• Detailed calculations for refining subsystem realizations
• Schematic capture of the subsystem design, using devices realizable in the
foundry technology, following a hierarchical approach (bottom up design)
• Netlist extraction of the schematic design to generate a SPICE netlist
• SPICE simulation of the individual subsystems, applicable interfaces (testing
loading effects) and then the system as a whole (if possible)
• Further refinement of the designs where problems/issues occurred during
simulations, followed by more simulations, until the design satisfy the set
specifications
• Creation of layout cells (hierarchical) using the parameters as set by the verified
design, which defines the devices itself. This part also includes good layout
techniques, and adherence to the requirements and rules as set by the foundry
• Post-layout simulation is then done by extracting device information from the
layout file and doing further SPICE simulation using the extracted netlist
• Layout-vs-schematic (LVS), which compares the netlist of the schematic design
to the extracted netlist of the layout of the design.
• Assessment of the results, and further refinements if required. In practice, CMOS
processes are subject to show extremities in what is called the “four process
corners”, with a typical mean. All four corners should be thoroughly simulated
and verified, as well as the typical mean (tm). (This might be limited in the
academic environment, due to time limitations)

2
Emphasis on software and EDA in the design process
This emphasis on continual development and an ever present demand for tighter
integration and higher speed forces the designer to make use of all the tools available to
shorten the design life-cycle and to efficiently and accurately prototype a concept design,
where accuracy is an important cost aspect. Fundamental to this method is the use of
computer-aided design tools, such as Cadence™, Tanner Tools™, Mentor™ and a
number of similar EDA systems. This allows a designer to almost fully design an IC, test
it and doing its layout, as well as do a number of verifications on the design, before
finally sending it off to a foundry to be prototyped on silicon. The latter is an extremely
expensive process; therefore it is advantageous to minimize the amount of “test chip”
runs that has to be done before the design is made commercially available.

One should always, however, be aware of the fact that the software will only be a
accurate as the model it is based on. Therefore, care should be taken in constructing, for
instance, a SPICE model definition for an NMOS. Luckily, this is usually supplied by the
foundry, but the designer should be aware of how an increase in number of squares drain
diffusion will influence the device behaviour, and include this information when doing
SPICE simulations. (Number of drain diffusion squares is defined, for instance, in the
device statement as NRD)

Explanation of Tanner packages included as available to UP

The Tanner Tools package available to the University of Pretoria includes:
• S-Edit, used for schematic capture and netlist generation
• T-Spice, a simulation engine based on the industry standard Berkeley SPICE3f5
• W-Edit, a waveform viewer to be used in conjunction with T-Spice
• L-Edit, a layout program used to “paint” the devices as physical geometric
features that is used to define the IC in terms of the foundry’s process layers
• LVS, a layout versus schematic program, to compare a schematic netlist to a
netlist extracted from a layout file

Getting started
Installation
Tanner EDA uses a dongle and license file method to grant access to Tanner Tools
software. The University of Pretoria owns a number of dongle supported licenses (called
local licenses), as well as a few network licenses, available from b120pc040.up.ac.za, the
network address of the license server inside CEFIM room 2-8.

Therefore, before continuing, make sure that either one of the following conditions is
satisfied:

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 • You are connected directly to UP’s internal network via wireless access or an
Ethernet network point
• You have one parallel port dongle, as well as the applicable license file (.tlu) to fit
with the dongle

The software can now be obtained via instructions given at

http://phobos.ee.up.ac.za/~subjects/files/EPR400_uE/Tanner_Installation.pdf

After a successful installation, you can now access the Tanner Tools packages either via
desktop shortcuts (if the option was chosen during installation), or via the start menu,
usually Start>Programs>Tanner EDA> …
Be sure to have your dongle installed, or that you are connected to the network.

A brief tutorial: Design of an analogue differential

amplifier
Software that is included in this tutorial
There are two directories necessary before this tutorial can be followed. The first is a
skeleton design set that was created specifically for this tutorial. The tutorial set consists
of:
Tanner_tut
¾ S-Edit
o EPR_template.sdb
¾ T-Spice
o Outputs
¾ L-Edit
o EPR_template.tdb
o ams_C35.ext
o ams_C35.xst
¾ Models
o rfdevices
ƒ tm
• modnrf.md
• modprf.md
o capacitors
ƒ tm
• caps.md
• cmim.md
• cpoly.md
• csink.md
• cstack.md
• cvar.md
• ngatecap.md
o cmos
ƒ tm

4
 • modn.md
• modp.md
• nd.md
• pd.md
o resistors
ƒ tm
• rdiffn.md
• rdiffn3.md
• rdiffp.md
• rdiffp3.md
• res.md
• rnwell.md
• rpoly2.md
• rpolyb.md
¾ Tanner_tut_models.md
¾ Tanner_tut_models_lvs.md
¾ Ams_C35_dig.lib

These include the model definitions as provided by AMS for the C35 process.

The second is a directory containing standard cell libraries and technology information
obtained from Europractice. The following tree describes its directory structure:

Ams_C35_dig
¾ doc
o ams_C35_dig.pdf
¾ l_edit
o ams_C35.ext
o ams_C35_3M.xst
o ams_C35_3M_v7.tdb
o ams_C35_3M_v8.tdb
o ams_C35_4M.xst
o ams_C35_4M_v7.tdb
o ams_C35_4M_v8.tdb
o ams_C35_dig.tdb
o README_LEDIT.txt
¾ lvs
o ams_C35_dig.map
o README_LVS.txt
o Test_all.sp
o Test_all.vdb
o Test_core.lst
o Test_core.out
o Test_core.vdb
o Test_pads.lst
o Test_pads.out

5
 o Test_pads.sp
o Test_pads.spc
o Test_pads.vdb
¾ mod
o ams_C35_dig.lib
o README_MOD.txt
¾ s_edit
o ams_C35_dig.sdb
o README_SEDIT.txt
¾ spr
o README_spr.txt
o Test_core.tdb
o Test_core.tpr
o Test_pads.tdb
o Test_pads.tpr
¾ ams_C35.txt
¾ README_dig.txt
¾ Revision_ams_C35.txt

Most of the above mentioned files that will be used will be from the Tanner_tut tree.

Introduction to S-Edit
Start S-Edit by double-clicking on Tanner_tut>S-Edit>EPR_template.sdb
If everything goes well, you will be welcomed by the following screen:

6
Navigating the workspace
The above picture shows the standard S-Edit workspace. Navigation of the workspace is
done using a combination of the keyboard and mouse. In the bottom left of the screen, the
selected tool mode is shown (for instance, in wire mode, the pointer gains the ability to
draw wires), with a description of the three mouse buttons (left, middle and right) just
above. In the above case, the pointer acts as a tool in selection mode, with the left mouse
button used to select areas on the workspace, the middle button used to move selected
objects around, and the right mouse button serving the same purpose as the left.

The whole workspace can be panned left, right, up and down by using the cursor keys.
The crosshair sits at the midpoint of the workspace, and is used as an anchor in some
cases (as will become apparent later on). Zooming in and out is done by using the + and –
keys.

To the left of the workspace is a toolbar containing different tool mode settings. The top
toolbar also contains a number of functions. For a detailed description of these, see the S-
Edit manual accompanying the software.

Setting up the S-Edit environment

To make the environment easier to use, it can be customized by setting a few parameters.
This is done by selecting Setup>… from the overhead menus. Colours, Environment,
Grid, Selection and Probing options are available. Some settings are shown below.

By setting up the S-Edit environment, one can customize the look, feel and behavior of
the workspace.

Schematic and symbol modes

Parts in S-Edit are called modules. Each module consists of a schematic part and a
symbol part, representing the schematic. If no schematic is defined, the module is called a
primitive. In the given .sdb (S-Edit database) file, there are a number of modules already
defined. But to get the idea, let us define an rf NMOS device.

Creating a primitive module

Select Module>New… The following box will appear:

7
In the Module Name box, type RFNMOS. This defines the name the module will be
using when instancing it. Optionally, the Author, Organization and Information boxes
may be filled in.

The following screen should appear:

Note the content inside the red circle. This basically states that in EPR_template, the
module RFNMOS is currently open for editing in Schematic mode.

Since there is no schematic that can be defined, use Shift+? to switch to symbol editing
mode. You will notice a change in the toolbars, making it possible to draw lines, circles
etc. and add properties.

To add a picture defining the RFNMOS device, one can either draw this, or copy an
existing picture from an existing module. To copy from an existing module, press o,
which will open the Open Module box. Then go to the module where you want to obtain
the picture, say NMOS. Open it in symbol mode, select the graphic and copy it to the
clipboard. Now go back to RFNMOS by again pressing o, and selecting it. Make sure it is
open in symbol mode. Paste the picture, and there you have it! Sometimes the picture
might be misaligned with the grid. Go to Setup>Grid and reduce the Mouse Snap Grid
units. Change it back after alignment.

8
Alternatively, one can draw the picture by hand, using the tools on the left toolbar. After
completion, you should have the following:

This is still just a picture and contains no device information.

The next step is to add ports to the device, to define the terminals. A standard NMOS has
four terminals, namely Gate [G], Source [S], Drain [D] and the Substrate/Bulk [B]. On
the toolbar to the left, select , defined as Other port. Just above this symbol, there are
three other port types listed. But since a transistor port is not necessarily an input, output
or bi-directional port, we use the Other port to define its terminals.

After selecting the applicable port type, create the port on the terminal of interest in the
picture. An Edit selected port dialog box will appear. Set the Name appropriately and be
sure to set the Text size option to a size that is more easily readable (for instance 1 in this
case). After adding the ports, your device should look like this:

The device now has ports defined, but still no behavioral properties.

One purpose of schematic capture is to eventually write a netlist readable by a SPICE

engine. Therefore, a SPICE model definition and device statement should be assigned to
the primitive module.

9
In S-Edit, this is done by adding a SPICE OUTPUT property.

An insight into SPICE

Spice uses model definitions to obtain information on device parameters. These
definitions are usually supplied by the foundry where the IC is to be
manufactured. It contains information on electron mobility, doping, capacitances
etc. and is defined in this tutorial by .md (model) files. The definition of an RF
NMOS is located in Tanner_tut>Models>rfdevices>tm>modnrf.md
Parameters for hand analysis can also be found in the definition file, but it is
essentially a type of library reference for the SPICE engine to find all the specific
device details.
Once a model definition is in place, a device statement is necessary to describe
how the device is implemented in a circuit. This statement describes the
interconnects of a specific device, its geometry etc. in a circuit and is unique to
that specific device, whereas the model definition is used for all NMOS devices,
for instance.

A model definition would typically look like this:

.MODEL MODN NMOS LEVEL=49
+MOBMOD =1.000e+00 CAPMOD =2.000e+00
+NOIMOD =3.000e+00
+VERSION=3.11
.
.
.

whereas a device statement would look like this

MN1 N3 N2 N1 N4 MODN L=0.35u W=0.7u M=1

where MODN is the model definition, N3, N2, N1 and N4 are the nodes of the
terminals and L, W etc. are describing the attributes of the specific device in the
circuit. For detailed information, refer to the T-Spice manual.

In the RF NMOS’s case, the model is fitted to RF data, and the model is described by a
sub circuit rather a single model definition. Refer to
Tanner_tut>Models>rfdevices>tm>modnrf.md for more details.

A statement for this devices takes the following parameters:

Node1 : Drain
Node2 : Gate
Node3 : Source
Node4 : Bulk
W : Transistor width
L : Transistor length
Ad : Drain area
Pd : Drain perimeter
As : Source area

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Ps : Source perimeter
Nrd : Number of squares diffusion – drain
Nrs : Number of squares diffusion – source
Rdc : Additional contact resistance – drain
Rsc : Additional contact resistance – source
M : Multiplicity

Most of the above can be calculated from the transistor width and length and the
diffusion area cross section of the drain and source diffusion strips. For the tutorial, we
will stick to defining only W and L.

In the symbol page, click on the button, which puts the pointer into Edit properties
mode. Now click somewhere on the workspace. A Create property dialog box will
appear. The first thing we want to do is make an editable property for transistor width, W,
which can easily be edited. Therefore, in the Name field, type W. The default Value type
is set to integer, but we want to enter values such as “1u” which the SPICE engine
recognize, therefore change the Value type field to Text. Now enter the default value as
1u. Furthermore, we want the W property’s name and value to be visible when
instancing(creating/using) it in a circuit, therefore set the Show field to Name and Value.
Also, change the text size to a reasonable value, such as 1. The module should now look
like this:

Do exactly the same in creating an L property, and set the default as 0.35u.

Now a device statement property should be created. In the Name field, enter SPICE
OUTPUT, which is what the netlist generator will be looking for when generating SPICE
netlists. In the Value field (after setting Value type to Text), the device statement
argument should follow. The details of this can be obtained in the T-Spice manual and
model definition files. Because we have already created the W and L properties, we want
to use that in the statement. This can be done very similarly to variables in programming.
We also want to include the defined ports in the right order in the device statement.

By noting that S-Edit recognizes %{G} as a port named G, ${W} as a property named W
and the # as an incremental value, we define the device statement as:
XRFNMOS# %{D} %{G} %{S} %{B} MODNRF W=${W} L=${L}

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Set the Show field to None, otherwise this will appear in the schematic when instancing
the device.

You have now successfully created an RF NMOS device, which you can use in circuits
and which is described in SPICE when netlisting a schematic. A netlist extract shows that
the following when creating a netlist with this device in it:

XRFNMOS1 N2 N1 N4 N3 MODNRF W=1u L=0.35u

First, we will have to define global nodes, such as Vdd and Gnd. This is already done in
the tutorial files, but can be done for other global nodes such as clocks etc.

For a clock node that is name CLK throughout the design, create a new module name
CLK. In symbol mode, draw a picture to represent the global node. Assign a global port
to the picture using the button.

Note that the module and port name may differ, but to keep confusion to a minimum, use
the same name describing both. To instance a global node, use the button.

Now it is time to design an analogue circuit with some of the primitives already defined
in the database used in the tutorial.

Create a new module, Module>New, and name it diff_amp. An open workspace will be
presented stating EPR_template:diff_amp:Schematic:Page0 at the top. If the
workspace is in symbol mode, switch using Shift+?.

Instance the following components using the button:

¾ Two NMOS transistors, defined by module name NMOS
¾ Two PMOS transistors, defined by module name PMOS
¾ One DC current source, defined by module name Source_I

Instance a Vdd and Gnd global node using the button.

12
You should now see something similar to the following:

Change the W and L values of the NMOS to 1u and 0.35u respectively, by selecting a
device and pressing Ctrl+E. A property box will then appear where the parameters can
be edited. Note that only that specific device’s properties will be changed, whereas
editing a primitive module results in a global change.

Further, change both PMOSes to W = 1u and L = 1u, and set the current source’s value to
100u.

Using the wire tool connect the circuit as follows:

13
Now we are going to add port to this amplifier and give it a symbol. Using the input
ports, label the two NMOS gates as V+ and V-, and using the output port, label the right
hand NMOS’s drain node as Vout. Note the bulk terminals are always connected to the
supplies. This results in the body effect occurring, but is necessary in CMOS
technologies to ensure continual reverse biasing if the wells.

Switch to symbol mode, and draw a picture to represent the amplifier. Use the same ports
and port names as in the schematic page.

Tip: Use the h key to flip a selected object horizontally, and r to rotate it by 90 degrees.

The symbol should now look like this:

You have now created an analogue differential amplifier. The next step would be to test if
this amplifier works, and the method to do this is via SPICE simulations. Save your
design by selecting File>Save.

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Netlisting schematics
The module diff_amp designed in the previous section will now be used to illustrate the
use of T-Spice in the design process.

The first thing to create is a test bench for the amplifier. The best way to do this is by
creating a module, for instance Spice test. Once this is done, instance the amplifier in the
new module’s schematic page. The symbol will now appear without any port names, but
instead with circles indicating the port locations.

For SPICE to understand what Vdd and Gnd does, one has to define at what potential
these nodes are set. SPICE looks for the first character in netlist lines, and then determine
what type of device it is. A voltage source is defined by
vname Node1 Node2 Parameters…

A DC power supply of 3.3V between nodes GND and VDD are defined by
v1 VDD GND 3.3

The statement has a lot of other parameters, such as sine wave generation etc. (refer to T-
Spice manual).

In this tutorial’s S-Edit database, a module named PowerSupply is defined to facilitate

ease of use. You can instance it and it immediately sets the potential between GND and
VDD. Open the module and have a look for more insight.

Instance PowerSupply to the Spice test module. This will define the global node voltages
as used inside the amplifier.

A reference to the model definition files must now be included in the netlist to define the
models used in the NMOS and PMOS devices. This can be done by creating a module
with a .include statement in the SPICE OUTPUT property, and then instancing this
module in the Spice test testbench module. The file Tanner_tut>Tanner_tut_models.md
contains references to all the available models. Have a look at that file using a text editor.

The tutorial contains a module named .include, which states that S-Edit should look at the
Tanner_tut>Tanner_tut_models.md file when creating a netlist, and further tells SPICE
to include all the necessary model definitions.

Now instance the .include module into Spice test.

Now we have to define what kind of simulation is to be run; an AC sweep, a DC sweep, a

parametric sweep or a transient analysis. We will look at each of these.

Transient analysis
Transient analysis is done when a .tran statement with the appropriate parameters are
included in the netlist. This is again made easier if a module is created containing fields
for all those parameters. The module named .tran is a perfect example. Instance it into
Spice test and have a look at its internals to get an understanding of the statement.

15
The default values are sufficient for this simulation.

Note : Modules such as .tran and .include can be easily tailored, and new ones made.
This is examples from the author’s final year project setup.

An input voltage source is now necessary to test the circuit. Instance the
Source_sine_wave source, and set the frequency to 1E6 and the peak voltage to 1E-2 (or
10 mV). This is again done by selecting the source and pressing Ctrl+E. Hook it to the
V+ terminal and hook the V- terminal to GND.

Now we still have to define what is to be viewed after the simulation, i.e. what data is to
be generated. For that, SPICE uses a .print statement. An easy way, once again, is to
create a module with a port, where the .print statement includes the port variable to which
it is attached. Instance the .print module, and connect its port to the output of the
amplifier. You will notice that a MODE property is necessary. This tells the .print
statement that the data will be in transient format (i.e. data vs. time).

The above setup is what the testbench should look like. It is now ready for SPICE netlist
exporting.

This can be done manually, by using the File>Export option and selecting the exporting
data type to SPICE format. Note the destination of the output file, which will have a .sp
extension.

Another method is to use the button. Pressing this button will result in a SPICE netlist
being generated with the same name as the module, Spice test.sp in this case, and in the

16
same directory as the S-Edit database. This will also automatically open T-Spice with the
netlist active in the editing area.

AC Sweep
In doing an AC analysis, SPICE needs to read a .ac statement in the netlist. This can be
manually entered into the netlist, or a S-Edit module can be used, named .ac sweep,
instead of the .tran module as in the previous case. Instance the .ac sweep module into
Spice test. Now the sine wave source won’t work, since the voltage source should be of
the AC type. This is easily modified in the .ac statement in the netlist. Alternatively, a
module called Source_v_ac exists. Please open and dissect this module to understand the
statement.

Intance this module into Spice test and edit its MAG property to 1e-2. This analysis will
study the AC behaviour over a frequency range, in other words, it is a frequency sweep
type of analysis.

The .print statement also needs modification. This is easily done in the instances .print
statement by setting its MODE property to ac. The type of sweep is determined by the .ac
statement, and can be edited in the .ac sweep module.

Again export this netlist using one of the previously described methods.

DC Sweep
A DC sweep is done on a specified DC voltage or current source, using a .dc statement in
the netlist. A module named .dc sweep is available to assist in this. But here the source to
be swept must be defined in the .dc statement. To do this, replace the source at V+ of the
amplifier with a DC source, module Source_v_dc. Now, to create a deterministic voltage

17
source name, edit the source’s properties, and change v# in the SPICE OUTPUT
property to vswp. This permanently names the source to be swept.

Now instance a .dc sweep module, and set the SOURCE parameter to vswp. The rest is
straightforward. Change STEPSIZE to 0.001, VAL1 to 0 and VAL2 to 3.3. This will
sweep source vswp from 0 to 3.3 Volt in 0.001 Volt steps.

The .print statement should also be changed, therefore, set the MODE to dc, to let SPICE
know that the output will be of the DC sweep type.

Export the netlist using one of the above mentioned methods.

Parameter sweep
The parameter sweep is a bit tricky, since a parameter has to be defined which is
“stepped” during each analysis run. Firstly, a parameter is to be defined in SPICE. A
.param Parameter module is available to do this directly from within S-Edit.

Using the same setup from the DC sweep analysis, instance the module .param
Parameter. Set the PARAMSTATEMENT property to Vmin = 0, which creates a
parameter named Vmin with a default value of 0. Instance a new DC source at V- of the
amplifier, and enter its value as Vmin. This will be the parameter that will be “stepped”.

Next, instance the .step parameter sweep module, and set its properties so that
DEVICE=Vmin, START=0, STOP=1 and INC=0.2. This will run the DC analysis with
Vmin staring at 0, then again with Vmin equal to 0.2 and so forth, until the analysis is run
with Vmin as 1.

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These statements are well documented in the T-Spice manual. It is important to see what
statements these “helpful” modules create and how they do it. It then becomes easy to
understand the SPICE engine and how to make things easier for the designer.

Export the netlist as described earlier.

Introduction to T-Spice and W-Edit

With a well created netlist, T-Spice serves as a very powerful SPICE engine. It is based
on the industry standard Berkeley SPICE, with some added features.

Basic netlist simulation and waveform viewing

The four netlists created above will now be simulated and the results will be viewed
using W-Edit, which has a number of useful features.

If you have simulated the above by pressing the button, you will immediately see the
T-Spice window open with the applicable netlist loaded. Otherwise, open the created
netlist in T-Spice manually.

Transient analysis
With the transient analysis netlist open, as exported a bit earlier, the following window
should be greeting the viewer:

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This contains the netlist information in the editable area. For the transient analysis, the
netlist is as follows:
* SPICE netlist written by S-Edit Win32 9.13
* Written on Mar 10, 2005 at 00:18:56

* Beneath is the amplifier subcircuit description with the terminals

* defined in the definition

.SUBCKT diff_amp V+ V- Vout GND MST_RST VDD

* This is an NMOS statement – Refer to the T-Spice manual
MN1 N4 V+ N5 GND MODN L=0.35u W=1u M=1 AD='1u*1u' PD='2*1u+2*1u'
AS='1u*1u' PS='2*1u+2*1u' NRD='1u/1u' NRS='1u/1u'
MN2 Vout V- N5 GND MODN L=0.35u W=1u M=1 AD='1u*1u' PD='2*1u+2*1u'
AS='1u*1u' PS='2*1u+2*1u' NRD='1u/1u' NRS='1u/1u'
MP3 N4 N4 VDD VDD MODP L=1u W=1u M=1
+AD='1u*1u' PD='2*1u+2*1u' AS='1u*1u' PS='2*1u+2*1u'
+NRD='1u/1u' NRS='1u/1u'
MP4 Vout N4 VDD VDD MODP L=1u W=1u M=1
+AD='1u*1u' PD='2*1u+2*1u' AS='1u*1u' PS='2*1u+2*1u'
+NRD='1u/1u' NRS='1u/1u'
i5 N5 GND 100u
.ENDS

* This is the power supply subcircuit

.SUBCKT PowerSupply GND MST_RST VDD
* V1 is not applicable
v1 MST_RST GND pulse(0 3.3 10n 0.001ns 0.001ns 1/2 1)
* v2 defines the power supply -> VDD and GND nodes
v2 VDD GND 3.3
.ENDS

* Main circuit: Spice test

* The include statement as generated by the S-Edit module (Note the
* file pathname, CHECK IT OUT!!!!)
.include ../Tanner_tut_models.md
* This is the statement printing the voltage at the specified node
.print tran v(N2)

20
* This sets up the simulation for transient analysis
.tran/op 0.01u 20u start=0

* This is the main circuit desription

Xdiff_amp_1 N1 GND N2 GND MST_RST VDD diff_amp
XPowerSupply_1 GND MST_RST VDD PowerSupply
* Note v1 is a sine wave source
v1 N1 GND sin(0 1E-2 1E6 0 0 0)
* End of main circuit: Spice test

To simulate the above circuit, press the button. A dialog box appears, which states the
input filename (default is the one open in the edit area) and the destination file for the
output. This contains the requested output data in text format. Confirm this and continue.

W-Edit will then automatically open with the plotted data. This should look like this:

That is all there is to it.

W-Edit calls these graphs “traces”. One can add more traces to a graph, or do arithmetic
operations on them, such as scaling, or adding two traces etc. The best is to play around
with it. With more than one .print statement, more traces are generated.

AC sweep
Open the netlist for the AC sweep. The netlist looks exactly like the previous one, except
that the following statements changed from
.print tran v(N2)
.tran/op 0.01u 20u start=0
to
.ac lin 100 1 1E9
.print ac v(N3)
If simulated, this should generate the following waveform:

21
This graph does not have a logarithmic x-axis. This can be changed by changing the
.ac lin 100 1 1E9
to
.ac dec 100 1 1E9

This will tell T-Spice to do a logarithmic sweep with the x-axis in decades.

DC Sweep
The DC sweep netlist looks similar to the two above, except for the following:
.dc vswp 0 3.3 0.001
.print dc v(N3)
* NOTE THE NAME OF THE VOLTAGE SOURCE
vswp N2 GND 3.3

When simulated, the circuit produces the following transfer characteristics:

22
Parametric sweep
The parametric sweep contains a number of different statements:
* States a DC sweep of source vswp
.dc vswp 0 3.3 0.001
* Creates parameter Vmin, defaulted to 0
.param Vmin = 0
* What to print
.print dc v(N1)
* Wht parameter to step, and how
.step Vmin 0 1 0.2
* Source named to be DC swept
vswp N2 GND 3.3
* Value of the source on the negative amplifier terminal.
v1 N3 GND Vmin

The following is displayed as output:

Note the number of traces on the plot.

Tips and tricks

One thing that will be notices relatively early on is the difficulty in printing currents,
since the .print statement takes the following format for printing currents:

.print mode i(<device>,<node>)

Therefore, a current into a sub circuit might be difficult to determine. The easiest way to
alleviate this is to insert a 0V voltage source in series with the branch under examination.
Name this source something like vcur or such, and the modify the .print S-Edit module’s
ARG property to, for instance, i(vcur,%{output}) so that the current going into device
vcur at node %{output} can be measured.

A lot of similar tricks is necessary, but with a little experience, it becomes a breeze.

Once a circuit performs satisfactorily, and the design is done, the next step is to draw the
device in terms of layers on the silicon substrate, or commonly referred to as “layout”.

23
Introduction to L-Edit
L-Edit is a powerful tool used to define the geometrical properties of devices in the
format necessary for manufacturing. In short, it is a program where you physically draw
microelectronic devices.

The differential amplifier designed in the previous part of the tutorial will be used as a
basis to create a layout. To start of, one needs to be reminded of the physical operation of
NMOS and PMOS transistors in the AMS C35 process used for EPR400. The file that
will be used from here on is Tanner_tut>L-Edit>EPR_template.tdb, which is an L-Edit
database containing information of process layers as well as design rules.

Physical description of NMOS and PMOS devices

The AMS process is based on a P-substrate, where the applicable diffusion layers and
polysilicon, contacts and metal layers are grown or placed on top to form complete,
operational devices.

NMOS explained

Bulk Gate poly

Source
SiO2 Drain

p+ n+ n+

p-substrate

The above diagram is very basic, but it shows the basic layers in an NMOS device. The
first thing to mention is that during the manufacturing process, a layer of SiO2 is grown
over the p-substrate, where SiO2 is a dielectric and an extremely good insulator. For more
accurate gate layout and automatic alignment of the gate over the channel, the gate is lain
down before the n+ regions are doped. This ensures a good alignment of the gate to the
channel. The gate is made of polycrystalline silicon, or poly in short, which is conductive.
The channel is then formed in the substrate when inversion occurs between the two n+
regions, thereby forming an NMOS device. The bulk is accessed through a p-tap, which
is a p+ region diffused into the substrate, and this causes a low impedance path to the p-
type material in the substrate. The drain and source are then connected via contacts to the
n+ diffusion areas.

24
PMOS explained

Bulk Gate poly

Source
SiO2 Drain

n+ p+ p+

n-well

p-substrate

The PMOS is almost exactly the same, except that it lies within an n-well with p+
diffusion regions defining the drain and source. The bulk is accessed through an n+
region connecting to the well. It becomes apparent why the substrate is always kept at the
lowest potential and the n-well at the highest potentials. This creates reverse-biased pn-
junctions, thereby eliminating most of the leakage currents that might slip through the
substrate.

Layers in a process
Referring to AMS’s process documents, one can find all the relevant information on what
layers are available and how it works, as well as what the design rules for the process are
(minimum diffusion spacing, etc.). This will be made available by your study leader.

Creating the amplifier layout

Opening the L-Edit database and creating cells
First of all, open the file Tanner_tut>L-Edit>EPR_template.tdb, which will serve as the
template for the process technology.

25
The toolbar on the left contains the different process layers used to draw the devices and
interconnects. The toolbar above the workspace contains the tools for drawing and
instancing cells.

Cells are analogous to modules in S-Edit. A primitive cell is a cell created from scratch.
One can than hierarchically create larger cells containing primitives, and then even larger
cells until a complete chip is made.

To create a new cell, select Cell>New and enter the applicable cell name in the Cell
name field. For the tutorial, enter NMOS_0.35x1 so that we know we are creating a 0.35
micron by 1 micron transistor.

Creating the required NMOS

The NMOS in question has a length of 0.35 µm and a width of 1 µm. Remember that the
length is the distance between the diffusion contacts, drain and source, the width is the
distance the channel runs orthogonally to the length.

First of all, let us define the gate. Select the poly layer on the left hand side, , named
POLY1. This will be used to define the gate. Now select the wire tool , since the wire of
POLY1 is defined as 0.35 µm thick in the top menu Setup>Layers…>POLY1>Default
wire settings. Draw a vertical wire of 1.8 µm long and end by right clicking. As you
draw, you will notice that the drawn length is displayed, and actively reflects the length
of the current wire being drawn. Alternatively, select the Drawing box button and
draw a box, also using the measurements as a guide.

The next step is to define where the diffusion should take place. Select the diffusion layer
DIFF from the left hand toolbar. Remember now, the diffusion will define the width of
the transistor. Therefore, draw a box of 1.4 x 1 µm2 and centre it on the gate, so that the
gate extends on both sides by 0.4 µm. Use the arrow to check the length of the sideway
diffusion overlap by left clicking and dragging it along from the edge of the gate to the
edge of the diffusion. It should extend the gate to both sides by 0.525 µm.

26
Now we have to define the source and drain regions.

Instance a CON_NSUB cell using the button. This cell consists of a box of diffusion
0.7 x 0.7 µm2 of size, a box of MET1, the first metal layer, also of size 0.7 x 0.7 µm2, a
block of CONT, 0.4 x 0.4 µm2 of size and a box of NPLUS, the n+ definition layer, of 1.2
x 1.2 µm2 of size. The CONT layer defines a contact that, if over the diffusion layer, hits
right down into it. NPLUS defines what type of diffusion should be done (n+ or p+) and
MET1 is a conductor, used to carry signals and (possibly) supply rails. Please refer to
AMS’s process documentation for details on all of these.

The CON_NSUB cell was instanced, because it provides a direct contact from MET1 to
the diffused n+ regions. Therefore, a terminal can be formed. Place the instanced cell in
the center, down the width of the transistor, on one side. Instance another and mirror it on
the other side. The transistor now looks like this:

The NPLUS layer now defines the diffusion used in the transistor also, so, at this stage,
this should suffice.

Next, the process documentation should be queried to determine if any design rules are
being broken. And yes, some have been broken:
• Rule NP.E.1 states that the minimum NPLUS extension of DIFF should be larger
than 0.25 µm, which is not the case at the top and bottom of the transistor.

27
 The easiest way around this is to draw a box of NPLUS exactly on the currently
existing block. After that, we measure that the NPLUS box extends the DIFF area
by only 0.1 µm. Select the newly created NPLUS box by repeatedly left clicking
on the NPLUS area, until the box is outlined and the appropriate selection name is
displayed in the bottom left of the window. Using the middle mouse button and
gripping the edge of our newly created NPLUS box, drag the box a further 0.15
µm upwards. This should then give a net extension of 0.25 µm. Do this on both
sides. The transistor should then look like this:

• Rule CO.C.1 is also broken. DIFFCON is defined as a contact box using CONT
over a diffusion area, DIFF. The area where both CONT and DIFF lies is called
DIFFCON. The spacing of DIFFCON to GATE, defined as POLY1 plus DIFF,
should be more than 0.3 µm, but is currently only 0.15 µm. Select the
CON_NSUB cell y repeatedly clicking on it until the correct object is selected,
and drag it away from the gate by 0.15 µm. This should be done on both sides.

• To eliminate sharp features, drag the initial diffusion block to the edges of the
contacts’ diffusion edges and extend the NPLUS to form a square:

28
So far so good! Now the gate of the transistor also needs to be connected to the MET1
layer. There is an existing cell called CON_P1, which connects POLY1 to MET1. This
consists of layers CONT, MET1 and POLY1. Note that the contact will stop at the poly
layer (This is process specific). Hook the contact to the bottom end of the transistor’s
gate, so that the POLY1 of the connector touches the POLY1 of the gate.

We now have a three terminal n-channel MOSFET device. The bulk contact has yet to be
defined. Use the cell CON_PSUB, which connects MET1 to the substrate via CONT into
a p+ region.

Make sure all the rules are met, such as minimum DIFF spacings and minimum NPLUS
to DIFF etc. This then defines a complete NMOS transistor.

Running DRC on the drawn transistor

To verify that all of the design rules are met, L-Edit as a design rule checker (DRC) built
in. The .tdb file used in this tutorial contains all the necessary information to ensure
proper operation, but for setting up and changing rules, use the top menu, Tools>DRC
Setup…

To run DRC, open the cell under examination (currently still NMOS_0.35x1) and go to
Tools>DRC. This will initiate the rule verification program. On completion a dialog box
opens displaying the results. If rules have been broken, one can easily navigate this box
to locate the error (Try moving the CON_PSUB closer to the transistor).

Creating the required PMOS

The PMOS will be created in exactly the same fashion. Create a new cell called
PMOS_1x1. Create a gate by using the box tool and drawing a piece of POLY1 with 1 x
1.8 µm. Create a diffusion block by drawing a 2.7 x 1 µm box of DIFF, and centre it

29
around the transistor so that the DIFF layer extends the gate on both sides by 0.850 µm
and that the POLY1 structure extends the DIFF layer by 0.4 µm at the top and bottom.

Now add CON_PSUB contact to both sides. Cover all the diffusion in PPLUS to define it
as p+ diffusion areas. Be sure to make the PPLUS extend all diffusion areas by at least
0.25 µm. Add a poly to MET1 connector using the CON_P1_2, which has two contacts,
thereby reducing the contact resistance. Wherever possible, use as much contacts as
possible to reduce this resistance.

Now add a CON_NSUB connector as a bulk contact.

There is still one thing missing, and that is to describe that the transistor lies in an n-well.
Using the NTUB layer, draw a box around the transistor. Be sure to let the NTUB box
extend all diffusion areas by at least 1.2 µm.

Run a DRC to check if any rules are violated.

30
Once the NMOS and PMOS devices are completed, the amplifier can now be
constructed.

Constructing the differential amplifier

Using the cells created, it is now time to construct the complete amplifier. Create a new
cell called diff_amp. Center the workspace around the origin (crosshair) and zoom in
appropriately. Instance two NMOS_0.35x1 and two PMOS_1x1. Space the cells as
follows:

Notice the shared gates of the PMOS transistors. Now select MET1 and the wiring tool,
and connect the nodes, as designed in the schematic.

31
The yellow-in-blue box between the sources of the two NMOS devices is called a via.
Via’s are used to connect different layers to each other, very similar to CONT contacts.
The specific cell is called VIA and connects MET1 to MET2. In doing so, one can “jump
over” other metal or conductive tracks, but only where the layer capacitances will not
seriously affect the circuit performance (for instance, the node at the sources of the two
NMOS devices are carrying a fixed current).

To define ports, one should realize that L-Edit is capable of handling two-dimensional
ports on each existing layer. Let us define the input ports as V+ and V-, etc.:
Since we want to add the port to the MET1 layer, select it on the left toolbar. Now select
the port tool, and draw either a box or (preferably) a line on one side of the terminal. A
dialog box will appear, containing a number of properties. Enter the appropriate names
for the ports.

Because we cannot create ideal current sources on silicon, we need to adjust the
schematic of the amplifier. Remove the current source in diff_amp in S-Edit schematic,
and create an extra port in both schematic and symbol modes, named Ibias. Now we can
still simulate the circuit by externally adding a current source.

A differential amplifier has successfully been created.

Device extraction – L-Edit to T-Spice

To test and verify the validity of the design, a layout extraction is necessary. The
extraction definition file is a modified version of the one shipped with the AMS digital
library, located at Tanner_tut>L-Edit>ams_C35.ext. This file is used when extracting
information from the layout, where a SPICE netlist is created from the layout itself.

To extract SPICE information on cell diff_amp, open the cell. Next, go to

Tools>extract… A dialog box will appear.

In the Extract definition file field, enter the pathname of the file Tanner_tut>L-
Edit>ams_C35.ext. Next, define where the extracted netlist should be stored by entering
the filename in the SPICE extract output file field. Follow this example to look for the
extract definition file in the L-Edit directory and to store the output in the same (current)
directory.

32
Next, select the Output tab and edit the SPICE include statement to point to the
following file: Tanner_tut>Tanner_tut_models_lvs.md
This has to be done, since the LVS program gets confused with the path names.

Once this setup is done, press Run, and a netlist will be extracted to the diff_amp.spc file
in the above case.

This netlist can now be used for post-layout simulations, where the designer is free to add
a lot of fringe and overlap capacitances in the layer setup (something not done by default
by Europractice, supplying UP’s Tanner Design Kits) and a very detailed netlit can be
compiled.

This netlist will now also be used in the LVS system, to compare the schematics to the
extracted layout information.

Layout versus schematic (LVS) verification

Two files are necessary as inputs to the LVS program. The first is the SPICE netlist as
generated by the schematic capture program. This file is named diff_amp.sp in our case.
Make sure that this file does NOT include the ideal current source as biasing element, but
rather only a terminal, as described in the previous section.

The second file is the extracted layout netlist, in our case, diff_amp.spc.

Start the LVS program from the desktop or Start Menu. Select File>New and then the
LVS Setup option. A small setup screen will now present itself.

33
Enter the appropriate path and filenames to the necessary files.
A very simple comparison will be done as an example. Click on the Output tab and
define an Output file, where the comparative results can be stored. After that, select the
Device Parameters tab. Check the boxes next to Lengths and widths in the MOSFET
Elements box. The other boxes may be checked if the designer extends the description in
the layout extraction definition.

Click on the button. The comparison should run and give verbose results:

Note that the circuits were found to be equal on the netlist level. Play around with the
layout, such as connecting extra pieces of metal between nodes, and view the output
again.

This was a very primitive comparison. For reliable results, he designer should feed the
programs with all the appropriate data necessary to create accurate netlists. After all, the
rule still applies: A simulation is only as good as it’s models.

34
Conclusion
This tutorial has touched on each and every subject necessary to complete, simulate and
verify a design on microelectronic level. This should give the user a good feel of how the
system is put together, and how to optimize the system for a specific designer’s use. The
best advice in trying to learn new software is to EXPLORE. Use the examples and gain
insight into the process by playing around with it!

35
An advanced tutorial: Digital design and Tanner Place
and Route
To automate large digital designs, Tanner Tools contains a module called Standard cell
Place and Route (SPR). Unfortunately, only standard cells can be used automatic place
and route, and although one can create standard analogue cells, it will be a tedious and
possibly unfeasible quest, since standard cells all have the same height.

Take a look at at ams_C35_dig>l_edit>ams_C35_dig.tdb. There are quite a number of

standard digital cell layouts. The companion in terms of schematics is contained in the
ams_C35_dig>s_edit>ams_C35_dig.sdb file, with the corresponding SPICE descriptions
of the circuits in ams_C35_dig>mod>ams_C35_dig.lib. The last file has been
incorporated into the tutorial directory structure and SPICE include files. Examine the
Tanner_tut>ams_c35_dig.lib and Tanner_tut>Tanner_tut_models.md files.

Copying standard cell schematics into an S-Edit workspace

Since you will probably have designs of both analogue and digital in nature inside your
design, it would be wise to copy the standard cells into your own .sdb file.

To do so, open the S-Edit file ams_C35_dig>s_edit>ams_C35_dig.sdb using File>Open.

Now, using the File menu again, go to the recent files and select your own database name
(EPR_template in this tutorial). This will have both databases open in S-Edit’s memory,
even though the user can only see one workspace at a time. Select Module>Copy and
ams_C35_dig from the drop down menu. This makes the digital library file’s modules
available.

As an example, we are going to design an a bit multiplexer chip. Even though there are
muxes in the standard cell schematic library, we are going to build one from scratch.
Therefore, copy a NAND gate, called NAND20_H. Now, return to the workspace.

Create a new module called MUX2. You should be able to instance the copied file in into
the schematic. Instance three gates and connect them as follows:
B
SEL_B
NAND20 C
A NAND20
!SEL_B
NAND20
Use the same port names and create symbol for the module.

36
Writing a .tpr netlist for routing purposes
Next, create a module called 8BITMUX. Instance eight of the MUX2 modules into the
schematic. We will create no symbol for this, since this will be the top hierarchical level
for our IC. Copy the INV0_H and CBU1P_H modules from the standard cell file. The
first is a CMOS inverter, the second is an I/O pad.

Connect the circuit as shown below. Note that one can use the nodes button to assign
names to nodes. Then connecting physical wires is not always necessary.

SEL_B
CBU1P
INV0 a1
CBU1P CBU1P A C A Y C_0
b1
a1 b1 B

A_0 A Y B_0 A Y SEL_B

!SEL_B
CBU1P
CBU1P a2
CBU1P A
b2 C A Y C_1
a2 b2 B

A_1 A Y B_1 A Y SEL_B

!SEL_B
CBU1P
CBU1P a3
CBU1P A
b3 C A Y C_2
a3 b3 B

A_2 A Y B_2 A Y SEL_B

!SEL_B
CBU1P
CBU1P a4
CBU1P A
b4 C A Y C_3
a4 b4 B

A_3 A Y B_3 A Y SEL_B

!SEL_B
CBU1P
CBU1P a5
CBU1P A
b5 C A Y C_4
a5 b5 B

A_4 A Y B_4 A Y SEL_B

!SEL_B
CBU1P
CBU1P a6
CBU1P A
b6 C A Y C_5
a6 b6 B

A_5 A Y B_5 A Y SEL_B

!SEL_B
CBU1P
CBU1P a7
CBU1P A
b7 C
A Y C_6
a7 b7 B

A_6 A Y B_6 A Y SEL_B

!SEL_B

CBU1P
CBU1P CBU1P a8
A
b8 C A Y C_7
a8 b8 B
A_7 A Y B_7 A Y SEL_B

!SEL_B

The use of the nodes becomes quite apparent when examining the schematic closely.

To generate a netlist for the Place and Route program to understand, a .tpr netlist is
created, which conveys connectivity and cell data to the place and router. If you open one
of these standard modules, you will notice a TPR= property. If no value is defined, the
value becomes the name of the cell, otherwise one can specify and arbitrary name.

The netlister searches down the hierarchy for these properties until it is found, and then
compiles a file describing connectivity and names.

After the circuit is complete, export it using File>Export…, but select now, instead of
SPICE, the TPR option. This will create a TPR file, by default called 8BITMUX.TPR.

37
Note the location of this file!!

Using SPR in L-Edit

SPR requires certain standard layout cells to be placed. The AMS digital cell layouts can
be found in ams_C35_dig.tdb.

Open the EPR_template.tdb once more. The old diff_amp module and some other
primitives should still be available. Now, there is file called
ams_C35_dig>spr>Test_pads.tdb. This file contains some design rules and setup
information for SPR that will be necessary. This will be discussed soon. To copy its setup
content into your current .tdb file, go to File>Replace Setup… A dialog box will appear.
UNCHECK ALL OF THE BOXES! In the Layers area, check the Layers box and select
the Replace radio button. Check the whole SPR area at the bottom. In the From file
field, browse and select the ams_C35_dig>spr>Test_pads.tdb file.

Next we need to set up SPR itself. Go to Tools>SPR>Setup… and notice the dialog box
popping up. Browse to the ams_C35_dig>l_edit>ams_C35_dig.tdb file in the Standard
cell library file field. This enables SPR to look for the standard cell files. In the Netlist
field, browse to the file netlisted in the section above, called 8BITMUX.tpr. This points
SPR to a circuit description of the standard cells, in other words, how all should be
connected.

The power signals will be defined by the setup as read from the Test_pads.tdb file. This is
usually vdd or gnd.

SPR can route the chip core, usually the circuit itself, the padframe (the region on the
outside of the chip where the pads are placed) and the pads itself.

The Core setup button opens the setup for the core routing. Note that all of the
information (Abut for abutment port, which cells used for crossing over, etc) are already
defined. This is because we have imported the setup from an existing file. It helps to read
up on these values in the manual to get an understanding of the process. This is well
documented. The name of the core cell can be defined here.

After you have explored the Padframe setup and the Pad Route setup, close the setup.
Now go to Tools>SPR>Place and Route… and customize the way you want the router
to work. Then press Run, sit back and wait.

After a while a cell will open containing a completely routed IC with pads. A number of
support cells, such as Row_1 etc. will be created in the process. DO not delete these, as
they form part of the IC and is a product of the way the router works.

38
There are numerous option available to customize and optimize the process for a specific
purpose, but this should be able to give the reader a good idea of how the system works.

39