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Mcp6001/1R/1U/2/4: 1 MHZ, Low-Power Op Amp
Mcp6001/1R/1U/2/4: 1 MHZ, Low-Power Op Amp
+
-
+
VDD
MCP6002 MCP6004
VIN + 2x3 DFN * PDIP, SOIC, TSSOP
MCP6001 VOUT VOUTA 1 8 VDD VOUTA 1 14 VOUTD
– VINA– 2
V –
7 VOUTB INA 2 - + + - 13 VIND–
EP
VSS VINA+ 3
9 V +
6 VINB– INA 3 12 VIND+
VSS 4 5 V + VDD 4
INB
11 VSS
VINB+ 5 10 VINC+
R1
R2 VINB– 6 - + + - 9 VINC–
R VOUTB 7 8 VOUTC
Gain = 1 + -----1-
VREF R2
* Includes Exposed Thermal Pad (EP); see Table 3-1.
Non-Inverting Amplifier
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VL = VDD/2,
RL = 10 kΩ to VL, and VOUT ≈ VDD/2 (refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -4.5 — +4.5 mV VCM = VSS (Note 1)
Input Offset Drift with Temperature ΔVOS/ΔTA — ±2.0 — µV/°C TA= -40°C to +125°C,
VCM = VSS
Power Supply Rejection Ratio PSRR — 86 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current: IB — ±1.0 — pA
Industrial Temperature IB — 19 — pA TA = +85°C
Extended Temperature IB — 1100 — pA TA = +125°C
Input Offset Current IOS — ±1.0 — pA
Common Mode Input Impedance ZCM — 1013||6 — Ω||pF
Differential Input Impedance ZDIFF — 1013||3 — Ω||pF
Common Mode
Common Mode Input Range VCMR VSS − 0.3 — VDD + 0.3 V
Common Mode Rejection Ratio CMRR 60 76 — dB VCM = -0.3V to 5.3V,
VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 88 112 — dB VOUT = 0.3V to VDD – 0.3V,
VCM = VSS
Output
Maximum Output Voltage Swing VOL, VOH VSS + 25 — VDD – 25 mV VDD = 5.5V,
0.5V Input Overdrive
Output Short Circuit Current ISC — ±6 — mA VDD = 1.8V
— ±23 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.8 — 6.0 V Note 2
Quiescent Current per Amplifier IQ 50 100 170 µA IO = 0, VDD = 5.5V, VCM = 5V
Note 1: MCP6001/1R/1U/2/4 parts with date codes prior to December 2004 (week code 49) were tested to ±7 mV minimum/
maximum limits.
2: All parts with date codes November 2007 and later have been screened to ensure operation at
VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.8V and 5.5V.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Industrial Temperature Range TA -40 — +85 °C
Extended Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C Note
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC70 θJA — 331 — °C/W
Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W
Thermal Resistance, 8L-PDIP θJA — 85 — °C/W
Thermal Resistance, 8L-SOIC (150 mil) θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 8L-DFN (2x3) θJA — 68 — °C/W
Thermal Resistance, 14L-PDIP θJA — 70 — °C/W
Thermal Resistance, 14L-SOIC θJA — 120 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Note: The industrial temperature devices operate over this extended temperature range, but with reduced
performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum
specification of +150°C.
20% 0
64,695 Samples VDD = 1.8V
Percentage of Occurrences
18%
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
5 -4 -3 -2 -1 0 1 2 3 4 5
Input Offset Voltage (mV) Common Mode Input Voltage (V)
FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 1.8V.
18% 0
Percentage of Occurrences
FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
45%
Percentage of Occurrences
-0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
VCM = VSS
-200
Input Offset Quadratic Temp. Co.;
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TC2 (µV/°C2) Output Voltage (V)
FIGURE 2-3: Input Offset Quadratic FIGURE 2-6: Input Offset Voltage vs.
Temp. Co. Output Voltage.
14% 100
1230 Samples VCM = VSS
Percentage of Occurrences
FIGURE 2-7: Input Bias Current at +85°C. FIGURE 2-10: PSRR, CMRR vs.
Frequency.
55% 120 0
Percentage of Occurrences
605 Samples
50%
VDD = 5.5V
45% 100 -30
150
300
450
600
750
900
1050
1200
1350
1500
0.1 1.E+
1.E- 1 1.E+
10 100 1.E+
1.E+ 1k 1.E+
10k 100k 1M 10M
1.E+ 1.E+ 1.E+
Input Bias Current (pA) 01 00 01 Frequency
02 03 04 (Hz) 05 06 07
FIGURE 2-8: Input Bias Current at FIGURE 2-11: Open-Loop Gain, Phase vs.
+125°C. Frequency.
100 1,000
VDD = 5.0V
Input Noise Voltage Density
95
PSRR, CMRR (dB)
90
(nV/√Hz)
80
CMRR (VCM = -0.3V to +5.3V)
75
70 10
-50 -25 0 25 50 75 100 125 0.1
1.E-01 1
1.E+0 10
1.E+0 100 1.E+0
1.E+0 1k 10k 1.E+0
1.E+0 100k
Ambient Temperature (°C) 0 1Frequency
2 (Hz)3 4 5
FIGURE 2-9: CMRR, PSRR vs. Ambient FIGURE 2-12: Input Noise Voltage Density
Temperature. vs. Frequency.
30 0.08
G = +1 V/V
TA = -40°C
Magnitude (mA)
0.04
TA = +25°C
20 TA = +85°C 0.02
TA = +125°C
15 0.00
10 -0.02
5
-0.04
-0.06
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.08
0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05
FIGURE 2-13: Output Short Circuit Current FIGURE 2-16: Small-Signal, Non-Inverting
vs. Power Supply Voltage. Pulse Response.
VDD = 5.0V
4.0
2.5
10 2.0
1.5
1.0
1 0.5
10µ
1.E-05 100µ
1.E-04 1m
1.E-03 10m
1.E-02 0.0 0.E+00 1.E-05 2.E-05 3.E-05 4.E-05 5.E-05 6.E-05 7.E-05 8.E-05 9.E-05 1.E-04
180
VCM = VDD - 0.5V 1.0
160 0.9 VDD = 5.5V
140 0.8
Quiescent Current
per amplifier (µA)
Falling Edge
120 0.7
100 0.6
0.5
80
0.4
60 TA = +125°C VDD = 1.8V
TA = +85°C 0.3 Rising Edge
40 TA = +25°C 0.2
20 TA = -40°C 0.1
0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125
Power Supply Voltage (V) Ambient Temperature (°C)
FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: Slew Rate vs. Ambient
Power Supply Voltage. Temperature.
10 6
VIN VDD = 5.0V
P-P )
G = +2 V/V
5
0
0.1
1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 -1 0.E+00 1.E-05 2.E-05 3.E-05 4.E-05 5.E-05 6.E-05 7.E-05 8.E-05 9.E-05 1.E-04
FIGURE 2-19: Output Voltage Swing vs. FIGURE 2-21: The MCP6001/2/4 Show No
Frequency. Phase Reversal.
1.E-02
10m
Input Current Magnitude (A)
1m
1.E-03
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09 +125°C
+85°C
100p
1.E-10 +25°C
10p
1.E-11 -40°C
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
R1 VDD
FIGURE 4-3: Output resistor, RISO
stabilizes large capacitive loads. VREF
R2
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the R2
V REF = V DD • ------------------
Signal Gain are equal. For inverting gains, GN is R1 + R2
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5: Unused Op Amps.
1000
VDD = 5.0V
RL = 100 k 4.6 PCB Surface Leakage
Recommended RISO (Ω)
VIN- VIN+
VSS –
1/2 R2 R1
MCP6002
VIN1 +
–
MCP6001 VOUT
+
– R2
1/2
MCP6002
Guard Ring VIN2 +
R1 = 20 kΩ
FIGURE 4-6: Example Guard Ring Layout R1
R2 = 10 kΩ
for Inverting Gain. VREF
1. Non-inverting Gain and Unity-Gain Buffer: R1
a. Connect the non-inverting pin (VIN+) to the V OUT = ( V IN2 – V IN1 ) • ------ + V REF
R2
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input FIGURE 4-7: Instrumentation Amplifier
pin (VIN–). This biases the guard ring to the with Unity-Gain Buffer Inputs.
common mode input voltage.
4.7.2 ACTIVE LOW-PASS FILTER
2. Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as The MCP6001/2/4 op amp’s low input bias current
photo detectors): makes it possible for the designer to use larger
a. Connect the guard ring to the non-inverting resistors and smaller capacitors for active low-pass
input pin (VIN+). This biases the guard ring filter applications. However, as the resistance
to the same reference voltage as the op increases, the noise generated also increases.
amp (e.g., VDD/2 or ground). Parasitic capacitances and the large value resistors
could also modify the frequency response. These
b. Connect the inverting pin (VIN–) to the input
trade-offs need to be considered when selecting circuit
with a wire that does not touch the PCB
elements.
surface.
Usually, the op amp bandwidth is 100x the filter cutoff
4.7 Application Circuits frequency (or higher) for good performance. It is
possible to have the op amp bandwidth 10X higher
4.7.1 UNITY-GAIN BUFFER than the cutoff frequency, thus having a design that is
more sensitive to component tolerances.
The rail-to-rail input and output capability of the
Figure 4-8 shows a second-order Butterworth filter with
MCP6001/2/4 op amp is ideal for unity-gain buffer
100 kHz cutoff frequency and a gain of +1 V/V; the op
applications. The low quiescent current and wide
amp bandwidth is only 10x higher than the cutoff
bandwidth makes the device suitable for a buffer
frequency. The component values were selected using
configuration in an instrumentation amplifier circuit, as
Microchip’s FilterLab® software.
shown in Figure 4-7.
100 pF
VIN
+ D1 RISO VC1
1/2
MCP6002 + 1/2 RISO VC2
– MCP6002 + VOUT
C1 R1 –
Op Amp A MCP6001
C2
Op Amp B –
Op Amp C
Sample
Switch
Clear
Switch tSAMP
Sample Signal
tCLEAR
Clear Signal
tDETECT
CLK
FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches.
OR OR
I-Temp E-Temp
Device
XXNN Code Code AA74
MCP6001 AANN CDNN
Note: Applies to 5-Lead SC-70.
5 4 I-Temp E-Temp 5 4
Device
Code Code
XXX ABY
YWW 944
NN 25
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
XXXXXX 6002I
YWWNNN 432256
XXXXXXXXXXXXXX MCP6004
XXXXXXXXXXXXXX e3
I/P^^
YYWWNNN 0432256
OR
MCP6004
e3
E/P^^
0746256
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03/26/09
Authorized Distributor
Microchip:
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