Operating System Lab (Week 1)

Part 1: Makefile

Brijendra Pratap Singh

Department of Computer Science & Engineering

Motilal Nahru National Institute of Technology Allahabad
Prayagraj - 211004, India

August 2020

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 Makefile

Makefile
Compiling the sourcecode files can be tiring
Especially when you have to include several source files and type the
compiling commands every time
Makefiles are the solution

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 Makefile

Traditional approach suffers from some problems

If this has to be done on multiple systems, the same set of commands
has to be typed repeatedly
Even if one of the files are updated, all the files are going to be
recompiled, which is inefficient
Practical projects might contain hundreds of files, which just amplifies
the inefficiencies

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 Makefile

Makefile
Make allows us to automate the process of building target file(s) from
source file(s)
At the basic level, it can be used to perform simple compilation of
multiple program files
At the advance level, it can allow us to cascade changes in a single
file to multiple dependant files and send the details to the concerned
users as an email

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 Makefile

Makefile
Uses timestamps to avoid processing unneccessary files
If the timestamp of target is newer than all the sources, do nothing
Else, one of the source files have been updated after the target,
therefore the target will be rebuilt

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 Makefile

Makefile
A file that can be only named makefile, Makefile or GNUmakefile
It is the “program” that make uses to build the target
Contains rules indicating the targets that are to be built using which
source files using which compilers along with related arguments passed
Target can be a file or an action to be taken, in the latter case it is
called a “phony target”

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 Rules are of the form

target: source_1 <space> source_2 <space> source_n

<tab> command
source_1: sub_source_1 <space> sub_source_n
<tab> command
...
...
so on and so forth

The “command” defines what has to be actually done to the source files
to produce the target. It can also contain shell keywords like touch, echo,
rm etc.

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 Example

let’s assume we have the following source files: main.cpp, hello.cpp,

factorial.cpp, functions.h

main.cpp is:

#include <iostream.h>
#include "functions.h"
int main()
{print_hello();
cout << endl;
cout << "The factorial of 5 is " << factorial(5) << endl;
return 0;
}

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 Example Cont’d

hello.cpp is:

#include <iostream.h>
#include "functions.h"
void print_hello()
{cout << "Hello World!";}

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 Example Cont’d

factorial.cpp is:

#include "functions.h"
int factorial(int n)
{
if(n!=1){return(n * factorial(n-1));}
else return 1;
}

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 Example Cont’d

functions.h is:

void print_hello();
int factorial(int n);

The trivial way to compile the files and obtain an executable is by running
the following command:

CC main.cpp hello.cpp factorial.cpp -o hello

This command generates hello binary.

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 Makefile

The makeprogram allows you to use macros, which are similar tovariables.
Macros are defined in a Makefile as = pairs. An examplehas been shown
below:

MACROS= -me
PSROFF= groff -Tps
DITROFF= groff -Tdvi
CFLAGS= -O -systype bsd43
LIBS = "-lncurses -lm -lsdl"
MYFACE = ":*)"

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 Makefile

There are certain special macros predefined:

$@ is the name of the file to be made

$? is the name of the changed dependents

For example, we could use a ruleas follows:

hello: main.cpp hello.cpp factorial.cpp
$(CC) $(CFLAGS) $? $(LDFLAGS) -o $@
Alternatively:
hello: main.cpp hello.cpp factorial.cpp
$(CC) $(CFLAGS) $@.cpp $(LDFLAGS) -o $@

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 Sample Makefile

Figure: Sample Makefile (taken from GNU Make tutorial)

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