TALLER VHDL

1. Un circuito demutiplexor de 1-8

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Entity DEMUX is
PORT ( A : IN std_logic;
E : IN std_logic_vector(1 to 0);
O : OUT std_logic_vector(7 to 0));
End DEMUX
Architecture BEH of DEMUX IS
Begin
Process (A, E)
Case A is
when “0000” => O(0) <= E; O(1) <= ‘0’;
O(2) <= ‘0’; O(3) <= ‘0’;
O(4) <= ‘0’; O(5) <= ‘0’;
O(6) <= ‘0’; O(7) <= ‘0’;
when “0001” => O(0) <= ‘0’; O(1) <= E;
O(2) <= ‘0’; O(3) <= ‘0’;
O(4) <= ‘0’; O(5) <= ‘0’;
O(6) <= ‘0’; O(7) <= ‘0’;
when “0010” => O(0) <= ‘0’; O(1) <= ‘0’;
O(2) <= E’; O(3) <= ‘0’;
O(4) <= ‘0’; O(5) <= ‘0’;
O(6) <= ‘0’; O(7) <= ‘0’;
when “0011” => O(0) <= ‘0’; O(1) <= ‘0’;
O(2) <= ‘0’; O(3) <= E;
O(4) <= ‘0’; O(5) <= ‘0’;
O(6) <= ‘0’; O(7) <= ‘0’;
when “0100” => O(0) <= ‘0’; O(1) <= ‘0’;
O(2) <= ‘0’; O(3) <= ‘0’;
O(4) <= E; O(5) <= ‘0’;
O(6) <= ‘0’; O(7) <= ‘0’;
when “0101” => O(0) <= ‘0’; O(1) <= ‘0’;
O(2) <= ‘0’; O(3) <= ‘0’;
O(4) <= ‘0’; O(5) <= E;
O(6) <= ‘0’; O(7) <= ‘0’;
when “0110” => O(0) <= ‘0’; O(1) <= ‘0’;
O(2) <= ‘0’; O(3) <= ‘0’;
O(4) <= ‘0’; O(5) <= ‘0’;
O(6) <= E; O(7) <= ‘0’;
when “0111” => O(0) <= ‘0’; O(1) <= ‘0’;
O(2) <= ‘0’; O(3) <= ‘0’;
O(4) <= ‘0’; O(5) <= ‘0’;
O(6) <= ‘0’; O(7) <= E;
when others => O(0) <= ‘0’; O(1) <= ‘0’;
O(2) <= ‘0’; O(3) <= ‘0’;
O(4) <= ‘0’; O(5) <= ‘0’;
O(6) <= ‘0’; O(7) <= ‘0’;
END case;
END process;
END BEH;
2. Un contador sincrónico de 5 bits de forma descendente.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador is

PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
cnt_out: OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
end contador;
architecture BEH of contador_is
signal cnt_tmp: STD_LOGIC_VECTOR(4 DOWNTO 0) := "0000";

begin

proceso_contador: process (reset, clk) begin

if reset = '1' then
cnt_tmp <= "0000";
if rising_edge(clk) then
cnt_tmp <= cnt_tmp + 1;
end if;

END process;
cnt_out <= cnt_tmp;
end BEH;

3. Un contador sincrónico de 4 bit ascendente

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador is

PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
cnt_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end contador;

architecture BEH of contador_is

signal cnt_tmp: STD_LOGIC_VECTOR(0 DOWNTO 3) := "0000";
begin

proceso_contador: process (reset, clk) begin

if reset = '1' then
cnt_tmp <= "0000";
if rising_edge(clk) then
cnt_tmp <= cnt_tmp + 1;
end if;
end process;
cnt_out <= cnt_tmp;

end BEH;
4. Un sistema que detecte cuando un número está entre rango 4<x<10 donde x es de 4 bits.

library ieee;

use.ieee.std _ logic_1164.all;

entity compara4 is

port (A, B: in std_logic_vector(3 downto 0);

AGB, ALB, AEB: out std_logic);

end compara4;

architecture comportamiento of compara4 is

begin

AGB <= ‘1’ when ( A > B ) else ‘0’; -- A > B, salida AGB a 1, resto a 0

ALB <= ‘1’ when ( A < B ) else ‘0’; -- A < B, salida ALB a 1, resto a 0

AEB <= ‘1’ when ( A = B ) else ‘0’; -- A = B, salida AEB a 1, resto a 0

end comportamiento;

5. Sistema que detecte la secuencia 100010