Cemat V 8.2 Function Block Library ILS - CEM

Cemat V 8.
2
Function Block Library ILS_CEM
Function Description Edition 07/16
Interlock C_INTERL
Safety Guidelines
This manual contains notices you have to observe in order to ensure your personal safety, as well as to prevent damage
to property. The notices referring to your personal safety are highlighted in the manual by a safety alert symbol, notices
referring to property damage only have no safety alert symbol. The notices shown below are graded according to the
degree of danger.
Danger
! indicates that death or severe personal injury will result if proper precautions are not taken.
Warning
! indicates that death or severe personal injury may result if proper precautions are not taken.
Caution
! with a safety alert symbol indicates that minor personal injury can result if proper precautions are not
taken.
Caution
without a safety alert symbol indicates that property damage can result if proper precautions are not
taken.
Attention
indicates that an unintended result or situation can occur if the corresponding notice is not taken into
account.
If more than one degree of danger is present, the warning notice representing the highest degree of danger will be used.
A notice warning of injury to persons with a safety alert symbol may also include a warning relating to property damage.
Qualified Personnel
The device/system may only be set up and used in conjunction with this documentation. Commissioning and operation
of a device/system may only be performed by qualified personnel. Within the context of the safety notices in this
documentation qualified persons are defined as persons who are authorized to commission, ground and label devices,
systems and circuits in accordance with established safety practices and standards.
Prescribed Usage
Note the following:
Warning
! This device and its components may only be used for the applications described in the catalog or the
technical description, and only in connection with devices or components from other manufacturers
which have been approved or recommended by Siemens.
Correct, reliable operation of the product requires proper transport, storage, positioning and assembly
as well as careful operation and maintenance.
Trademarks
All names identified by ® are registered trademarks of the Siemens AG.
The remaining trademarks in this publication may be trademarks whose use by third parties for their own purposes
could violate the rights of the owner.
Copyright Siemens AG 2005 All rights reserved Disclaimer of Liability

The distribution and duplication of this document or the We have reviewed the contents of this publication to ensure consistency
utilization and transmission of its contents are not permitted with the hardware and software described. Since variance cannot be
without express written permission. Offenders will be liable for precluded entirely, we cannot guarantee full consistency. However, the
damages. All rights, including rights created by patent grant information in this publication is reviewed regularly and any necessary
or registration of a utility model or design, are reserved corrections are included in subsequent editions.
Siemens AG
Automation and Drives Siemens AG 2005
Postfach 4848, 90327 Nuremberg, Germany Technical data subject to change.
Siemens Aktiengesellschaft
Reference Manual Objects Interlock C_INTERL
INTERLOCK C_INTERL 1
Description of C_INTERL 4
Type/Number 4
Calling OBs 4
Function 4
Operating principle 5
Input Interfaces 5
Output Interfaces 8
Engineering 9
Error handling 10
Start-up characteristics 10
Time response 10
Assignment of the 32-bit status word VSTATUS 10
Message characteristics 10
Monitoring of process variables 10
I/O-bar of C_INTERL 11
OS-Variable table 13
Variable details 14
Operator control and monitoring 15

Display 15
Operator Control: 15
Copyright Ó Siemens AG. All Rights Reserved. 3
N:\00_Cemat_Entwicklung\V8\V8200\30_Doku\Doku_Englisch\Reference\Objekte\000_Normal\C_INTERL_009.doc
Interlock C_INTERL Reference Manual Objects
Description of C_INTERL
Type/Number
Module name: C_INTERL
Module no.: FB1057
Calling OBs
In the same OB with and after the last block whose signals are to be displayed on the
C_INTERL.
Function
The C_INTERL block is used to implement a standardized interlock display which can be called
on the OS. The block can be assigned a maximum of 10 input signals, which can each be
inverted as required.
The first five inputs I1_1 to I1_5 form a group. Each signal can be linked logically either directly
or inverted by setting the corresponding inputs NEG1_1 to NEG1_5.
Important: The modification of the negation inputs NEG1_1 to NEG1_5 in runtime (download
! for changes) can lead to a loss of the RLO for one CPU Cycle.
Therefore we recommend inverting directly at the Inputs I1_1 to I1_5.
The same applies to the second group of five inputs.

The type of logic operation of the first group is set at the AND_OR1 parameter. NEGRES_1 = 1
inverts the result of Q1 used to form Q via AND_OR3. Output Q1, however is not inverted.
The two group results can be operated linked logically by an AND/OR operation.
The logic result “LOG1” is represented by green color.
4 Copyright Ó Siemens AG. All Rights Reserved.
Operating principle
Input Interfaces
I1_1 Input Signal 1, first group Basic state 1-Signal
Format BOOL
The status of this interface is displayed in the interlock faceplate. The display is grey if the signal
is ok and red if the signal is missing.
The display text must be entered under Object Properties under Text1 (only one text can be
defined per interface). The maximum length of the text string is 16 characters.
At input I1_1 a direct connection of a negation can be used. The indicated status is the status
after the negation. The negation itself is not shown in the faceplate.
NEG1_1 I1_1 will be inverted Basic state 0-Signal

Format BOOL
1-Signal at the interface NEG1_1 leads to a negation at input I1_1. In this case the negation is
visible at the Interlock Faceplate.
Note: The modification of the negation input NEG1_1 in runtime (download for changes) can
! lead to a loss of the RLO for one CPU Cycle.
Therefore we recommend inverting directly at Input I1_1.

Format BOOL
See I1_1

Format BOOL
See NEG1_1

Format BOOL
See I1_1

Format BOOL
See NEG1_1

Format BOOL
See I1_1

Format BOOL
See NEG1_1

Format BOOL
See I1_1

Format BOOL
See NEG1_1
AND_OR1 1= AND, 0= OR first group Basic state 1-Signal

Format BOOL
1-Signal at the interface AND_OR1 connects the inputs of the first signal group with an AND
function.
0-Signal at the interface AND_OR1 connects the inputs of the first signal group with an OR
function.
I2_1 Input Signal 1, second group Basic state 1-Signal

Format BOOL
See I1_1

Format BOOL
See NEG1_1

Format BOOL
See I1_1

Format BOOL
See NEG1_1

Format BOOL
See I1_1

Format BOOL
See NEG1_1

Format BOOL
See I1_1

Format BOOL
See NEG1_1

Format BOOL
See I1_1

Format BOOL
See NEG1_1
AND_OR2 1= AND, 0= OR second group Basic state 1-Signal

Format BOOL
1-Signal at the interface AND_OR2 connects the inputs of the second signal group with an AND
function.
0-Signal at the interface AND_OR2 connects the inputs of the second signal group with an OR
function.
AND_OR3 1= AND, 0= OR both groups Basic state 1-Signal

Format BOOL
With 1-Signal at the interface AND_OR3 both signal groups are connected with an AND
function.
With 0-Signal at the interface AND_OR3 both signal groups are connected with an OR function.
QC_Q_I Quality Code for output Q Default: 16#80

Format BYTE
Input QC_Q_I can be connected with the quality code of a driver block. This quality code is
transferred to output QC_Q.
Output Interfaces
Q1 Interim result, first group
Format BOOL
Output Q1 shows the interim result of the first AND/OR function.
Q2 Interim result, second group

Format BOOL
Output Q1 shows the interim result of the second AND/OR function.
Q Output signal
Format BOOL
The result of the complete interlock function is shown at output Q. This output is used for the
connection to the interface of the CEMAT block.
QC_Q Quality Code for Q

Format BYTE
This quality from input QC_O_I.
Additional output as Interface to the OS:

VSTATUS Status word for OS
Format DWORD
Interface to OS
For more information see Variable details.
Engineering
AS:
CFC Plan editing example:
The assignment of instance names is particularly important when the Interlock module is used.
Depending on the "main object", the name is formed as follows.
For example, C_DRV_1D motor with plant identifier "FK11/E001" should be given an interlock
protective circuit on the input interface "ESVG".
The name of the interlock module instances consists of:
FK11/E001 = main object
_ESVG = interface description
1-3 = number of the interlock modules, max 3 units
i. e. FK11/E001_ESVG1 is the name of the first interlock module.
Please note:
- Correctly select the interconnection logic (red background means error)
- Assign the signal designations for the control room operator with understandable text.
- Only Text_1 is displayed in the Faceplate
- on one Interface it could only connect one of the Interlock module Type
(Interlock or Interlock5)
OS:
No further parameterization is necessary.
However, an OS compile must be carried out (in order to generate the tags in the tag
management).
Error handling
Only by means of the operating system.
Start-up characteristics
No special measures taken.
Time response
The block does not have a time response.
Assignment of the 32-bit status word VSTATUS

See VSTATUS for C_INTERL
Message characteristics
Does not exist.
Monitoring of process variables

Does not exist.
I/O-bar of C_INTERL
C_INTERL
Permitted
Element Meaning Format Default Type Attr. HMI
Values
I1_1 Input signal 1, first group BOOL 1 I +
NEG1_1 1 = I1_1 will be inverted BOOL 0 I
AND_OR1 1= AND, 0= OR first group BOOL 1 I
I2_1 Input signal 1, second group BOOL 1 I +
AND_OR2 1= AND, 0= OR second group BOOL 1 I
AND_OR3 1= AND, 0= OR both groups BOOL 1 I
QC_Q_I Quality Code for output Q BYTE 16#80 I U
Permitted
Element Meaning Format Default Type Attr. HMI
Values
Q1 Interim result, first group BOOL 0 O
Q2 Interim result, second group BOOL 0 O
Q Output signal BOOL 0 O
QC_Q Quality Code for Q BYTE 16#80 O U
Extended status display in

VSTATUS DWORD 16#00 O U +
block icons
OS-Variable table
C_INTERL
PLC Data
OS Variable Description OS Data Type
Type
I1_1 Input signal 1, first group BOOL Binary variable
I2_1 Input signal 1, second group BOOL Binary variable
Extended status display in

VSTATUS DWORD Unsigned 32-bit value
block icons
Variable details
Internal structure of the Status word:
OS- Msg Fault

Parameter Function Designation German Designation English
Addr. Class Class
VSTATUS Status Status

I1_1 Eingangssignal 1, erste Input signal 1, first group
VSTATUS_B41 0
Gruppe
VSTATUS_B41 1
Gruppe
VSTATUS_B42 2
Gruppe
VSTATUS_B43 3
Gruppe
VSTATUS_B44 4
Gruppe
I2_1 Eingangssignal 1, zweite Input signal 1, second group
VSTATUS_B45 5
Gruppe
VSTATUS_B46 6
Gruppe
VSTATUS_B47 7
Gruppe

VSTATUS_B30 8
Gruppe
VSTATUS_B31 9
Gruppe
VSTATUS_B32 NEG1_1 10 1= I1_1 wird invertiert 1 = I1_1 will be inverted

VSTATUS_B24 20
VSTATUS_B25 21
VSTATUS_B26 AND_OR1 22 1= AND, 0= OR erste Gruppe 1= AND, 0= OR first group
AND_OR2 1= AND, 0= OR zweite 1= AND, 0= OR second group
VSTATUS_B27 23
Gruppe
AND_OR3 1= AND, 0= OR beider 1= AND, 0= OR both groups

VSTATUS_B10 24
Gruppen
VSTATUS_B11 25
VSTATUS_B12 Q 26 Ausgangssignal Output signal
Q1 Zwischenergebnis erste Interim result, first group
VSTATUS_B13 27
Gruppe
Q2 Zwischenergebnis zweite Interim result, second group
VSTATUS_B14 28
Gruppe
VSTATUS_B15 29
VSTATUS_B16 30
VSTATUS_B17 31
Operator control and monitoring
Display
When an interlock protective circuit is present, the corresponding interface is indicated with a
blue point in the diagnostic dialog of the associated module type.
The interlock dialog displays the input parameter name of its logical state and the subsequent
interconnection.
In an error situation, the input signal is displayed with a red background.
For the control room operator meaningful designations should be chosen for the input
parameters.
Operator Control:
A single click on the corresponding interface designation opens the Interlock dialog.
The interlock dialog can be closed using the “Close” Button.
Further functions are not enabled.

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Operator control and monitoring 15

Copyright Ó Siemens AG. All Rights Reserved. 3

The same applies to the second group of five inputs.

4 Copyright Ó Siemens AG. All Rights Reserved.

NEG1_1 I1_1 will be inverted Basic state 0-Signal

I1_2 Input Signal 2, first group Basic state 1-Signal

NEG1_2 I1_2 will be inverted Basic state 0-Signal

I1_3 Input Signal 3, first group Basic state 1-Signal

NEG1_3 I1_3 will be inverted Basic state 0-Signal

I1_4 Input Signal 4, first group Basic state 1-Signal

Copyright Ó Siemens AG. All Rights Reserved. 5

NEG1_4 I1_4 will be inverted Basic state 0-Signal

I1_5 Input Signal 5, first group Basic state 1-Signal

NEG1_5 I1_5 will be inverted Basic state 0-Signal

AND_OR1 1= AND, 0= OR first group Basic state 1-Signal

I2_1 Input Signal 1, second group Basic state 1-Signal

NEG2_1 I2_1 will be inverted Basic state 0-Signal

I2_2 Input Signal 2, second group Basic state 1-Signal

NEG2_2 I2_2 will be inverted Basic state 0-Signal

I2_3 Input Signal 3, second group Basic state 1-Signal

6 Copyright Ó Siemens AG. All Rights Reserved.

NEG2_3 I2_3 will be inverted Basic state 0-Signal

I2_4 Input Signal 4, second group Basic state 1-Signal

NEG2_4 I2_4 will be inverted Basic state 0-Signal

I2_5 Input Signal 5, second group Basic state 1-Signal

NEG2_5 I2_5 will be inverted Basic state 0-Signal

AND_OR2 1= AND, 0= OR second group Basic state 1-Signal

AND_OR3 1= AND, 0= OR both groups Basic state 1-Signal

QC_Q_I Quality Code for output Q Default: 16#80

Copyright Ó Siemens AG. All Rights Reserved. 7

Q2 Interim result, second group

QC_Q Quality Code for Q

Additional output as Interface to the OS:

8 Copyright Ó Siemens AG. All Rights Reserved.

Copyright Ó Siemens AG. All Rights Reserved. 9

Assignment of the 32-bit status word VSTATUS

Monitoring of process variables

10 Copyright Ó Siemens AG. All Rights Reserved.

I1_1 Input signal 1, first group BOOL 1 I +

NEG1_1 1 = I1_1 will be inverted BOOL 0 I

I1_2 Input signal 2, first group BOOL 1 I +

NEG1_2 1 = I1_2 will be inverted BOOL 0 I

I1_3 Input signal 3, first group BOOL 1 I +

NEG1_3 1 = I1_3 will be inverted BOOL 0 I

I1_4 Input signal 4, first group BOOL 1 I +

NEG1_4 1 = I1_4 will be inverted BOOL 0 I

I1_5 Input signal 5, first group BOOL 1 I +

NEG1_5 1 = I1_5 will be inverted BOOL 0 I

AND_OR1 1= AND, 0= OR first group BOOL 1 I

I2_1 Input signal 1, second group BOOL 1 I +

NEG2_1 1 = I2_1 will be inverted BOOL 0 I

I2_2 Input signal 2, second group BOOL 1 I +

NEG2_2 1 = I2_2 will be inverted BOOL 0 I

I2_3 Input signal 3, second group BOOL 1 I +

NEG2_3 1 = I2_3 will be inverted BOOL 0 I

I2_4 Input signal 4, second group BOOL 1 I +

NEG2_4 1 = I2_4 will be inverted BOOL 0 I

I2_5 Input signal 5, second group BOOL 1 I +

NEG2_5 1 = I2_5 will be inverted BOOL 0 I

AND_OR2 1= AND, 0= OR second group BOOL 1 I

AND_OR3 1= AND, 0= OR both groups BOOL 1 I