fromamicroprocessor ? ‘Ams, A microprocessor is an LSI (large scale integration) chip that is capable of performing arithmetic and lpi funetons as defined by agiven program and acomputerbult with a microprocessor iscalleda microcomputer. (Q.2, What are the advantages of using a microprocessor in an ‘Ans. The advantages of using a microprocesorin an instrument ae (@redveed size () more reliability i) elimination of ditt of. snalog circuits and () changes in design of thesystem isnot a ‘ause for total redesign ofthe sytem. Q.3, What isa date bus? Ans. The data buss group of eight lines used fr data flow. These lines are bdirectional-data flow in eth etions between the MPU and memory and pheripheral devices. The MPU uss the ata bus to perform the second function: transferring data, ‘Thecight dtalines enable tle MPU to manila it data ranging from 00 ro FF (2% =286 numbers). The largest mamber tt can appear on the data bus is IIILILL (255g). The 8085 microprocessor is known as an 8-bit microprocessor. Microprocessors such the Intel 8086, Zilog 78000, and Motorola {68000 have 16 data Tines: hus they are known as 16-bit ‘microprocessors andthe Intel 80386/486 have 32 data ines thas they are classified as 32-bit microprocessor, Q.4, Whats aconto bus? Ans. The control buss comprised of various single lines that carry synchronization signals. The bus is bi-directional but the individual line is unidirectional. The MPU uses such line to perform te third function: providing timing signals, Q.5. Whatare the applications of microprocessor ? Ans. Microprocessors find wide applications in the fields of instrumentation, communication, data processing, industrial process instrumentation, commerce and consumer prod. ype (Questions With @nswers Q.6. Whatisthe frequency ouput of eighth FE when the inputelock frequency is 512 kHz? AME, See ernie Cra Sommer 2095) Ans, 4 kil (Q.7. What is expanded form of EEPROM ? How is an EPROM eco ULL Sc Bet Cre Summer 2085) ‘Ans, EEPROM stad for Electrically rasable Programmable Read uly Memory. Foreraing i its to be taken ouo is normal {rc and placed in front of 2 special ultraviolet eraser for several mints Q.8 Why'is the maximum numberof instructions posible in an eight bit microprocessor256 ? (UPS. LES. ete Earring I 2008) ‘Ans. Maximum number of instructions possible in an n-bit microprocessor is 24, s0 for an eight bit microprocessor maximum number of instructions possible = 2° = 256, There are 256 possible combinations of 00000000 to LLLI1111 in 8 bit microprocessor (Q.9. What is the function of signal at pin marked 1O/M in 8085 microprocessor? (UPSC-LES. ute Eagnrnt, 206) ‘Ans. This is a status signal used to differentiate between UO and ‘memory operations. When tis high, tndiates an YO operation; When tis low, itindiatesa memory operation, (Q.10. Why is the7-flog of 8085 microprocessor not affected aftr ‘execution ofthe instruction MOV D, B ? PSC. KES. eet Eien 302) ‘Ans. Z-flag ofan 8085 microprocessor is only affected afer ALU operation of microprocessor. The zero fag is sti the ALU operation results in O and the flag is reset Le results nt 0, MOV D, Bis nota ALU operation hence Zero) fl is not affectedAnswers: 1.(0.2.(6),3.6 Microprocessors uestions I. Digia computers use complement sition, The manson forivis (very simple process. () elimination of direct subtraction (©) casy handling of negative numbers. (@ simplification of iret. Personal computer cannot sd for wich one ft flowing? (2) Gane psyng. (6), Weater forecasting, (©) Officeautomation. _(€) Home computing oe (UPS LES: EEA 309) following are included inthe achitecueo compe? 1 Addressing modes, design a CPU. 2 seton set, data formats : 3 ‘memory. operating system. Select the correct answer veal ars sing the code given below (@) Land2 ony, (© 2and 00! only. (©) 1 and3 only, (@) 1,2and3. (use tas. exe, 0,20 ‘A microprocessor is ALU (a) andconrloiton singe on single chip. (2) andmemory ona single chip. (©) reper unit and WO device na single. (@) ptr wit and conta uiton single hip. ftrse-tes. nem ALU Ashmet Lope Ui ofan 888 mires csi (2) Acca emporay ier het a aS. (©) Accumulator, arithmetic ond vee. (2 Acoma acting count, temporary reise hme logic ccs and five fag. furse ues ee, Which ofthe Fotlowing art eres satement()? 1. Busis group of yieneanying information. 2 _Busisnesiedtesctieveresomble sped operation 3. Buscancapy-dat for adress 44 Abus conte shared by more than one device. Seletthecrrect answer from th coves sven below 6) Loniy. (oy tand2only. © 2Sanddonly. ——(@) 1.2,3and4 frse ins exes, 09) . Consider the following statements: 18085 microprocessor, data-busand adess-bus are multiplexed inorder to 1. Increase the speed of microprocessor. 2 Reduce number of. Coanect more peripheral chips ‘Which ofthe above statements sare corect? (@) Lonly “(b) 2only (©) 2and3 (@) 1,2and3 UPS. LES. EAL 20) 40.5. @), 6.7.0), 8, Consider dhe following statements on binary tee 1. Attee with nodes kas (n— 1) edges. 2. labelled androoted binary tee can be uniquely constructed ives post-order and pre-order travel ress. 3. ‘The maximum number of aodes ina binary tre of hei Geptyhis 2*"~ 1). 4. Accomplete binary tree with » internal noses as (n + 1) eaves. ‘Which ofthe statements given ove are correct? (@) 4,2, 3and4 () 1, 2and3 only. (and 3enly. (@) Zand 4 only. [UPC LES. ETH, 207) 9, The parallel computers ae divided into which of the following shitectural configurations ? 1. may processors. 2. Data Processors 3, Mul-processor systems. 4, Pipelinecompuers Selec the comet answer using ecole give below: (@) L.2and3 only. (), 2S and 4 ony. (© 13andonly. (6 1, 2and4 only. TPS TES AL, 20m 10, Consider teflon iterents: 1. The out unitof «computer communicate the response ofthe ofpater the user. 2, \READ/WRITE memory volatile. 3), The flipflops in register are connected in pale “Which ofthe above statements are correct? G@) Lonly (b) Tand2 (@) 2and3 (@ 3only (UPSC LES. Et 209 11, The suitable programmable counter for 8086 microprocessor is (a) 8253chp. () 8254 chip. (e) 8359 A chip. (©) 251 chip. UPR. UES. EE, 25) 12, In 8085 microprocessor, how many interrupt are maskable. (@) Two. () The. (@) Four. (@) Five. Turse ies eet 26) 13, Which components are NOT found on chip in a microprocessor ‘but may be found on chip in microcontoler? (@) SRAM and USART. (6) EPROM and PORTS. (©) EPROM, USART and PORTS. (@)_ SRAM, EPROM and PORTS. urs.e.t8s. etn 201) 14, Which stack is used in 8085 microprocessors? @ FIFO) @) FILO (© LIFO @ tno 15, In'an instruction of 8085 microprocessor, how many presen? (@) One ortwo, (©) One, two or thee (©) Oneonly. (@ Twoorthree Turse. tex, 16, The interfacing device use for generation of accurate time delay ina microcomputer system is (@) Incl 8251. (e) el 8253, () tet 8257 (6) Inel 8259. [Ups ues ea 20n (©), 9. (©) 10. (0), 14 (b), 12 (©), 13. (0) 14. (0), 18,0), 16. (0),0. 18, Bs. 2. ‘Question Bank in Electrical Engineesing 8085 miroprocesoris a Ibitesiter, The program couneri Deewase (@)itcounes 16 bits aati, (@) there are 1S address times, (©) itfecilates the user storing 16-bit data temporarily. (@) ithastofetch ewos-bitdataatatime. TUPSC. LES. EEL 200) ‘Which one of the following addressing echrigue isnot used in 8085 microprocessor? () Regisr (©) Regiserindivee. (0) Immedias, 4) Relative (Urs. ts, em 200, ‘Which of the following re features in an 8085 microprocessor system with memory mapped 10? 1. DOdevices have 1-bit addresses, 2. WO devices are accessed vsing IN and OUT instructions, 13. There canbe maximum of 256 input devices and 256 output sevies, Select the comect answer using the code given below : Codes: @ 12and3, (©) 2and3 only (©) Land3 only (@ Land only TOPS LES EE, 7) Which one ofthe foilowing isthe mos suitable definition of ARRAY ? {@ Itisacollection of tems which share a common name (©) tis collection of items which share # common name and ‘ceupy consecutive memory locations. (©) Iisacollection of items ofthe same type and storage class ‘which share common name and occupy consecutive memory locaton (© isjusta collection of unordered items. (UPS Les eet 207) Consider the following statements 1 Stitly speaking C supports I-dimensional arrays only. 2. Anarray clement may bean ara by itselt. 3. Array elements need not occupy consecutive memory locations. Which of the shove statements fare correct? G@) Lonly. (@) 2only. (©) Land2. @ 24nd, (UPS, ERM) ‘Which oft following are the memory perforpagece parameters? Access time and atency. 2. Block size and block acess ine. 3. Cycletime snd bandwidth, Selec the comet answer fram thlcades given below: (@) Lonly ‘@) 1and2omly (©) 2and 3 only (®) 1,2and3, (URS LES EL 20 What is the purpose of DMA facility in microprocessor based (@ To increase the speed of data transfer between the AP and WO devices. (©) Toincrease the speed of data transfer between the uP and the rmemary. (©) Toincrease the speed of data transfer between the memory and the 1O devices. (@)Toimprove the reliability of the system, TPS. LES. 200 A Direct Memory Access (DMA) transfer implies (@)_ Direct transfer of data between memory and accumulator. (0) dliect wansfer of data between memory and VO devices without the use of microprocessor. a () ‘Transfer of dataexchiveiy within micmprocesortesisters. (OA fast transfer of data between microsrocessur and YO eves. JUPSCUES- RIL 2008) . Handshaking mode of data transfers (@) Synchronous data transfer (©) Asynchronous dats transfer, (©) interrupt driven data transer. (©) Level mode of DMA data ransfer. (ues: 2S. EE, 2010) ‘Ouipat ofthe assembler in machine code is referred a8 (@) Objectprogram. ———(b). Source program. (©) Mactoinseuction. (4) Symbolic addressing, (UPS LES. EEL 203 1. In a microprocessor, the address ofthe next instruction to be executed, is stored in (@) stack pointer. (©) program counter. (©) addess ach 8) general purpose epister. (GATE Bx 1997) Inet 8085 A microprocessor ALE signals made high to (2) enable the data bus tobe used as low order address bus. (©) tolatch data Dy-D, fom data bus (©) todisable databus, {@)toachieve all the functions listed above. TUPSG 15. 0, 2008 ‘Which one ofthe following statements fr Ind 8085 i correct? (@) Program counter (PC) spexifestheadeessof the nsruction lastexecuted. (©) PC specifies th address of the inseton being executed. (©) PC specifies the addess of te lnsruction tobe executed, (2) PC specifies the limber of instructions executed so fr TUPSC LES. Ee-T, 3000 ). Which one ofthe Yollowing register of 8085 micropocessoris not pat of programming model”? (- Hascuction register. O. Status register TUPSC LES ET, 206) Inhow many different modes aunivecsal shift register operates? @2 3 Of ws : (orse-188 Rem, 2010 A shift egiter with the serial output connacted back tothe sera inputisa (@)_Teedback shit register. (©). shiftrepister counter. (©) universal shit register. (G) seria to parallel converte. Both the ALU and contro section of CPU employ which special urse.us. ee. 200) Purpose storage locations ? (@) Buffers. (©) Decoders. (©) Accumulator. (@) Registers. (UPS. LES, 208) ‘Wich one oft lowing sateen des ot describ oper characteristic of stack pointer-epsterin 8085 (@)_ltpoins 1 top ofthe stack. (b) Its UP/DOWN counter, (©) Itisautomaticaly iniiaized vo OO00H on power-on. (@) Misa 16-bitregister. (PSC. LES. EM, 2007) The description ofa program counter (PC) in 8085 microprocessor (@) anupldown counter, (b)_an8-bit register. (©) initialized automatically by microprocessx. (@)_ used to pointtostack memory area. (UPS. LES. Et 208) Answers: 17 (b), 18. (0), 19. (6), 20. (€), 21. (b), 22. (), 23. (0), BA (b), 25. (8), 26. (b), 27. (€), 2B. (B), 29. (), 30. (©), 31. ©). 32D), 38. (©), 34. (0), 38. (0),7 ‘Wars the addres space of 8086 CPU ? @) OneMegabyics. ——(h).256iloby © Tinegabyes. (@)_ GEkilobytes. UPS eS. ETE 290), ‘A memory system has a total of 8 memory chips, each with 12 addres lines and data lines. The tal size ofthe memory system 4a) I6kbytes, ©) 32k bytes. (©) 4Bkbytes, (@) 64k bytes (care EE mes, ‘The number of oupins of 8085 micropracesser are @ 0) 27) 2.) 19. (UPS HES Ext 200 Microprocessors ee (©) 4m asynchronous sequential circuit operating im the fundamen mods. @ avasynchronous sequestal iret opertinginplse mode. Ne Pet Dial Ces ee 2008 ‘Consider the following statements: 1.” total of about one milion bytes can be direly addressed bythe 8086 microprocessor. ; £086 asthe 16 bit register. 086 has cight aes. Compare 8086, the 8026 provides higher depree of memory protection. ‘Which ofthe statements given above ae comet? 2 Widhonesltetovgisuatasteimetecaipitas WR Sm gL Sats tenia even bb maeiconies @ tame @ kee (a) 8259 (b) 8255 (©) 8253 (d) 8251 (OPSC LES. BEST, 20051 Tiradtes ete, Constr eftovng fons 8 ior 40. Costrtebivicgmmessbattiarinieretweny 7 (heya 1 tice mtapostae sees E Sorbpetet atmo lisinDs 2 ihabstrwatcoe coe 3 Serle mon 3 talowrcmesfaeny CRU autasterinincia. «3 seems i Mima iretoanas Thich denote ste stn? Vidhan pean? Odea naan Oa re 8 23a @ sims Same Braet PGh cea ee : (4. ianlcoconpues vy ewan? 4 MOUBeIMC Giamnieivtering SZ“ Sena og ORUDEMA open (a) To rt the logical fevels at the ‘and sendir bomen! iba, ered Bag ive ees ate acing eg Pr dig ni Toso pert em © Tons pelteteoe artemis ©) Toomere tM catgsatecotagantnevng © Tonetneon pee tipo mac ater vee ie 18. Sedma puge pega pen pe ee ee rmmarenpaiven irae (UPSC. LES E-t, 000) processing. Tis is because 42, The content of the Program Counter of an Intel 8085. N97 aa proccasing with vcghncrs ie caner hen with meaner. acquire ona Oy barge ahs acme mtn errr rrine race efile teeta auc entero teinntin ig co Si anstee tat roin innen (©) Theadaress ofthe next instruction to be execute, (@) Data processing with registers takes fewer eyees than that (G)_ The number of instructions executed sufar ‘with memory. Leis ee ee! Tipe teseesomm a Keppra ossinganliceaasenlyangag 43, ‘The content ofthe programme counteeof an 8085 microprocessor programmer makes use of the general purpose registers rather : Soe eee (te wut amir tlic nde prog stenty ar an pring wh memey be : o 6) deal canines 0 Sanprcesing ons wen ise sd © temencyesiarotocineiortastsageiely —_) ur nono acinnsion ete aera sont romaine © Remminadtenctieimniontaintecied (Seta Ear ie ver a at = oc ao eee ‘44, While a program is being executed in an Intel 8085 microprocessor, S1. Consider the following statements : eprmncomueltcsrpee sm cee npr 1 map 10 pon (5 Semen emetic eagerly Pal ‘executed. 2. Pointers cannot be used to access memory mapped 1/0 ©) ean stiesoticineniondatsetecues > a ee ‘3. Fewer machine instructions can be used with /O mapped (2 femmtrofinmacn hae aden DOniangscopannensyeayettO see © Seuuinmiwetinincerinicesenpepensts 4 waned early Sen im ae ses ing 10 mone U0 45, tee ati siienire (nay ue ca wo TIT 2mae © mse co ima ©) tues ml Socio you seen sta tn a spllonn pre toaster Hae 36.37 0,3, (39.05 4, Bh A, A, ALO AT, HAH HUST§8BE—_cueston Beni in octal Enginecing 52, Wiad hininicngt mney eqenenttaprogan Go Mesiniring nner of marc (0) Minimiingromber of masoc {©) Minimizing cept rcen @ BomGjandiGabove, jusse ass exe £58, Which logical orration is performed by ALU of tn to Sonpkmenta mater 'AND. (©) NOT (OR @ sxctusive or poese us we 54 The cote of memory lotion 4 FH ae 101101, The memory werd cutd mt be inerpeed ay hich one othe following? (@) 'scomplementnumber.(b}_'scomplement number. (©) Octal number (@ BCD number. UPS LES. FEI 0, 55, Ifthe ASCII character His sent and the characer Is received, ‘what typeof enor is represented? (a) Single-it () Muliple-bit © Burst (8) Recoverable TUPSC UES. Et, 28) 86. Which one of the following is correct for ASCII code ofall upper ‘ase English letters compared tall lowercase English eters? (a) Areall larger. (©) Aveallsmatir. (©) Areal equa (@) Some are larger and some are sale. TUPSC. LES. EE 2006) ‘57. The circuit iltastrates atypical application of the JK Mip.ops. What does this represent igh ici ciocg ux ou Pus E (A shiftrogister, (©) A frequency divider circuit (©) A date storage device. (@) A decoder circuit (OPS LES EE, ‘8. Circuit showa below is a +f ol Soh ale Oe (®) shit ropster (©) pple counter. (©) binary counter. (@) sequence detector. TUPSC. Les. E20) 59, Memory-tmapped UO scheme for the allocation of adress to ‘memories and UO devices, is used for (2) smallsystems, (0) largesystems, (©) both arg and small systems, (very large systems, furse urs Ream) 9, Which one ofthe following statements about RAM is notcomect? @)_ RAM stands for random-access memory () Kisalsocalledreadiwite memory 6. o. (©). Wheayowe: supply snitched off he itormation in AM. isusualy lost, (4) ‘The binary contents are entered or ster in the RAM chip during te manufacturing. forse Ls rt, 2003, ‘Which one of the fllowing statements is conexi? (@) ROMis: Read/Write memory (©) PC points tote last instruction that wasexccued (6) Stack works onthe priniple of LIFO. (@) Alvinstrctonsaffecttbefags. (usc. ues et 2009) Which ofthe following eof the combinations logic types ? 1. ReadOnly Memory. 2, Random Access Memo. 3. Shift Register Memory. Select the correct answer using the codes gives below : Codes (@) Land? () Qand3 (6) Gand3 (@) 1,2and3 TUPSC. LES Eb 993) Why does an increase of the RAM of computrtypicaly improve perforce? (@) Virwal memoryincrease.(b). Larger RAMs are faster. (©) Fewer page faults occur, (6). Fewer segmentation faults occur, (Urs. 12s. BIE. 2007 single ROM is used design a combinational circuit deseribed byatruth table. What isthe number of adessines inthe ROM? G@)_ Numberof input variables inthe uth be. (©) Number of output variables inthe uth able. (€) Number of inpu plus ouspursatables inthe uth table. (@)_Namber of lnes inthe trutheabe, (UP. 188.87:-1 2061 Consider the followingstatemerts Datathat ae stored ata va adress in arandom access memory swelost 1. whem poWeF goes off 2. when the data are read from the address, wen new data are waite atthe addres. because itis non-olale memory. ‘Which ofthe statements give above are corset? (@) Tand2. (o) 1,2and 4.) and. (a) Land. TUPSC LES. Est, 206) Consider the following statements Tnmemoris, 1. ROMs are use foremporary program and data storage. 2. dynamic RAM is ess expensive than static RAM, 3. MASK ROM is used in high volume microprocessor base system, Which ofthe statements given above islare comet G@) Lonly. (@) Land2. (@) 2and3. (@) 1,2and3. UPS. 18 EL 0s) Consider the following statements: 1 The process of entering 2. ROMs are volatile memories. 3. ROMS are used in uC security systems ‘Which ofthe staternents given above ae correct? (@) L.2and3. () Land 2only. (©) Zand 3only (@) Land 3 only. WPS 1S. Et 2007 is called burning in ROM, A semiconductor ROM is prefered to a semiconductor RAM because (@) ROMis cheaper than RAM, (©) ROMis aster (€) ROM does nat require power supply fr their operation ()_ Program storedin the ROM cannot be steed, (UPSc-18S. Rt, 201) Answers: 52. (d), 83 (€), $4. (4), 85. (6). 56. (D), 57. (C), SB. (2), 59. (by, 60. (d), 61. (B), 62. (8, 63. (C), 64. (2), 65. (@), 66. (6), 67. (8), 8.08),6 nt. ‘The increasing onder of spe! of data access forthe following devices (Cache Memory, {iy Dynamic RAM (9), Magnetic Tape. i) Co-Rom. (is) Processor Registers, 0) (Ai, GD, 65. 60) @ L6.0.6i0,00 ‘A erry system of G4 k bytes needs tobe desiened with RAM chips of 1K byte each, and a decoder tee constructed with 2:4 decoder chips with “Enable” input. What i the total number of ecoder chips 7 @ 2 6 © 2 w2% (urs Les eet 206) ‘What re the number of memories required of size 16% 4to design memory of size 64 x8? oo @6 ws (UPS. LS 09) 3. Memory chips of four ditferent sizes as below are available Lo 2Kx4 2 QKxI6 3 8Kx8 4 Kea n m 1 16. 7. Pp. Al the memory chips as mentioned in the above list ate Read Write memory: What minimal combination of chips or chip alone an map full addres space of 8085 microprocessor? @) Land2. (0) Lonly. (@) only. (d) domly (rs ues, 205) “The smallest valid signed integer that can be stored in a memory location of a4 x8 bit RAM is. (0 () -128- ©) 2048 (d) ~65536 (UPS. LES. Ea 201) ‘The capacity of a memory chip is 8192 bis it has 2088 rows ‘Then the organization ofthe chipis (@)- Word organized (©). byteorganized. (©) nibbleorgarized. (4) bi TAACLE SHC 8 ELECTHONIE CIRCUITS SUMMER 206 Eight memory chips of 32x 4 bit size have their addres buses ‘connected together. What sthe size ofthis memoysyser)? (@) 5122 dis (0). 256.4 bits, (64x 16 dis (@) Bx a2e (ese tes ren,207 A I6 bit memory addres register cam address memory locations of @ 16k — @) 322% We) 64k @) 128K wrse.1es. RE, ame, Suppose 64 K8&, ROM ICs are available in abundance. 1 MB. ROM canbe obained from (@) 16ICsinarow. —_(b)_161Csinacolumn, (©) 8ICsina column and 21Cs ina row. (@)_ None of the above. UPS. KS RAL 28 Inwhich units the performance of cache memory measured ? (@) Ha, (6) Bits, (©) Cache constant (@) Hitrato (UPSC. LES. Ex 207) ‘Thelogicereuitusedto generstethe active Ay low chip select (CS) by an 8085 4 microprocessor to address a peripheral is —q shown in figure. The peripheral will respond to addresses inthe range. (@)5000-EFFF. (0) O008-FFFE, (©) 1000-FFFF. (6) 0001-FFFI. (exten 200 aL . Thelogiccieut wea generate Microprocessors ee e vy tie acu low chip elect signal A 4 So we os oo Iicopecstr to adres» peipheruisovninigae. 81 ——L Te yepert wierd asin ang. () OOH TF) WOH TEFEH (© Moon AFEEH (6) aMO BFR H teat a bean PAMIC is arranged in 8 rows Sixty-four number of 256 4 and 8 columns get memory of (@ 1KB (6) 2KB Ge) 4B © 8B (WPS UES. Em, 2030) ‘Theredced site ale of asequentie machine has 7 rows. What the minimum number of ip-lops needed to implement the machine? @ ao 2 OT 3 URS LES ext, 200 ‘Toaaddress the memory I its are used. Then what isthe adress ofthe last memory location? (@) 16382") 1GBRS —) 16384) 16385 urs tes. BE 200 | Theshieisershown infig- oes seein one with Nols ] bitpaer 1010 Subsguealy SEA 85. theshiftrepiserisclocked and with ech clock pulse the pat tem gets shifted by one biepo- sition to dhe ight With each shift the bit the ssa input is pushed to the left mast position (easb)eAfter how many clock pulses will the content ofthe shit register become 1010aguin? Qs 7 ou @ 15 (GATE Bx 203) B255A chips selected when Ay to.A, pins ate 1, what isthe address of Port? @ FC PD © FB @ FE (urste ues Ext, 20m, 168255 4 chips selected when A isto A; bits teal! 1, what is the address of por A? @ 9) FA © FR @ FC urs ues J. Inmode 0" Zero} operation of 8255, the ports can be wsed as port, (a) A 2s input por only (©) Aasoutput port only () Bas output por only (2) Aas input or ouput port [UPS Les Ee, 20 3. Ports are used to connect the CPU t0 which of the following nis 7 Prine, 2. Floppy disk drives. 3. Videodisplay unit, 4 Incoming power supply. Select the corect answer using the codes given belo: Codes G@ Hand 2, (&) 2and3. (@) and 4. (@) Land3. (URS LES: EU, 205) 1. When a program s being executed in an 885 microprocessor its Program Counter contains {@) the numberof insrutions in the extrent program that have already been execute. () the tal umber of suction in the program being exeeued Answers: 69. (0), 70 85. (0), B6, (2), 87), 88. (), 89.) TH. (A), 72. (6), TB. (), TA (B). 78. (UD). 76. (©), 7. (0), 7B. (), 79. (a), HO. (4), BH. (b), #2. (€), 83. (0), 84 ()o Question in Eictrcal Engineering (6) thememory addres of he inseucion tnt is being curently executed, (@) the memory adres of the instruction that isto be executed ext (GATE RE 03) UF the status ofthe control lines $1 and SO is LOW, then 8085 microprocessors performing (2). Reset opration. (©) Haltoperstio, (@) HOLD operation (2) Interupt acknowledge Consider the ftlowing: 1. Signa. 2. Trapfag 3. Parity ag. 4. Auxiliary cary lag. ‘Which of the above lags slave present in 8085 microprocessor? (@) Tony. (b) tand2. (@) 2and3, (@) 1,3and4, (OPS. Les, Bet 30m ‘The sign-fag of 8085 micrnprocessoris setto 1 if (8) theresultofan arithmetic operations zero (©) the most significan:bitof theres of en arithmetic or logic operation i (©) thereis a cary from addition or borrow fom subtraction. (@)_‘Theresut of the operation cartes fur Is in accumulator. (UPS LEs Bet 30) Inthe case ofa 16-bit processor asngle instruction is enough to rocess function. For processing the same function, (8) more than one 8-bit processors willbe required to work in sequence. ‘more than one $-bit processors will be required to work in parle, ‘long sequence of instructions wil be required for a &-it procestor. © © (@) the same instruction will do fr a8-bit processor 100, 101, 102, Selects correct answer using the cade given blow (@) Land 2 only. “) 2nd 3 ony © Land 3 only (0) 1.2083. (IS 18. e208) {nan Intel 8085A. whic i always the fst machine eyele of an instruction ? (@ Anop-code fercheyele, (b) Amemoryreadcycle, (©) Aiemory writscycle. (8) An UO read cycle TOPS LES. .5-, 20 . The frst mache cycle ofan instruction isalways (@) amemoryreadeyele. (0) afetcheyele, (© anVOreadcycle ——(@)_amemory write cycle TUPSC. LES. EE, 20 ‘A group of personal computers are configured to werk togsther for speeding wp the execution ofa single program in (@) simutatedevaluation. (6) clustercomputing. (©) network computing. (@) client serves computing TUPSE LES. ERE 20 the HLT instructos ofan Intel 6085 microprocessors executed (@) the microprocessors disconnected from the system bus till the RESET is pressed. the microprocessor halts the execution ofthe program and reiuras tothe monitor. (©) the microprocessor enters into a HALT state and the buses sre -sated. the microprocessor reloads the propram counter from the locations 0024 H and 25H.) (Uae. 18.8 R109) ‘The contents of memonyloceidns 2000 H, 2001 H and 2002 H sae AH, BBH and CCH reipectvely. What ar the contents of H and L registersafier execating the following instructions in sequence? © © 105. (4), 106), TUPS.C. 128. EEL 200) cae Ce 94, ‘The ouput daatnes of microprocessors and memes reusaly NAS ho ceret ser esing te code ge below pepmederam! A@ Contents of Hand | registers are 20 H and 01 H, respectively. (4) morthan om vie tannin over hed (0) CounctitendL ieee a AAHontBBtCcc reer, us by enabling only one device st atime. (©) Contents of H and L registers are BBH and CCH, respectively. (©) mee tha one device can asm over the data he (@) Contents of Han L vegies areCCHand BBA respecte, Sametime (PSC. ues ete GB Meal eentemmlinlesed orbohputeacouput, gy ig it ete cone of hcl wad of inl 825 fr or Mode 0 (operation) an fo the following ports configuration Port A —cutput, Port B — ouput, 95. Which one fhe following icone? Pott Cee — OP Poet Cpe ——npt? A mieroprogram is @ STO sn Wn @ sn (@)_anyscurce propaga pion microcomputers. (rss, 2000 {b) any setofinsiosforprimiiveopertonsinasystem, 104, Which ofthe fllowngisntcomect? (© general game for macos" ved in assembly language (2) Busis a group of wires programming (&)_Bootsrapisatectiqu or evc forking fitinsttion (© any program of every smal sins wesc 185. am (©) Aninsrveonisast ofits that defines computer operation, 96. Which one of the following is correct ? (4) "An imerrupt signal is required a the star of every program. ‘Amicropegram tuse-tes Re (@) isusually ween nigh level language 10 ‘The aléressng mde wsdinthe insrvction MPF 37 incase (©) isaprogam for mirocompute ofan nel 8085 microprocessors whichone ofthe following? (©) isaprogam vrtenin sembly langage (@) Dire (©). Reviserniect. (@)_isasequencing program for the conro unit of any processor. (©) Implicit (@) Immediate Tose tes Ee Sm TUPSC. 18, Ex, 2) (97. Which arc the characteristics of vertical micro instructions ? 106, ‘When the operand requires for an instruction is stored iaside the 1." Considerable encafing of contol information proceso, then what his aldresing mode called? 2.Limited bil expres parallel micro operation, (@) Diet. (by Resi 3. Long format © Implicit (8) meine, (PSC.1RS. a0 Answers 90, (0, 9. (8), 92: (C93. (6), 94. (0) 95. (B96 (B97), 9B. (a), BB. (), 100 (8), TON. (), HOR. (Hy 1038, @, 104. @,107, Whatare the eommands tothe ascimble itself, called? (0) Macros 0) Macro-insirctons. (©) Micro-insuctions. (4). Paeudo-insrutions. TUPSC 18 ETE, 207 108, ‘The cycle required to fel and exeeute an instruction ina 8085 snicroprocessris which one ofthe following? Clock eyte (©) Memory eycie. (6) Machine cycle (@) Instruction eyele. UPS. HES REAL 207) 108. If Kis the numberof parity bits provided with a messuge, the ‘numberof errors which ean be detected are @ KK @) K-1 @ K+t (@) dependent upon the number of isin the message aso (UPS. Les Ee 03) ‘Aa 8254 programmable interval times consists of independent 16-bit programmable counters, Tis umber is @2 63 ©4 ws (Urs 1s Ee 2098) ‘An Intel B085A microprocessor is operated at a frequency of 2 “Mliz If the instruction LXIH, 000 H that takes ten” states, ‘executed, then whatistheinstruetion eyele time? (@) 10Hs &) Sus ©) Aus @) 25jss (urs Us PRA 208) ‘The 8085 assembly language insuucton tat stores the content of ‘Hand L registers into the memory locations 2050, and 205 yy, respectvelyis 110, m1, 1m, (@) SPHL 20505, ©) SPHL 20514, (@ STAX 20804, (©) SHLD 2050, care 2x 20s) ‘Whats the comect 8085 assembly language instruction tha stores the contents of Hand L registers into the memory locations 1080 Hand 1081 H respectively? m3, (@)SPHL 1080 H (@) SHLD 1080 11 (©) STAX 1080 H (@) SPHL 1081 (ORS. sna, 29) 114, What isthe number of machine cycles in te instruction LDA 2000 H hat consists of thirteen states? @2 3 Ot ws worse a, 20 4 8085, i the loc frequency is MR he tine required to excute an insirvcionaf 18st () 30m @) 36us @ 40m (® 6oys urscoiks BYE, 2m Toseraly shift bye dts no a hit eps there must be (@ oneclockppse (0) oneload pulse. (©) eightcloce pus (@)_oneclock pulse foreach oe inthe dat TABLLE Sec Bacto Cs Winter 86 ‘A memory system of size 32 Kbytes is required to be designed using memory chips which have 12 addres tines and 4 datalines ‘ch, Wht i the numberof soch chips requied to design the ‘memory system? or OB us, 16, 47. Ow @ 2 (UPS Les ers, 208) ‘Toadress the full memory space ofan Intel 8085 microprocesot| four RAMS of different sizes are available: ua, LBKx8 2 16Kx4 332K x4 4 32Kx16 ‘What minimal combination of chip() wil serve the purpose? @ L23and4 2 © 3 (@) 4 qurseurs.ee-u,2my Answers: 107. (6), 108 120. a1, 123, 1a, ms, 126. 7. 128, Microprocessors & Which ofthe fotowing semen canesponding execution cf SIM amt ino comet” (a) eilselecvelymarall be eras of 5. (6) Comeats oft (areas on SOD pin oly iit 2g in seis (©) RST75 canrest without exestng ISR orRST 7.5 (@) Reaandeinerpsandseral O.(erse ues-n,20m INR insti of 8085 doesnt fet cary Nap Wich ofthe folowing cot about INR insrstion? (a) Ovedlow can noe detects (©) Overtow canbe dette. (©) Haprogamreqaies veo tobe tect ADDinsructon shouldbe used instead of INR (@) canbe sedoinrese becomes of he BC register pi. forsetssten, bas) (On eeving an interop the CPU ofan 8085 mcuprocestor (@) complete curenindron nthe gost intern (2) tranees fo he itt sevice ote immediatly (©) hands over contol of adress bus and dats bu 1 she inerping device. © weOHALT eforeemint aaa Tose tes nen, bom ‘The 259A programmable Inert conlesan 1. manageciht interop, 21 sectorenitemsptequsta ber i memory map. 3. ve ior 16-btinervalctveen inept vector oations 4. inated wih operon command words(OCW's) (®) Tand2. () 2and3. (©) Bandas (@) 1,2,3na4. UPS. net, 20m) The ingerupt vector table VT of 8086 contains (@), “The contents of CS and IP ofthe main program address at “which the interupt has occurred. @) The contets of CS and IP ofthe main program address to hich th contrt has to come back afte the service routine. (©). Thestating CS and IP vale ofthe iterupt service routine. (@) The starting address ofthe IVT. (UPC. Les. Ea, 205 ‘Intel 8085, the interrupt enable flip-top i reset by (@)_Diinsructions only. (b)_system RESET only. (©). imerupt acknowledgement only (@) ether Dfor system RESET or interupt scknowledgement. (UPS LES et, 6) ‘When an 8086 executes an INT ype instruction it (@) Resets both IF and TF flags. (6) Resesall lags. (©) Sets both IF and TF. (2). Resets the CP and TF. (UPSE-L8S BR, 05) ‘Whats aninteruptin which he external vie supplies its address 28 well as the interrupt request known as? (@) Vector interrupt. (6).-Maskableinterrpt. (©) Non-maskabl interrupt. (4) None ofthe above. [UPS 1S EM, Control buss used for transiting and receiving contro signals between (@) processor and keyboard (©) processor and various devices (©) processorandimemory. (8) igutdevies and memory ‘When TRAP interuptis triggered inan Intel 8085A, the program control is tansferred to which one ofthe following ? (®) 0020H (b) 0024H (c) OO28H (@) WHICH (UPS. LES, EE, 20 (6), 109. @), 110. (0), AH. (0), 112. (©), 113. (), 14. (©), IIS. (0), 116. ©), 17. (2), 118. (@), 119. @), 120. ADL. (9), 122. (4), 123. (€), 124. (€), 125. (€), 126. (0), 127. (0), 128. (0),i: 13. 136. Bi. 132, 1, 138, 136, 131, 138, 139, 140. ‘Question Sank 19 Elostioat Engineering ‘Ths power fnitee alarm mast he connected fo which on of the following inputs of $085 ? (@) RST7S (@) TRAP (© INTR (@) HOLD (UPS. Les ect 207 ‘Which oe ofthe following is not a vectored interrupt? (@) TRAP () INR @ _RST3_ (@) RSTIS (GATE RE. 2; LPS. LES Ei, 200) Which intercupthas the ghost proity? @ RST7S () RST? (@ RSTGS (@ INTR UPS. Les. EAL 20) Which one ofthe following inemupss is both level and edge sensitive? (@ RST75 (b) RSTSS (6 TRAP (@) INTR TUPSC LES. EE, 205) Which ove ofthe following isthe software intercept of 8085 microprocessor? (@) RST7S (b) RSTT (© TRAP. (@) INTR Turse Les, EM, 306) ‘Which value a program counter wil have when non-niskable ‘nerrupt of 8085 microprocessor ie serviced? (@) 0008 1, (®) OOH. (©) 0028 H. (@) 0034 H, . TUPSC.1ES. eet 200) In 8085 microprocessor, the order of priority for hardware iterups, are (@)_ INTR,RST 75, RST 65, RST, TRAP (@) TRAP, RST 75, RST 6.5, RSTS5,INTR (©) TRAP, INTR, RST, RST65,RST 75 (@ INTR.RST55, RST 65, RST TS, TRAP ‘uur. ues, ett ama, ‘Three deviees P, Q and R have to be connected to an 8085 ‘microprocessor. Device P has the highest priority and device R has the lowest priority. In this context, which ofthe following is ‘the comet assignment of nterupt inputs? (@) Puses TRAP, Q uses RST'S. and R uses RST 6. (©) Puses RST S'S, Quses RST65 and Ruses RST 7, (©) Puses RST 7.5, Quses RST 65 and R uses RST 5 (@) Puses RST 55, Quses RST 65 and R uses FRAP. TUPS.6cL6S le Which on ofthe following statements rag le INT (inept) and the BRO (but request) pins ina CEU sue? (@) TheBRQpinis sampled aflerevery instruction cycle, butthe INTissampled after eyaryjaphine cycle Both INT and BRQge¢ sainpled efter every machine cycle, ‘TheINT pinis sampled after every instruction eyee,butthe BRQiis sampled after every machine cycle. Both INT and BRQ are sampled afer every instruction cycle TOATE RE 7) For 8085 microprocessor, the instruction RST 6 restarts subroutine ataddress @ oor o © @ (OH @) 30H (a) 33H (PSC. Les, Eat, 02) Which can be maximum dimension ofan aray in C language Program? M3 4 @s (@) tiscompiter independent. (URS. UES. ex, 209) Iman Intel 80854, what isthe content ofthe Instruction Register aR (2) Op-ode forthe instruction being executed, (©). Operand forthe instruction being executed, 1. 12, 183, 44, 5, 146. ur. 148, 9, (©) Op code forthe instruction tbr exccuted nex. {@) Opecand forthe insirution wo he execute uex. TUPSC LES. EEA, 20m) "The opcode forthe insuuction “Add Immediately te Accumulatue with ez" in 8085 microprocessors @ ADI) ACI @ ADC * (@) ADD TUPAC LES. EEL, 210 ‘Inanntel 80854 microprocescr, why is READY signal sed? (2) Toindicateto usr that the microprocessors working andis ready for use. ‘Toprovide proper WATT sats wien the microprocessor is communicating with slow peripheral device. ‘Toslow down a fas peripheral device so as w communicate atthe microprocessors speed. (®) None ofthese. (URS. UES. 20) 1 8085, the DAA instruction is weed for (@) Direct Address Accumulator. () Double Add Accumulator (©) Decimal Adjust Accumulate. (@) Direct Access Accumulatoe, (UPS. LES. EH, 24) ‘Which of the following does not ake place when 8085 processor isreset? (2) 8085 gives reset out signal to rest extemal hardware, (©) 8085 resets program counter to FEFFH. (©) Theinteruptsysemis dished, (0) ‘The buss aretrisate. ‘Which signal of 8085 microprocessor is used to insert wait states? (@) Ready YALE (© HOLD @ INTR Turse LES. Ea, 20m) © © Ursc. ts. net, 205) ‘When REY ifufuctionisexecuted by any subroutine then @ the top of the stack willbe popped out and assigned tothe Pe. ut any operation, the calling program would resume from instruction immediately folowing the call nsiretion. the PC will be incremented after the execution of the instruction. ‘without any operation, the calling program would resume {rom instracton immediately following di val iastution, andalso the PC willbe ncremented aftr the exeation ofthe instruction. (UPSC LES. EE, 200) ‘The eld, whichis never presenti an assembly language statement, 5) Opcode (©) Cominve (©). Operand (8) Comment UPS. LES. EL 200) ‘What are the ses of commands ina program wich ae nt ranslted into machine instactions during assembly process, called? @) Mnemonics (©) Directives. (@) Meniiers. (© Operands UPS. LES. Et 207) ‘A sequence of instruction is executed as follows: begin decode the instruction fetched; ‘operand in memory then fetch operand; execute instructions; end “This sequence of instructions ha performed @) fetcheyele () bothfetchandenecwe cycles. (©) executeand decode cycles. (@) exceweeyce TUPSC.LES. EAL 200) ‘Answers: 129. (b), 130. (b), 131. (a), 132. (€), 133. (0), 134. (€), 138. (6), 136. (©), 137. (2), 3B. (©), 139. (@), 140. (@), HAL (), 142. 143. ( 144. (0), 145. (0), 146 (8), 147. (0), 148. (€), 149. (0),150. 1st. 152. 153, 154, 155. 156, 157. 158, Answer “The addressing inode used inthe struction SATX.B is (@) rect. (b) immediate (6) implci. (in TUPSC-185 REL, 8) How many aod which types of machine eycles are needed to ‘execute PUSH PSW by an Tatel 8085 microprocessor? ()_ 2, Fetch and Meinory wie () 3, Fetch and? Memory wit (@) 3.Feich and Memory read (@) 3, Fetch, Memory read ynd Memory wsite. TUPSE-UES 61 25) In 8085 microprocessor, during PUSH/PSW operaion, sack pointeris 5) decremented by one, (©) incremented by one. (©) decremented by two. (@) incremented by 0. TUPSC- 18S. R- 20) Which one ofthe following addressing modes is used in the inaction PUSH B ? (@ Direct (0) Reister, (©) Registerindiect. (2) Immedie TOPS LES. Et 200) Consider the following 8085 instructions [ANA A, ORA A, XRA A, SUB A, CMP A. "Now, consider the following statements 1. _Allatearthmetc and loge instrctons. 2. Alleause the accumulator to be cleared imespecivs ofits ‘riginl contents, 3, Allresctthe cary lag. 4 Allofthemare -byte instructions. ‘Which of te statements given above islare comet? (a) 1,2,3ant () 2only. (©) Zand, (@ 13and, SEE m5) If the accumulator of an Intel 8085A microprocessor contains '37H.and he previous operation has sete cary ag th istuction ‘ACIS6H will result in @ EH © 4H © EH @ BH Turs.c- 1568 1 20) ‘Which one of the following functions is performed by te 8085, {nsiestion MOV H.C? (2) Moves the contents of regisigr Ha € pei. {(@)_ Moves the contens of C regex yo tegistr. (6) Moves the contents of C register WL. pair. (2). Moves the contens of HL ptt C register TUPSC- Les. E-,200 Consider the exebdbi Of the following instructions by 8085 microprocessor LXTH, O1FF SHLD 2050, Aller execution the contents of emery locations 2050, and 2051 and the registers Hand L, willbe (@)- 2030. FF: 20514 > 01; H > FF; L~0 () 20804, 01; 20815) FF; H > FF. 01 (©) 2080, FF: 2051), 01; H > 01; LFF. (@)_ 20804, FF; 2051), > 01; H + 00; L— 00. UPSC.LES E1200) ‘An output device is interfaced with an 8085 microprocessor as ‘memory-mapped HO. The address ofthe device i 1000 H. In ‘order to output data from the accumulator othe device, what will, be the sequence of instructions? (@)_ LXTH, 1000H MOV A, Mt (©) EXT HL 10008 MOV M, A (©) LHLD'1000H MOV A, M (@)_LHLD 1000H MOV MA (usc 2-1 209) 164, (c), 165. (2), 166.8), 159, 16. 161. 182, 163. 164, 165. 166, Microprocessors Carry fig is notafected ater the execution of @ ADDR () SBBB @ INKS (@) ORAB fuese, Ws Fit, 20m Prosessor status word of BOSS microprocessor has five flags. ‘Which ae these five lags? (@) S,Z,AC, PCY, (©) S.Z,0V.P.CY. i) SOV, AGP,CY. @ S.Z,AC,¥,0¥, (UPC IES 6x, 206) Which one ofthe fotiowing RO8S asembly angungeinsrctions ‘doesnot affect the contents ofthe accumulator? (@ CMA () CMPB @ DAA (@ ADDB TUPSE.S. EEL 200) ‘Which one ofthe foiiowring statements isNOT correct? (a). CMP A is a single byte instruction and CMA is not an (0) ‘The instruction SUB A sets the zero flag. (©) Bus isa group of wires. (@)_ Instruction INR C doesnot affect cary fag TUPSe. Urs. eet, 0) [After an arithmetic opefation, the flag register of a 8085 ‘mieroprocessor has the following ook Dy | Pe] Ps | Pe} PD | Pz | P | Do es The arithmetic operation asrevultedin (@) Acary and an ofA party nimber having 1 as the MSB. (6) Zero and dealer earry flag being st (©) Avoumberwith even parity and | as the MSB. (@)_ A number with odd parity and 0 as the MSB. [UPSe.Tes. eam, 208, ‘Oxiexcouion ofthe following segment of instructions in sequence MVEA, SIE “XRI OU Sihich one ofthe following is corect 7 a) Content of ccumulato is OOH. Carry, Auxiliary Carry and Zero flag st 100, 1 and 0, respectively. Contentofsccumulatoris 91 H, Carry, Auxiliary Carry and ‘Zero tag sto 0, Oand 1, respectively. ‘Content of sccurmlatr is OOH. Carry. Auxiliary Carry and Zero flag set10 0, Oand 1, respectively Content of accumulator is 91H, Carry, Auxiliary Carry and ‘Zero flag sto 0, 1 and 0, respectively TOPS. UES EL 207 Examine the following instruction to be executed by a 8085 microprocessor The input port has an address of O1H and has 2 data OSH to input © © © IN OL ANI 80 After execution of the wo instructions the following fag portions ‘may occur 1. Zero fagisset. 2, Zoroflagis reset 3. Camyflagiscleared, 4, Auxiliary cary flagis set. Select the correct answer using the codes given below Codes: (@) Land3 (b) 23and4(c) 3and4 (a) 1,2andd (UPS. UES EEL 200) An input device is inverfaced with Intl 8085 microprocessor as ‘memory mapped VO. The address ofthe devices 2900H. Inorder to input data fons the device to accumulator, the sequence of insrietions willbe (@) LXt #25001 Mov AM 150, (a), 151. (b), 152, (0), 153. (©), ASA (), 15S. (2), 18. (0), 187. (€), 158. (b), 159. (), 160. (a), 161, (0), 162 (2), 163. (®,eS @ 1x Mov © ump Question Bank in Electrical Engineering 250011 MA. 2500 Mov AM @ ELD 2500 Mov M, (eave ee: 28) For I6bitadres-bus, ian 8 K RAM chipis selacted when. Ay Aygand Ay gadares bits areal one, then whats He rengeo the memory adress? @) OOOH - BFFFH (©) POOH ~ FFFFHL Lt SP, MVE A XRI oH PUSH PSW POP: a Mov A, ort 10H LT ‘What ae the contents of A H, L, SP and PSW repisters after executing the above set of instructions? Assume undefined fags slays remain cleared, - (2) 108, 25H, 00H, 7EFFH, OOH respectively. (b) 14H, 27H, O48, 7FPFH, O41 respectively (©) L4H, 25H, OOH, 7FFFH, O4H respectively, (@) 10H, 27H, O48, 7FFFH, OOH respectively, TUPSC ies Ken, 0) 167. (6) FOOOH - FRRFHL (@ FOOOH — FEEEH TIPS LES it, 20) 168, 25H 169. ‘Thestackpointeof an 808SA microprocessorcontans ABCD H. PUSH BSW. XTHL PusH =D iMP EC 3H Atte end ofthe execution ofthe above instructions, what would ‘be thecontent ofthe stack pointer? (® ABCB I) ABCAH(©) ABCOH () ABCEHL (UPSe. 18, Be 20 176, ‘The stack pointer ofan 8085 microprocessors ABCDH. Atthe end of execution ofthe sequence of instructions, what wil be the ‘content of the sack pointer? PUSH PSW XTHL PUSH D IMP. FCTON @ ABCBH wy ABCA (©) ABCSH (6) ABCSH Tesc.1Es. ea 28m, ATL. The contents of Program Counter (PC), when the microprocessor {steading from 2FFF H memory location, will be (0) 2FFEH (b) 2FFF H (©) 300011 (4) 3001 UPS Es tL, 208) 1 the following program is executed in a micfoprocessor, the ‘numberof instration cycles wll take from START to HALT is START MVIA, 14 SHIFTRLC INZ. SHIFT HALT 8 on nm, 1 Rotate left without carry + Jump on non-zero to SHIFT ws © 16 tears ex, 204) 173. An 8085 microprocessors executing the programme a fallowe MVIA, 2041 MVIB, JOH m4, a8. 176. m. it, 180, BACK: NOP. ADD B RLC INC BACK, HLT iow many tes te instruction NOP will be executed? O08 oa a 1 fUPSC.Les. 24-1, 205) ‘Toexecute the followinginstructons LDA 2100 H (®) LXIH, 21004 by a inte 8085 microprocessor the numbers of memory eycles requiredare: (@) 2 for(i) and 2 for Gi) (©) 3for(i)and3 for Gi) (©) 4 for (and? for Gi) (@) 4 for() and for Gi) wesdues. 2x0, 015, "he following sequence of instructions are executed by en 8085 Imicroprocessor 1OOOLXISP.27 FF 1003 CALL 1006 1006 POPE; ‘What arc the contents ofthe stack pointer (SP) andthe HL. register pairon completion execution ofthese instructions? 7 FF, HL = 1003 () SP =27 FD, HL = 1003 mrse{tes e321, 2005 instruction allows control transfer toa subroutine, hich when complete, sue the instruction to turn contol othe main program, (@) CALL, IMP. (6) CALL,RET (©) CALL RSTI (@) BLDIursctesee-1.206) Which one ofthe following signal combinations wilt generate MEM. signal? NOMA RD ©) JO VRD. 0% vRD © TOMAR (UPSC- 15,241,200) nan 8085A microprocessor based system its sited toincrement the contents of memory location whase address is avalabe in (D, E)register pairand store the result in same location. The sequence ofinstruction ie (@) XCHG () XCHG © INXD (@ INRM INRM —INXH —XCHG XCHG. - Which one ofthe following instructions 3-byte instruction? @ MVIA (© IMP2050 ©) LDAXB (® MOV A.M UPS. LES. Pt 206) Read the following Assembly Language Program Segment of 808s rT RIM ANI 80H SIM ‘What ind of task is performed by above se of instructions? (2) Sends bit out on SOD pi (©) Accepts bitin from SID pin, (eo) Accepts RST 7-5 interrupt. (@) Resets RST. interrupt Wwrse.t8. EE, 20m How many times will the following loop be executed ? xB ‘ooo Loop: ex B Mov AB ORA c INI Loop Answers: 167. (6), BL, 168. (), 169.6), 170. (6,171. (€), 172. (0, 173. (8), ATA. (A), 175. (6), 176. 0), 177. 0), 178. (179, 18D.183, 186, 187. 188, Selec the comet answer using the code given below © 0 © 6 @ Is UPS ese 2006) is written as given below 4, 25D ij 25D iu Loop a INZ_ LOOP How many times DCR i instretion wil be executed 2 @) 255°) S10 (©) 65025 (4) 65279 (cave ex 2008 ‘Which one is the indirect addressing mode in the following, instructions? (@ LXIH2050 1H (@ LDAXB (©) MOV A,B (@) LDA 20504 (UPS. RE, 2008) ‘An example of 8085-instruction that wes direct addressing @ LC (&) STA @ RRC) CMA UPS. LES. Et, m0) ‘nan 8085 microprocessor, the contents ofthe Accumulator, after the following instructions are executed wil become XRAA ‘MVIB FOH SUBB @ OH ©) OFH © FH @ 0H (Gare ee. 200) MVEA, AAH oR FFH RRC RRC cme 5 ‘What are the contents of A and PSW registers after executing above set of instructions sequence? (@) AAH and 00H (8) FH and 66H! (©) 00H and S48 (€)_ 00H and oof (nse, bes ee, 219) For which one of the following, the idgticson XRA A in 8085 microprocessor can be used? (@) Setthe cay fag. (©) Setthe zero ag (Reset the carey ag tnd clear the accumulator. (@) Transfer PPRo the accumulator. {UPSC.LES. E41, 200) ‘The following program is writen for an 808S microprocessor to ad two bytes located at memory address IFFE and IFFF LXL HL, 1FFE MOV BLM INR OL MOV AM ADD B INR MOV MA XOR A Oncompleion ofthe execution ofthe program, thereof adtion is found (@) intherepister A. (b)_atthe memory address 1000. (©) atthe memory address 1F00. (@) atthe memory address 2000. roar ex, 205) 190, 11. 1m. Microprocessors && Read the following Assembly Language Progra Segment of ‘8S Microprcessn UXT H,2501H = MOV ALG MOV AL ANI FOH ORI FOH MOV HA MOV LA HLT |Whatare the contentsof A, Hand Lreicters after executing the above set of nsrsctions in sequonce ? {@) Contents of A, Hand Lregisor are 25,201 respectively. () Contents of A, H and L registers are 05, 25 and 01, respectively (©) Contents of A, H and L registers are 20, 20 and Fi, respectively (®) Contents of A, H and L registers are 25, 05 and 01, respectively. (UPS LES. Et, 2007) ‘Consider the program given, which ransfersa block of data from, ‘one place in memory to another MVIC OBH stax D Lxtn 2400 INR L txip (3400 INRE Li:Mov AM perc INZLI ‘What ste wot auaber of memory accesses (ncuding instruction fetches) earied out? @ 118) 140 9B Ww 108 use ues bn, ams, ‘The content of some of the némary cation in an 885A based system ae given below ‘Address (Con * 6H r 26FF o 2700 a 2701 B 2702 om ‘The content of stack (SP), program counter (PC) and (H, C) are 2700 H, 2100 H and 0000 H respectively. When the following. Sequence of instruction are executed 2100H : DAD SP. ‘2101 H: PCHL the content of (SP) and (PC) at the end of execution will be (@) PC =2102 H, SP = 2700 H. (@) PC =2100 H, SP = 2700 H. {(@) PC=2800 H, SP = 267 H (@) PC=2,A02 H, SP = 2702 H. (OxTE Ee. 081 A portion ofthe main program ocala subroutine SUB in an B08S, environmentis given below. Lx LP:CALL D, DISP SUB Its desired that contol be returned to LP + DISP +3 when the RET instruction executed the subroutine. The set of instructions thatprecedethe RET instruction inthe subroutine are @ POP D () POP H DAD H DAD D PUSH D INX INK H INX PUSH H ‘Answers: 182. (0), 183. (c), 184. (0), 185. (2), 186. (c), 187. (0), 188. (€), 189. (c), 190), 191. (0, 192. (6),6618 cunstion Bank in Elctical Engineering (POP ) XTHL, DAD D INx D PUSH H Ix D IX D XTML — (eurees om 193. Whena ‘CALL addr’ instruction is executed, the CPU caries out thefollowiug sequential operations internally Noter (®) means content of register R (i) means conten of memory lacaion pointed by PC means Program Counter ‘SP means Siac Pointer @) (SPyincremented (6) (PC) Ade (PC) — Addr (SP) — PC) sry = PO) (SP)incremoned (©) PO) Addr (@ (SP) — PO) (SP) incremented (SP)incremented (SP) = PE) (PC) © Addr (OsTE ex sn) 194, Microprocessor based instruments canbe ured to measure (@) temperature only. (b)_ pressure ely (©) flow ony. (@) allt quantities a (2,4) and), TWMLLE Se Decor ad i Meco Sommer 32) 7 segment display. The digits are ofreshed rato! SOO He, The ON time for each digit wsuined equal is @ 4x10 () 04x 103s © 107s, (@) 25x 102s, Turse tes net Statement for Linked Answer Questions (196-197): ‘The associated Figure shows he two types of rotate right instruments RL, ‘22available ina microprocessor where Reg sa8-itroister snd Cis the cary bit. The rotate let instructions Li and L2 are similar except that C now links the mest Reg instead of the least significant 196. 17. fa . Cee ignifcantbit or ‘Suppose Reg contzns the 2's complement number 11010110. If this numbers divided by 2 the answer should be (@ o11o1011 (} Lo019101 (© t01001 G) ENOIOLL exrees. 2900 Such adivision can be correctly performed by the fllowing set of ‘operations @ 12,R.R1 () L2,RLR2 (©) RO,LIRI (@) R12, RD (care ex, 2007 Answers: 93. (@), 194. (8), 198. (8), 196. (), 197. 1, (Ar Analog computers are more widely ys it cdtnparison to Aigital computers (Analog computers are efficei in eontinous calculations such differentiation ai igegation, 2 (Ak Digital computeryart wore widely used in comparison to analog computers, (Ry: Digital compares are more accurate than analog computes. 3. (A): Suck is a group of memory locations in RAM used for temporary storage of data. (R): PUSH and POP instructions are used to send and retieve data from stack. (OPSC.LES. Et, 206) 4 (Ay: STACK isusedo temporarily stor the dtain RAM locations specified by the programmer in main program, (R): PUSH and POP instructions are used to send or retieve the data fom the STACK. [UPS Es EE, a 5. (Ay: Analog to digital converters ate used to interface ‘microprocessor to analog signals (R}: Many applications in real world produce signal analog in tre, Twrse.LEs, R “The adder is geared for doing subtraction alone, Semiconductor memories ate prefered. ‘Semiconductor memories ae non-volatile andof large size, Magnetic cores are generally used in main memory of adigi- talcomputer. Magnetic cores ae slow and volatile : Read only memory (ROM) is a random access memory. ‘Time taken to acess any location of ROM is the same [UPS LES. Ect 9) Each memory cell ofa DRAM requires refreshing every 2,4 ‘or ms or its data wil be lost. DRAM stores Isand Oss charges on small MOS capacitor ‘which has tendency to lek of charge alter a period of tie, TUPSC- TES. Bt 208) DMA fs faster than ether Interrupt initiated HO or Piling based UO for very lage data transfers, DMA takes contotofthe system buses and need no proceso imervenion during the data transfer. UPS LS e-1, 2007) A subroutine isa program writen separately from the main program to perform function that occurs repestedly inthe main program. ®y ws Armswers: L(A), 2. (0), 3. (b), 4 (0), S. (8), 6 (2), 7. (©, 8. (0), 9.) HO. (2), HL. (@), 12. (0),(Ry: A subroutine ean be calle hy a CALL ins-ction, Wase tas 2071 a. coisas EB (4): Address bass uniairectiona (Ry: Databucis bidive=ona lurse.1es Rh 2am) 13: (Ax Dasfow mus xlitnasim tion, 22 (A): Thpot adress in INOUT instrtion i bit eee (Teast ysis doplestdinmastine ee for NIOUT 14. (A): D-fip-flops are used as buffer rgistes. Rees (eel ers he Danes 25, (Ay: An WO device connected o microprocessor in JO mapped @®: Dstip-ops, municoeon, DO mote san 8 bit port adres. 1S. (A): Dflip-los are seo struct a bles registers, {): Micrmprocessor bated system design uses concept Of zero (8 Baferepsers are used sore nar word epoca ing {UPSE. Les BE, 208) Turse ts neuen te) 24 (AY: Ake speciation of any memory devi acess ime 16, (AY: Binary search function canbe easily implemented ui {R): Tastes tineofhe memory mst bere thane access cee’ dna : time ofthe microprocessor. TUPSC.LES. EReUL, 2010) (By: Recursion is based on number of elements in array to be 25. (A): Port B of 8255 A can only be used as input port. seared (use tes ern. €®): Porc can only be operate in Mode Oar Mode 17. (A: The development of micoroceor based prod eu ‘use 188 et, an the design of pcgram andthe hardware 26, (A) The fequeney of OES system is V2 of he ryt reqiency. (® Thedesineffor fran lstronic product flows he same (By: Miroprocesor 8085 rues two phase clock. base steps sen the development of software. (urse.ues eect ane ursc ins ETE, m0 : eee Gentaffetatoten 7% (AY: Isrucion SIM is necessary to implement the interns the execution of the following couple of instructions. ie t Mv 3.03 (®): INTR requires external hacéwaeforipplementtion, Mov AB {URS urs ei, 2m 2%. (A): STMinsruction cannot be we fable orange priory €®: After th execution of dtatranser instruction, ergs Set if the accumulator content is zer0.(U2S.C.LES. EFI, 2903) oes 19, (A): Neumann machines ae called Control Flow Computes GO INTR ie pease goog neue PIN, (R}: Instructions are executed sequentially as controlled by * (UPS. LES, EXAM, 2010) program coune. Turse iesetea ae — 2 (A): Mongetabie mivibrators (IC 74121) are used in 20, (A): Ina microprogammed CPU, each machine instruction is tnleropreesir based system for frequency measurement exerted ea time nerpce {Rx Microprocessor counts he mn oft sgnal/scond (By: Realtime interpreter helps toachievehigh dere paras twine specie interval though ISR inmicrprogrammedcontol, (urs. tes er 307 Turse: ues neta mowers: 13. (014 (0), 55. (0) 16 (0) 17) 18), 19. (20 0B. 0), 22. (0), 23. (), 24), 25, 260) BT. @, 2B (OL2B. 1 “Soe List Used toindicate memory location, A combination of eters, symbols and numerals ‘A. Monitor program. 1 BL Assembler. 2, ©. Mremonic. 3, A program that translates + symbolic instructions into binary equivalent. 1. Programeounter. 4. An operating system, Cider Ge cee) @ 4 3 1 ® 4 3 4 2 M 8 on 3 @ 34 2D yursees.etea, aes List List (Instructions) (Application) A SIM 1. 6bitaddition, Inalizing the stock pointe. DAA 3. Serial ouput data, D. SPHL 4 Checking the curentinterrupt ‘mask settings 3. BCDaddtion, ce A cree @ 5S 4 2 4 Os 1 3: Os 1 2 4 @ 3ST upse.tes ex 200) List List2 (Type of Memory) (sed as A. DRAM 1. Cache memory BL SRAM 2 Main memory. C. Parallel Access Registers 3. BIOS memory. D. ROM 4 CPU register. Answers: 1.(0),2.(0).3.(0),GS ‘Question Bank in Eiectrical Engineering Cues? A OB © oD @ 1 4 2 3 ® 3 42 4 @ 1 2 4 3 O 8s a a Wrscres een, 20m 4 List List Alnteerupt) Property) RST 7S ‘None maskable RSTSS age sensitive, INTR Level sensitive . TRAP Non-veetored. eA pcp 1 3 4 2 24 a a 23 4. Lurseiesee.nane 5% List List2 (Feature of Instruction) (astruction) ‘A. Maskable interrupt LL RSTSS B. Signal. 2 XTHL © nstruction, 3 SD D. | Memory location O02CH. 4. RST6S Codes: AB COD @ 4 1 2 3 oo oe oY © 4 3 2 4 @ 2 1 4 3 eurscrseenawn 6 List List2 ‘A. Modified duringfetch phase. 1. DI B. Holds subscripts of ary 2 Ds ©. Needed by the DEBUG program. 3. IP D. Caleuatesadéressesofdata 4. TE indata-segment Codes! AB OC Ob @ 2 4 1 3 ® 3 1 4 2 Ce 4s O 3 4 1 2 mpscamRadee 2 List Hist 2 aterrupts) —__(Corresporing.Characteristics) A. TRAP 4. Laveleiggered. BO OINTR 2° Non mashable, © RsT75 3. Forinereasing the number ofinterupts. D. RST6s 4. Positive edge wiggered, Gis A Bb Cc oD Ot 6 gf ® 1 4 3 2 © 4 @ 2 3 4 yurserrs essen List List2 (Microprocessor Pin) (Signals on Pin) A. TRAP Le Interrupt BL HLDA 2 Intalizing. 10. u. 2 c.RESET Dale Codes: A on o 3 oO 1 G3 List Alnstruction Code} A. JUMP 2021 H B LDAXB c IN1OH © © Oo List 1 (Addressing Mode) A. Implicit addressing. Bi. Registerindiect. ©. mmeie, D. Directaddressing Codes: AB @ 44 ® 4 '2 o 36 @ 3G A on 4 2 4 Soe 2 Sk 2 Codes: A (aes 3 oOo 4 @ 4 vosee 3. Enable 4. Memory access, D Neaea 1 3 1 turscuss.e6-.2009) List 2 (Adaressing Mode) Direct addressing. Immediate addressing. Indirect register addressing. 4. implicit addressing. D 2 4 2 4 tursc.urs eet 2009) List2 > nstruction) IMP 3 FAO H. MOV ADM LDA 03 FCH RAL D. 3 3 4 4 ursctsseenos List2 (ype of Addressing) Direct addressing. Register addressing. Implicitadaressing, Reiser indirect addressing, Immediate addressing, D oo c 2 1 1 2 3 1 3 3 (URSc.tes ex 209) List 2 (Operation) Exchange the top ofthe stack with the contents of HL pir Exchange the contents of HL with those of DE par. ‘Transfer the contents of HL to the stack pointer, ‘Transfer the contents of HL to the programme counter, D See eee -eeHe 1 1 2 uPScusera,aen Answers: 4. (€), 5. (€, 6. (0,7 (8, 8. (©), 9, (b), 10. (0), Hh. (12. (0,Microprocessors &; Bret rue(T) / & alse(F) Bype @ uestions 1. Computers are programmabie calculators 2 Analog computers operate in ral work and perform operations like adition, scalar multiplication and imegraion, 3. The basic components of a modern digital computer ere central processor and VO devices, 4. The processing componeat of microcomputers « microproces- '. central processing unit (CPU) ofa computer consists of contol ‘and arithmetic logic unit an primary storage. 6 al er is a smell computer andhas the basic elements ~ microprocessing uni, memory and inptloutput devices 7. The arithmetic and logi wit controls the flow of programs and data in and out of the memory. 8. Theretrcva of information from she computer i define asthe ouput. ‘An bit accumulator ean tore up 0255 integers, 10, Inaregiste the flip-flops ae connected in paraliel. 11, A PCeounts the number of programs run after stating. 412, Mest operating systems for microprocessors permit mult-pro- ‘ramming. 13, Maemonic symbols are ase to assist human memory. 14, Semiconductor memories are non-volatile, 415, The contents of ROM ae easily changed 16, Secondary storage is volatile, 17, Primary storage is non-vlatile, 18, Disks are connected directly tothe CPU. Eee 19. In comparison to secondary storage, primary storage is fast and expensive. .Systein software is more yeneral than the epplcation sofware, Punched cards are inexpeasive as data entry media “Magnetic disks expensive n comparison to magnetic tape, ‘Compilers used in microcomputers are classified as aplication softwares ‘Compilers nd inespeters ae themselves programs. Aninterpreter translates high evel language source program line byline executes cach ine immediatly. FORTRAN is one ofthe oldest high level language. 1. COBOL is widely used in scientific applications Microprocessor caries out both logic and arithmetic operations, .DACisan important part ofthe microprocessor. Four byt instruction not re forthe 8085 mlkroprocessor. 1. Assembly language is used for progratming in an 8O8S microprocessor. ‘The memory chips used in migfOprecetsor based units are only RAM. Accom nn och asm pr tbe ‘maintained bythe ALU. . The CPU contol all inpur, output and processing. ‘Registers aed counters are similar in the sense that hey both count salses and store binary information. 5. Insimicroprogranmmed CPU, each machine instructions executed by realtime interpreter Answers: A. (2 (1), 3. (1), 4.1), 5. (1), 6. (1. 7 (F&M), 94(D), 10. (F), 1 (12. (F), 13. (1), 14), 1S. (P16. (F). 17. ©) 18. ), 191), 201), 2 221, 28.24), 251), 26 (1) 27 F281), 298), (1 B11), 3), 33. (DMD, 36.0), 36.0, 1 ‘The physical part or electronic circuitry ofa computer system is called (ardware/achine) 2 Intel 8085iea bit microprocessor. {41 Somme 94 3. isthe heart of an analog computer. 4. A microcomputer comprises the following elements: @ () random access memory (c) ead only memory (@)inpuoutput devices and (e) interface components MILE Sommer 9) 5. Themost common input device used today i the 6. The organisational structure of «microprocessor is called the ‘7. Whena number of inputs isto be processed by the microcomputer, a is used, (AMULE Se Beco an He, Mearns Water 1999) 8 DiAconverer, constituent of «microprocessor. 9. Ina microcomputer, sits heart, 10, The central processing unit of «small eomputer system, including ALU and contol functions on a single LS chip is known as 11, The register which stores the operand execute an instretion with the help of other registers and memory is called the, 12, Thesize ofthe memory, amieroprocessor can accessis determined by the numberof. ines the processor bas. (ASCLE Rmte of Hector & Inaramitton Sommer 1998& > 13, A progremme witen in machine langue salle the tion Bank in Electrical Engineering program. 14, A setof intrietons written in computer language i called the 15, Number of cards read por minute by acard reader may be of the order of 16, The flow of ditatakesplceon busine micoprocesion based system. TAME Se Bhat nd ke Meret Some 98 17, 18085 microprocesscr itermups are mavkable. 18, Thenumber ofits equied to addres 4k memory is_ 419, Inan bit microcomputer, the ferch eyes required to fetch an 8 byte instruction wll be va) keeps i microprocessor. 21. The imerrupt pin TRAP of «8085 microprocessor is 22, The equipment attached to CPU which computer ean access are called the 23, Analog computers are used primarily in ‘control and pplication. 7 20, track of next instruction tobe executed na Analog cosapater podces ite results inthe formet___. printed copy of computer oupat is call the MR stan for register, “The development ofthe programs for various requirements is called the A source program ithe program written in langage. Prograns for applications are normally written i lan 3. Computer equipment and peripheral are sensitive to temperate yaaa .Thecontents of ROM are_. “Tsay the most popular microcomputer storage media are the ars dish and the “The main advantage of disk sts large __- Appunched card bas. sows and__eolumns. ‘A__s translating program that converts the souree pro- ‘amintoan object program. “The most busines oriented language i,