EE524 Nano Electronic devices

Project: Simulation of a DGMOSFET

Report Submitted By: Kinza Batool 18060018
Malik Faizan 18060022

Run the Double gate (extremely thin SOI) MOSFET example with all default parameters with
the given bias conditions
 Threshold voltage (V th) using Id vs. Vg plot [You can define threshold voltage to be the
gate voltage when I ON =10 μA /μm ]

Threshold voltage is Vt= 0.244V as shown in the plot

 ON current ( I ON ) [when both gate and drain voltages are high i.e., > V th]

We selected Vg = Vd = 0.3 V which is greater than threshold voltage (Vt=0.244V)

I ON = 1477 uA/um as shown in plot

 OFF current ( I off ), when both gate and drain voltages are 0]

OFF current ( I off ), when both gate and drain voltages are zero = 0 uA/um (zero)

 OFF current ( I off ) when gate voltage is 0 but drain voltages is > V th]

We selected Vd = 0.301 V which is greater than threshold voltage ( Vt=0.244V) and

Vg= 0V.
I off = 29.6 uA/um as shown in plot
  Extract the value of DIBL from the 1st subband energy plot at different Vd

DIBL can be calculated by taking horizontal shift in subthreshold regime, divided by the change in Vd.
We selected Vd of 0.501v and 0.201v to plot the curves.

DIBL = 30(mv)/0.501-0.201 = 100 mV/V

Ids vs Vg Plot
10 4

Vd=0.501v

10 3
Ids(uA/um) on log

Vd=0.201v
10 2

30mv

10 1
-0.05 0 0.05 0.1 0.15 0.2 0.25 0.3
Vg(v)
  Plot Id vs. Vg plot at (i) low Vds and (ii) high Vds. Calculate subthreshold swing for both
cases

Subthreshold swing is the gate voltage change needed to induce a drain current change of
one order of magnitude

Low Vds :
Vds=0.001V
Id=1uA/um at Vg=0.0515 V Id=10 uA/um at Vg=0.2444 V
Subthreshold Swing = 0.2444-0.0515 =192.9 mV/decade
High Vds :
Vd=0.501V
Id=100 uA/um at Vg=0.03695 V Id=1000 uA/um at Vg=0.2207 V
Subthreshold Swing = 0.2207-0.03695 =183.75 mV/decade
  Look at 2D electron density along the channel. Multiply this with q to get mobile charge
density in Coulombs/c m 2. Compare with the analytical expression we derived for mobile
charge when Vg > Vt.

From 2D electron density along the channel txt file, at Vg = 0.3v and x= 0nm:
N2D/cm^2 = 2.731xe*12.
mobile charge density = N2D*q =2.731xe*12 x 1.6xe*-19 = 4.36xe*-7 C/cm^2
Theoretically Qn=Cin(Vg−Vt )

At Vg>Vt and Cin=2Cox

εox∗8.85 × 10−12 −6
Cox= =3.45× 10 F at tox 1nm
tox

Cin=2× Cox=6.9 × 10−6

Qn=6.9 ×10−6 ( 0.3−0.2444 )=3.83 ×10−7 C /cm2

 Shortly describe the main issues that you see in the design of this MOSFET

The first issue with this DGMOSFET is that the value of DIBL is high. Also the
subthreshold swing is large and increases for smaller values of Vds which means high
leakage, and high energy. Ioff/ leakage current is also high for this design.

 Run the Nanomos simulation while modifying each of the above parameters (change only
one parameter at a time) and record its impact on short channel effect in the table below:
Graphs and calculations showing the table contents are given after the table.
DIBL Ioff
Defaul Ioff modifie
t DIBL % default d %
Default Modifie (mV/V modified improveme (uA/um (uA/um improveme
  Parameter value d value ) (mV/V) nt in DIBL ) ) nt in Ioff
1  Gate length  9 nm  20 nm  100  16.6  83.4  29.6  0.53  98.2

 Gate oxide  0.5

2 thickness  1 nm nm  100  33.33  66.67  29.6  11.3  61.8

 Dielectric
3 constant  3.9  5   100  83.33  16.67   29.6  14.6  50.6
 Source/drai
n doping  Almost
concentratio  2xe*2  2xe*1 negligible
4 n 0 8   100 *     29.6  11.3  61.8

* DIBL is significantly increased by increasing doping concentration if channel length becomes under
25 nm. Here we decreased the doping concentration and DIBL became almost negligible.
Calculation of Parameters in Table:
1- Gate length =20nm for both
i) Ioff from txt file = 0.53uA/um (At Vd > Vth = 0.301v)
ii) DIBL = 5(mv)/0.501-0.201 = 16.6mv/v

Ids vs Vg Plot

10 1
Ids(uA/um) on log

Vd=0.501v

Vd=0.201v
10 0

-0.02 0 0.02 0.04 0.06 0.08 0.1

Vg(v)

2- Gate oxide thickness = 0.5nm for both

i) Ioff from txt file = 11.3ua/um (At Vd > Vth = 0.201v as Vth is lowered
now to 0.1v)
ii) DIBL = 10(mv)/0.501-0.201 = 33.33mv/v

Ids vs Vg Plot

10 2
Ids(uA/um) on log

Vd=0.501v

10 1
Vd=0.201v

10 0

0 0.05 0.1 0.15

Vg(v)
3- Dielectric constants = 3.9 to 5 both

i) Ioff from txt file = 14.6 ua/um (At Vd > Vth = 0.301v)
ii) DIBL = 25(mv)/0.501-0.201 = 83.33mv/v

Ids vs Vg Plot
10 4

10 3
Ids(uA/um) on log

Vd=0.501v

Vd=0.201v
10 2

10 1
-0.05 0 0.05 0.1 0.15 0.2 0.25 0.3
Vg(v)

4- Source/drain doping concentration 2xe*20 to 2xe*18

i) Ioff from txt file = 11.3ua/um (At Vd > Vth = 0.201v as Vth is lowered
now to 0.1v)
Ids vs Vg Plot
10 3

10 2
Ids(uA/um) on log

10 1

10 0

10 -1
-0.05 0 0.05 0.1 0.15 0.2 0.25 0.3
Vg(v)
ii) DIBL is significantly increased by increasing doping concentration if channel
length becomes under 25 nm. Here we decreased the doping concentration
and DIBL almost became negligible.
Gate Length:
With the increase in gate length the saturation drain current decreases, thus
reduction in gate length results in more DIBL. Also, if gate length is less then channel length
then gate will lose control of the barrier height.
Gate Oxide Thickness:
Thinner gate oxide will cause high drain current and will shift Vth to lower value. Ioff
will also low for thin gate oxide layer. Thin layer has better control of the barrier height of
the channel.
Dielectric Constants:
If the dielectric constant of the SiO2 oxide is increased the device shows better short
channel effects.
Source/drain Doping Concentrations:

No idea why dibl and ioff are improving due to doping.