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Design Verification
Design Verification
⃞ Check with the high-level documentation if all the requirements are translated into design properly or
not.[1]
⃞ 90% of design is based on some reference design, all essence of the original design is
captured properly.[2]
⃞ The remaining 10% of the schematic is simulated or logically evaluated.[3]
⃞ Check the datasheet fine and app notes for all ICs.[4]
⃞ Pull-ups on all open collector/open drain outputs.[5]
⃞ Check mating connectors for the same pinout.[6]
⃞ Estimate the total current consumption.[6]
⃞ All no-connect pins on IC’s labelled NC.[7]
⃞ Unpopulated parts annotated and enclosed by the dashed-line box on schematics.[8]
⃞ Wires exist between all connected pins/ports (no direct pin/pin connections).[9]
⃞ Polarized components checked for connected polarity.[10]
⃞ Check pin numbers and pin type assignment of all custom-generated parts.[11]
⃞ Check for single nets.[12].
⃞ Check for multi-driven nets.[13]
Notes: -
pg. 1
⃞ Check all the specific instructions are noted down near each component/net that can be
utilized in layout e.g. High-frequency net, matched impedance net value, thermal requirement
etc. [15]
⃞ Adequate bypass cap for each IC.[16]
⃞ Electrolytic and tantalum capacitors checked for no reverse voltage.[17]
⃞ Sufficient capacitance on low dropout voltage regulators.[18]
⃞ Check for the ferrite bead/resistor current carrying capacity used in power line.[19]
⃞ Ensure that MLCC used are having at least twice the voltage rating than required.[20]
⃞ Ensure Tantalum/Electrolytic capacitors used are having at least 1.5 times rated voltage than
required.[21]
⃞ Ensure that high-frequency high power devices powered by a separate regulator with(/or)
adequate filtering.[22]
2 LAYOUT CHECK: -
⃞ Verify if every signal has a proper return path available. There should be no break in ground
signal.[23]
⃞ Foot print dimension check.[24]
⃞ Check hidden power and ground connections.[25]
⃞ No power or ground loop exists. [26]
pg. 2
⃞ All outside world I/O lines filtered for RFI.[27]
⃞ Separate analog signals from noisy or digital signals.[28]
⃞ Check maximum power dissipation at worst-case operating temperatures. find if heat-sink is
required.[29]
⃞ Automotive powered devices must withstand 60 to 100-volt surges.[30]
Note: Isolation is not always necessary for design, use engineering judgement to decide. Magnetic
isolation increases susceptibility.
3 BOM:
⃞ Each component has quantity, reference designator and description.[31]
⃞ Suggested and alternate manufacturer(s) listed.[32]
⃞ Price and availability checked for each component.[33]
⃞ Part is verified against schematic value and assigned footprint.[34]
4 TESTABILITY:
⃞ Ability to isolate/ off the power supply for a certain section of design to test.[35]
⃞ Diagnostic resources by design (LEDs, serial ports, etc.) even if unpopulated by
default.[36]
⃞ Test points on power and ground lines.[37]
⃞ The filename on each sheet.[38]
⃞ Special PCB or parts list information entered for each component if required.[39]
⃞ Power and ground pins listed for each component.[40]
⃞ Title block completed for each sheet.[41]
⃞ Schematic should also contain logos that are supposed to be printed on PCB.[42]
pg. 3
⃞ Text should not overlap wire or symbol graphics on schematics.[43]
5 SCHEMATIC VERIFICATION: -
5.1 PMIC
Two 0-Ohm resistors connected to SDA & SDL (not used connection since to programming
needed).
INT pin (19) pulled up with 4.99K-Ohm resistor since its open drain.
pg. 4
CLKIN pin (3) connected with 0-Ohm resistor to SOP2 in AWR IC.
Enable pins (7,15,2) all pulled up with 4.99KOhm and 10KOhm resistors.
Power circuit:
1. C71
2. C72
3. FL2
4. C66
5. C67
6. L5
7. C64
8. C62
9. FL1
10. C63
11. C65
12. C68
13. C69
14. C70
15. R28
16. R31
17. R30
18. C80
19. R33
20. IC1
21. R26
pg. 5
22. C61
23. L6
24. D1
25. C73
26. C74
27. C75
28. C76
29. C77
30. C78
31. R27
32. R29
33. R32
34. C79
35. C90
36. C91
37. D3
38. R36
39. DS2
40. Q1
41. R70
42. R71
43. R34
44. SW1
45. R37
46. C81
47. D2
48. R38
49. R35
50. DS1
pg. 6