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uvm_component:
Quasi Static Entity (after build phase it is available throughout the simulation)
Always tied to a given hardware(DUT Interface) Or a TLM port
Having phasing mechanism for control the behavior of simulation
Configuration Component Topology
uvm_object:
Dynamic Entity (create when needed, transfer from one component to other & then
dereference)
Not tied to a given hardware or any TLM port
Not phasing mechanism
Any class deriving from uvm_component may implement any or all of these callbacks, which
are executed in a particular order.
Dynamic
Associative Array
There is a built-in objection for each in-built phase, which provides a way for components
and objects to synchronize their testing activity and indicate when it is safe to end the phase
and, ultimately, the test end.
The component or sequence will raise a phase objection at the beginning of an activity that
must be completed before the phase stops, so the objection will be dropped at the end of
that activity. Once all of the raised objections are dropped, the phase terminates.