Mixed-Signal-Electronics

PD Dr.-Ing. Stephan Henzler

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 Chapter 8
Oversampled Converters
Sigma-Delta Modulator

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 2. Order Noise Shaping

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 Noisespectrum

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 Simulation with Matlab/Simulink

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 Simulation for OSR=32

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 Output Spectrum of ΣΔ-Modulator for
Sinusoidal Input Signal

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 Output Spectrum of ΣΔ-Modulator for
Sinusoidal Input Signal

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 Input Level Dependent SNR

2. Order

1. Order

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 Tones

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 Tones in Frequency Domain
power spectral density 0

-50

-100

-150
0 0.1 0.2 0.3 0.4 0.5
frequency/sampling frequency

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 Dithering

pseudo random signal

 affected by noise shaping, i.e.
noise power mainly shifted to high frequencies
 SNR only slightly reduced

 Reduce the risk of tones by randomizing (artificially) the

comparator input signal: Dithering
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 0 0
power spectral density

power spectral density

-50 -50

-100 -100

-150 -150
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
frequency/sampling frequency frequency/sampling frequency

0 0
power spectral density

power spectral density

-50 -50

-100 -100

-150 -150
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
frequency/sampling frequency frequency/sampling frequency

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 3. Order Single-Loop ΣΔ-Modulator
(not cascaded)

 Deviation from „ideal“ transfer functions due to stability

requirements J. Sauerbrey

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 STF of 3. Order ΣΔ-Modulator

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 Noiseshaping of Various ΣΔ-Modulators

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 Cascaded ΣΔ-Modulator (Multi stAge noise Shaping)

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 Noiseshaping of Various ΣΔ-Modulators

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 3. Order MASH Structure

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 Scaling of ΣΔ-Modulator
1. If inputs of integrators become too large for a significant time
the integrators saturate
non-linearity  clipping  strong non-linear distortion
(Comparator should be only non-linear component)
2. Exploit full dynamic range for good SNR

 Modulator Scaling:
Linear transformation so that
 saturation of integrators is avoided
 dynamic range is exploited

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 9000
12000
8000

10000 7000

6000
hist(S1)

hist(S2)
8000
5000
6000
4000

4000 3000

2000
2000
1000

0 0
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 -4 -3 -2 -1 0 1 2 3 4
S1 S2

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 x 10 x 10
2.5 2

1.8

2 1.6

1.4

1.2

hist(S2)
1.5
hist(S1)

1 0.8

0.6

0.5 0.4

0.2

0 0
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 -1.5 -1 -0.5 0 0.5 1 1.5
S1 S2

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 2.5 2

1.8

2 1.6

1.4

1.5 1.2
hist(S1)

hist(S2)
1

1 0.8

0.6

0.5 0.4

0.2

0 0
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -1.5 -1 -0.5 0 0.5 1 1.5
S1 S2

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 Application of ΣΔ-Modulator
in Data Converters (ADC)

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 ΣΔ-Analog-to-Digital Conversion

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 Decimation Filtering

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 Sinc-Filter
Basic low-pass filter averages N subsequent samples:

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 Sinc Filter Transfer Functions

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 Sinc Filter Transfer Functions

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 Sinc Filter Implementation

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 Implementation of Sinc-Filter

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 ΣΔ-Digital-to-Analog Conversion

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 ΣΔ-Digital-to-Analog Conversion

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 Multi-Bit Sigma Delta Converter

 Replace single-bit quantizer by multi-bit quantizer

Quantizer: Comparator  Flash ADC
Feedback DAC: implicit  real DAC
 Comparator and DAC nonlinearity become critical
 Countermeasures: Dynamic element matching, mismatch
shaping, trimming, (digital) correction
 Benefit: Reduced OSR and/or better resolution
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 Continuous Time Sigma-Delta Converter

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 Comparison of Discrete- and Continuous
Time Sigma-Delta Converters
Discrete-Time Continuous-Time

Anti-Aliasing Filter Explicit anti-aliasing filter Implicit filtering

(AAF) required
Sampling Sampling at input
 low jitter & full linearity
required for sampler
Max. frequency and All transients must settle
bandwidth of opamps within half of clock cycle,
quickly changing pulses
everywhere in circuit
 high bandwidth
requirements limit max.
frequency
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 AAF may be obsolete for
some applications
Sampling at comparator, i.e.
within ∑∆-loop
 sampling error subject to
noise shaping
Continuous time waveforms
5-10x relaxed bandwidth
requirements
 higher clock frequency
possible
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 Comparison of Discrete- and Continuous
Time Sigma-Delta Converters
Discrete-Time Continuous-Time

Jitter Only critical for sampler but Very sensitive to timing

not for rest of sigma delta variations of clock
modulator
Loopdelay Not an issue Very sensitive to loop delay

Switches Signal dependant on No switches

resistance

Signal dependant Not an issue Very sensitive  causes

comparator delay harmonic distortion

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 Comparison of Discrete- and Continuous
Time Sigma-Delta Converters
Discrete-Time
Feedback-DAC Low sensitivity to waveform
settling not critical
Process variations Filter transfer function
based on capacitor ratios
 very robust
Noise generation Switching generates noise
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Continuous-Time
Very sensitive to waveform
and settling, limits linearity
of modulator
Filter transfer function
depends on RC constants,
i.e. very sensitive to
variations
Reduced supply and ground
noise
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