Class Notes (Part 1)

CS201

Dr. C. N. Zhang
Department of Computer Science
University of Regina
Regina, SK, Canada, S4S 0A2
C. N. Zhang, CS400 2

I. DIGITAL CIRCUITS
1 Binary Algebra and Gates
1.1 Binary Algebra
An algebra that deals with binary variables and logic operations.
 All variables take on two discrete values 1 and 0 (binary variable).
 There are three basic operations: OR, AND, NOT dened as follows:
AND OR NOT
X Y X.Y X Y X+Y X X
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1

Figure 1: Truth tables of the three basic operations.

1.2 Logic Gates

X X
Z=X.Y Z=X+Y X X
Y Y
AND gate OR gate NOT gate or INVERTER

X 0 0 1 1

Y 0 1 0 1

(AND) X . Y 0 0 0 1

(OR) X + Y 0 1 1 1

(NOT) X 1 1 0 0

A
A B
B F = ABC C F=A+B+C+D
C D
Three-input AND gate Four-input OR gate

Figure 2: Some logic gates and their timing diagrams.

C. N. Zhang, CS400 3

2 Boolean Function and Simplification

 Boolean function: Boolean function consists of an algebraic expression formed with
binary variables, the constants 0 and 1, the logic operation symbols, parentheses, and an
equal sign. For a given value of the binary variables, the Boolean function can be equal
to either 1 and 0.
 Duality function f: f  is obtained by interchange OR and AND operators and
replacing 10s and 00s and 00s and 10s.
 Duality principle: if f1 = f2 then f1 = f2
If f1 and f2 are duality functions of two Boolean functions f1 and f2, then f1 = f2

2.1 Truth Table

A tabular representation of the Boolean function f (x1; : : : ; xn). It consists of a list of 2n
combinations of the n binary variables and a column that shows the values of the function.
F =X +Y Z

Table 1: The function truth table.

x y z F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

2.2 Logic Circuit Diagram

Logic circuit diagram is logic gate implementation of a Boolean function. For example,
X

Y F
Z

Figure 3: Logic circuit diagram for F = X + Y Z .

C. N. Zhang, CS400 4

2.3 Basic Identities of Boolean Algebra

1. X + 0 = X 2. X . 1 = X
3. X + 1 = 1 4. X . 0 = 0
5. X + X = X 6. X . X = X
7. X + X = 1 8. X . X = 0
9. X = X
10. X + Y = Y + X 11. X . Y = Y . X Commutative
12. X + (Y + Z) = (X + Y) + Z 13. X . (Y . Z) = (X . Y) . Z Associative
14. X(Y + Z) = XY + XZ 15. X + Y . Z = (X + Y) . (X + Z) Distributive
16. X + Y = X . Y 17. X . Y = X + Y DeMorgan Law

Figure 4: Basic identities of Boolean Algebra.

 All of these identities can be proved by truth table. For example, (X + Y ) = X
Y
Table 2: Truth tables to verify DeMorgan's theorem.
X Y X +Y X +Y X Y X Y X
Y
0 0 0 1 0 0 1 1 1
0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 0 1 0
1 1 1 0 1 1 0 0 0

 Simplication of Boolean functions using basic identities.

Example 1:
F = XY Z + XY Z + XZ
= XY (Z + Z ) + XZ by (14)
= XY
1 + XZ by (7)
= XY + XZ by (2)

Y
Y F F
Z
Z

F=XYZ+XYZ+XZ F=XY+XZ

Figure 5: Implementation of the Boolean function with gates.

C. N. Zhang, CS400 5

Example 2:
XY + XZ + Y Z = XY + XZ + Y Z (X + X by (7)
= XY + XZ + XY Z + XY Z by (14)
= XY + XY Z + XZ + XY Z by (12)
= XY (1 + Z ) + XZ (1 + Y ) by (14)
= XY + XZ by (7)
Example 3:
(A + B )(A + C ) = AA + AC + AB + BC by (14)
= AC + AB + BC by (8)
= AC + AB + ABC + ABC by (1 and 14)
= AC (1 + B ) + AB (1 + C ) by (14)
= AC + AB by (3)
Example 4:
(A + C )(B + C ) = AB + AC + BC + CC by (14)
= AB + AC + BC + C by (6)
= AB + (A + B + 1)C by (14)
= AB + C by (3)
 Find complement of Boolean function.
The complement of Boolean function f (x1; : : :; xn) denoted by f (x1; : : :; xn) can be ob-
tained by the following approaches:
1. Approach-1 (based on truth table): The truth table of f (x1; : : : ; xn) can be
obtained from the truth table of f (x1; : : : ; xn) by exchanging the values of 0 to 1
and 1 to 0 in the function value column.
2. Approach-2 (apply DeMorgan Law repeatedly):
Example-1: Find complement of function F = XY Z + XY Z .
F = XY Z + XY Z
= (XY Z ) (XY Z )
= (X + Y + Z ) (X + Y + Z )
= XX + XY + XZ + XY + Y Y + Y Z + XZ + Y Z + ZZ
= X + XY + XZ + XY + Y Z + XZ + Y Z
= X (1 + Y + Z + Y + Z + Y ) + Y Z + Y Z
= X +YZ +YZ
C. N. Zhang, CS400 6

Example-2: Find complement of function F = X (Y Z + Y Z ).

F = X (Y Z + Y Z )
= X +YZ +YZ
= X +YZ
YZ
= X + (Y + Z )
(Y + Z )
= X + ZY + ZY
3. Approach-3:
First, nd dual of f , f , and then complete each variable of f 
Example: Find complement of function F = X (Y Z + Y Z )
F  = X + (Y + Z )(Y + Z )
F = X + (Y + Z )(Y + Z )
= X +YZ +YZ
 Time delay of a gate: It is the time duration from the time of input signals arrived to
the time of output signal established. Example: NOT gate (5 ; 10ns); AND and OR
gate (10 ; 20ns).
5V

A B t
5V
∆t
t
5 ns < ∆t < 10 ns

Figure 6: Time delay of an inverter.

 Time delay of logic circuit: It adds up the time delay of all gates on a path from
input to output which requires longest time delay.
 Logic circuit cost: It depends on:
{ number of gates required
{ number of inputs for each gate
 Minimum cost logic circuit design:
{ minimum number of gates with minimum total number of inputs
 Goal of logic circuit design:
{ minimum cost and minimum time delay
C. N. Zhang, CS400 7

3 Simplification Using Map

3.1 Minterms and Maxterms
 Minterms: It is a product term in which all the variables (either complemented or
uncomplemented) appear exactly once.
 Maxterms: It is a summation term in which all variables (either complemented or
uncomplemented) appear exactly once.

Example:
MINTERMS MAXTERMS

X Y Z Product Term Symbol Sum Term Symbol

0 0 0 X Y Z m0 X+Y+Z M0
0 0 1 X Y Z m1 X+Y+Z M1
0 1 0 X Y Z m2 X+Y+Z M2
0 1 1 X Y Z m3 X+Y+Z M3
1 0 0 X Y Z m4 X+Y+Z M4
1 0 1 X Y Z m5 X+Y+Z M5
1 1 0 X Y Z m6 X+Y+Z M6
1 1 1 X Y Z m7 X+Y+Z M7

Figure 7: Minterms and maxterms for three variables.

 Relationship: The minterm and maxterm have relationship as follows:

mi = M i

3.2 Two Canonical Forms

Any Boolean function can be expressed as a unique sum of minterms or as a unique product
of maxterms. For example, nd two canonical forms of E (X; Y; Z ) = XY + Z .
1. Sum of minterms.
E (X; Y; Z ) = XY + Z
= XY (Z + Z ) + (X + X )(Y + Y )Z
= XY Z + XY Z + XY Z + XY Z + XY Z + XY Z
= XY Z + XY Z + XY Z + XY Z + XY Z
=  (m0 + m1 + m3 + m5 + m7)
=  m(0; 1; 3; 5; 7)
C. N. Zhang, CS400 8

2. Product of maxterms.
E (X; Y; Z ) = XY + Z
= (X + Z )(Y + Z )
= (X + Z + Y Y )(Y + Z + XX )
= (X + Y + Z )(X + Y + Z )(X + Y + Z )(X + Y + Z )
= M4
M6
M2
=  M (2; 4; 6)
Note:
if f (x1; x2; : : : ; xn) = m(i1; i2; : : :; in), then f (x1; x2; : : : ; xn) = M (j1; j2; : : :; jn ), where
fi1; i2; : : : ; ik g + fj1; j2; : : :; jlg = f0; 1; : : : ; 2n ; 1g and jm 6= in for all 1  m  l and
1  n  k.

3.3 Two Standard Forms of Boolean Functions

 Sum of Products (SOP) Form:
Any Boolean function can be expressed by a summation of product terms.
 Product of Summations (POS) Form:
Any Bollean function can be expressed by a product of summation terms.
Where each product term and each summation term may have one, two, or any number
of variables (literals).
Example-1: Rewrite the function F = AB + C (D + E ) in SOP form.
F = AB + C (D + E )
= AB + CD + CE
Example-2: Rewrite the function F = AB + C (D + E ) in POS form.
F = AB + C (D + E )
= (A + C (D + E ))(B + C (D + E ))
= (A + C )(A + D + E )(B + C )(B + D + E )
 OR-AND implementation:
Any Boolean function in POS form can be implemented by an OR-AND two level net-
work, where OR gate corresponds to the summation term and AND gate is for the logic
product.
Example: F = X (Y + Z )(X + Y + Z ).
Note: term of X does not need an OR gate.
C. N. Zhang, CS400 9
X

Y
F
Z

X
Y
Z

Figure 8: The logic gate for F = X (Y + Z )(X + Y + Z ).

 AND-OR implementation:
Any Boolean function in SOP form can be implemented by an AND-OR two level net-
work. Each product term requires an AND gate, the logical sum is formed with an OR
gate.
Example: F = AB + CD + CE .
A

C
F
D

Figure 9: The logic gate for F = AB + CD + CE .

3.4 Two-Level Minimum Cost Designs

 Simplied SOP Expression: It is a SOP form with a minimum number of products
and each product has the fewest number of literals.
F = AB + ABC + ABC + B
is a SOP but not simplied, because:
F = AB + B
= A+B
 Simplied POS form: It is a POS form with minimum number of summation terms
and each summation term has the fewest number of literals.
F = (A + B )(B + C )(A + C )(B + C )
is not a simplied POS form, because:
F = (A + C )(A + B )(B + CC )
= (A + C )B
C. N. Zhang, CS400 10

3.5 Karnaugh Map

Karnaugh map is a table made up of squares, each of which represents one minterm of a
function.
 Two variable map.
Y 0 1 Y 0 1
X X
0 m0 m1 0 XY XY X

1 m2 m3 1 XY XY X

Y Y

Figure 10: Two variable map.

 Three variable map.

YZ YZ Y

X 00 01 11 10 X 00 01 11 10

0 m0 m1 m3 m2 0 XYZXYZXYZXYZ

1 m4 m5 m7 m6 1 XYZXYZXYZXYZ X

Figure 11: Three variable map.

 Four variable map.

Y
YZ YZ
00 01 11 10 00 01 11 10
WX WX
00 m0 m1 m3 m2 00

01 m4 m5 m7 m6 01
X
11 m12 m13 m 15 m 14 11
W
10 m8 m9 m 11 m 10 10

Figure 12: Four variable map.

C. N. Zhang, CS400 11

3.6 Map Manipulation

 The key idea in the formation of the map is that any two horizontally and vertically
adjacent squares corresponding to two minterms dier in one variable only.
Note: Adjacency of the map includes right-most, left-most, top-most, and down-most.
Example-1: In the three variable map, m0 and m2 are adjacent, and we have:
m0 = XY Z
m2 = XY Z
m0 + m2 = XZ
Example-2: In the four variable map, m0, m2, m8, and m10 are adjacent, and we have:
m0 + m2 + m8 + m10 = WXY Z + WXY Z + WXY Z + WXY Z
= WXZ + WXZ
= XZ
Note: In general, if there are 2k adjacent squares, then their corresponding product has
n ; k variables.
 Prime Implicant: It is a product term corresponding to a 2k adjacent squares in the
map in which at least one square is not adjacent to any other adjacent squares (excluding
any sub adjacent squares of these adjacent squares).

Example: Consider f (X; Y; Z ) = m(1; 3; 4; 5).

YZ
X 00 01 11 10
m0 m1 m3 m2
0 0 1 1 0

m4 m5 m7 m6
1 1 1 0 0

Figure 13: Map for example m(1; 3; 4; 5).

There are three adjacent squares: (m4; m5), (m1; m5), and (m1; m3). Their corresponding
products are XY , Y Z , and XZ , respectively.
We say that XY is a prime implicant because there is only one square, m4, which does
not belong to these adjacent squares, (m4; m5). Similarly, XZ is a prime implicant. On
the other hand, Y Z is not a prime implicant because all its squares, (m1; m5), belong to
other adjacent squares (m1 belongs to (m1; m3), and m5 belongs to (m4; m5)).
C. N. Zhang, CS400 12

 Procedure (nding simplied SOP form):

1. Make '1' for those squares corresponding to the minterms of the function, mark the
rest of squares by '0'.
2. Find all adjacent squares which correspond to prime implicants (the number of
adjacent squares is power of two) and circle them together, write down their corre-
sponding products.
3. Find the largest adjacent squares on the map, circle them together, and write down
the corresponding products. Repeat this step until all 1's have been circled.
4. List all products and write them in SOP form.
Note:

{ Any square marked by '1' can be selected more than once, but at least once.
{ If there are 2k squares adjacent together, then k variables should be eliminated.
Example-1: F (X; Y; Z ) = m(1; 2; 3; 4; 5)
1. '1' is marked in each minterm of the function.
2. Find all possible adjacent squares which correspond to a prime implicant in the map,
write down the corresponding products, i.e., XY and XY .
3. There is only one square uncircled in the map (i.e., m1). The largest adjacent square
which includes m1 can be (m1; m5) or (m1; m3). Since both of them have the same
number of squares (i.e., two), we can pick up any one of them. Let (m1; m5) be the
chosen square and Y Z be the product. Now all squares marked by '1' have been
circled.
4. Write down the function in sum of product form: F = XY + XY + Y Z .
YZ
X 00 01 11 10

0 0 1 1 1 XY

1 1 1 0 0

XY YZ

Figure 14: The map for example m(1; 2; 3; 4; 5).

Example-2:
F1(X; Y; Z ) = m(3; 4; 6)
F2(X; Y; Z ) = m(0; 2; 4; 5; 6)
C. N. Zhang, CS400 13
YZ YZ
X 00 01 11 10 X 00 01 11 10

0 1 0 1 1

1 1 1 1 1 1 1

XYZ YZ XY Z

F1 = X Y Z + Y Z F2 = X Y + Z

Figure 15: The map of F1 and F2.

3.7 Don't Care Conditions

In some applications, a Boolean function is not specied for certain minterms which are referred
to as don't care items.
Example: Four bit binary code for the decimal digits has six minterms which are not used
(unspecied). In general, a Boolean function with don't care items can be represented by:
F = m(: : :) and D = m(: : :)
where D is a collection of all don't care minterms of F .
Example:
F (W; X; Y; Z ) = m(1; 3; 7; 11; 15) and D(W; X; Y; Z ) = m(0; 2; 5)
The procedure of map manipulation for functions with don't care conditions can be modied
as follows:
 In step 1, mark 'X' for those don't care minterms.
 In step 2 and 3, we can assign each 'X' as '1' or '0' to make larger adjacent squares.
Example: Y
YZ
00 01 11 10
WX
00 x 1 1 x WX
F (W,X,Y,Z) = Σ m (1,3,7,11,15)
D (W,X,Y,Z) =Σ m (0,2,5) 01 0 x 1 0
X
11 0 0 1 0
W
F=WX+YZ 10 0 0 1 0

Z YZ

Figure 16: The map with don't care.

C. N. Zhang, CS400 14

4 NAND, NOR, XOR, and XNOR Gates

X Y F
0 0 1
X 0 1 1
NAND F F=X.Y 1 0 1
Y
1 1 0
X Y F
0 0 1
X
0 1 0
NOR F F=X+Y 1 0 0
Y
1 1 0
X Y F
X 0 0 0
XOR
F
F=XY+XY 0 1 1
(Exclusive-OR) Y 1 0 1
=X Y
1 1 0
X Y F
0 0 1
XNOR X F=XY+XY 0 1 0
F
(Exclusive-NOR) Y =X Y 1 0 0
1 1 1

Figure 17: Logic gate symbols and truth tables.

4.1 Universal Gate (Circuit)
A gate or circuit is universal if all OR, NOT, and AND operations can be implemented by
this kind of gate (circuit) only.
Example-1: NAND is a universal gate.
NOT X X

X
AND XY=XY
Y

OR X Y=X+Y

Figure 18: Universal NAND.

Example-2: NOR is a universal gate.
NOT X X

X
OR X+Y=X+Y
Y

AND X+Y=XY

Figure 19: Universal NOR.

C. N. Zhang, CS400 15

4.2 NAND-NAND and NOR-NOR Implementation

 Conversions between NAND-NAND and AND-OR networks.
AB + CD = AB + CD
= AB CD
Any AND-OR network can be converted into a NAND-NAND network by:
1. replacing each AND (OR) gate by a NAND gate.
2. if there is a single input to the OR gate, then replace it by its complement.
Example:
A A
B B
E F E F
C C

D D

Figure 20: NAND-NAND implementation.

 Conversion between NOR-NOR and OR-AND networks.

(A + B )(C + D) = A + B C + D
= A+B+C+D
Similarly, we have that any OR-AND network can be replaced by a NOR-NOR network
and vice versa.
A A

B B

C C
F F
D D

E E

Figure 21: NOR-NOR implementation.

4.3 XOR and XNOR Gates

Exclusive-OR function is represented by the following logic equation: X  Y = XY + XY
Exclusive-NOR function is denoted by the following logic equation: X  Y = XY + XY
Note: its is easy to prove that XY + XY = XY + XY .
C. N. Zhang, CS400 16

4.4 Single Error Detection Using Parity Bit

Even (odd) parity bit: A parity bit is an extra bit for a binary message to make the total
number of 1's even (odd).
Parity bit generator: The circuit that generates the parity bit is called parity bit generator.
Parity bit checker: The circuit that checks the parity bit and the message in the receiver.
If the number of 1's including message bits and parity bit is even (odd), then there is no
error. Otherwise, it nds an error.
Example: 3 bit message (X,Y,Z), even parity bit.
P = X Y Z
C = X Y Z P

X X

Y Y
C
P
Z Z

Figure 22: Multiple input XOR functions.

5 Integrated Circuits
5.1 Digital Logic Families
 TTL: transistor-transistor logic
 ECL: emitter-coupled logic
 MOS: metal-oxide semiconductor
 CMOS: complementary metal-oxide semiconductor
5.2 Levels of Integration
 SSI: small scale integration (number of gates < 10)
 MSI: medium scale integration (10 ; 100)
 LSI: large scale integration (100 ; 5000)
 VLSI: very large scale integration (> 5000)
 WSI: wafer scale integration (> 30000 ?)
C. N. Zhang, CS400 17

6 Combinational Circuits
6.1 Denition
A combinational circuit consists of logic gates whose output at any time is fully determined by
the values of the inputs.

n inputs Combinational m outputs

Circuit

Figure 23: A combinational circuit.

Design Procedure
1. From the specication of the circuit, determine the number of inputs and the number of
outputs. Assign a letter symbol to each input and output.
2. Derive the truth table. The size of the table depends on the number of inputs and outputs.
The values of the outputs are determined by the specication of the circuit.
3. Obtain the simplied SOP form for each output using map approach.
4. Draw the logic diagram for all outputs.
Example-1: Design a combinational circuit with three inputs and one output. The output
will be in logic '1' when the binary values of the inputs are less than three. Otherwise, it will
be in logic '0'. Use NAND gates only.
1. Let X; Y; Z be the inputs and F be the output.
2. The truth table is as follows:
Table 3: Truth table.
X Y Z F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
C. N. Zhang, CS400 18

3. Map simplication:

XY
YZ
X 00 01 11 10

0 1 1 1
XZ

Figure 24: Map F = XY + XZ .

4. The circuit:
X
Y

Figure 25: Logic diagram.

Example-2: Design a code converter from a BCD code to excess-3 code.

1. BCD code : ABCD
Axcess-3 code: WXYZ
2. Truth table:
Table 4: Truth table for code converter.
Decimal A B C D W X Y Z
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
10 1 0 1 0 x x x x
... ... ... ... ... ... ... ... ...
15 1 1 1 1 x x x x
C. N. Zhang, CS400 19

3. Map simplication:

C C
CD CD
00 01 11 10 00 01 11 10
AB AB
00 00 1 1 1

01 1 1 1 01 1
B B
11 x x x x 11 x x x x
A A
10 1 1 x x 10 1 x x

D D
W=A+BC+BD X=BC+BD+BCD
C C
CD CD
00 01 11 10 00 01 11 10
AB AB
00 1 1 00 1 1

01 1 1 01 1 1
B B
11 x x x x 11 x x x x
A A
10 1 x x 10 1 x x

D D
Y=CD+CD Z=D

Figure 26: Maps for W; X; Y; Z codes.

4. The circuit:
A

B X

C Y

D Z

Figure 27: Code converter circuit.

C. N. Zhang, CS400 20

6.2 Half Adder

1. Input: X and Y
Output: S (sum) and C (carry)
2. Truth table:
Table 5: Truth table for Half Adder.
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
3. S = XY + XY = X  Y
C = XY
4. Logic diagram: X
S
Y

Figure 28: Logic diagram of Half Adder.

6.3 Full Adder

1. Input: X , Y , and Z
Output: S and C
2. Truth table:
Table 6: Truth table for Full Adder.
X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
C. N. Zhang, CS400 21

3. Map:
YZ YZ
X 00 01 11 10 X 00 01 11 10

0 1 1 0 1

1 1 1 1 1 1 1

S =XYZ+XYZ+XYZ+XYZ C=XY+XZ+YZ
=X Y Z = X Y + Z (X Y + X Y)
= X Y + Z (X Y)

Figure 29: Map for Full Adder.

S =X Y Z
C = XY + Z (X  Y )
4. Logic diagram:
X
Y S

C
Z

Figure 30: Logic diagram of Full Adder.

6.4 Parallel Adder

B3 A3 B2 A2 B1 A1 B0 A0

FA FA FA FA C0
C3 C2 C1

C4 S3 S2 S1 S0

Figure 31: 4-bit Parallel Adder.

C. N. Zhang, CS400 22

6.5 Decoder
It generates 2n minterms with n inputs.
Example-1: (2  4) decoder with enable input.
D0

A1

(2 x 4) Decoder
D1 A1 D0
D1
A0
D2 D2
E D3

A0 D3

Figure 32: A (2  4) decoder.

D0 = EA1A0, D1 = EA1A0, D2 = EA1A0, D3 = EA1A0
Example-2: Construct a (3  8) decoder from two (2  4) decoders.
(2x4) Decoder
0 0 D0
A0 2
1 D1
1
A1 2 2 D2
A2 Enable
3 D3

(2x4) Decoder
0 D4
20
1 D5
21 2 D6
Enable
3 D7

Figure 33: A (3  8) decoder.

Example-3: Any Boolean function can be implemented by a decoder and OR gate: F (X; Y; Z ) =
m(0; 1; 5; 6; 7).
0
(3x8) Decoder

1
X
2
Y 3
4
Z 5
6
7

Figure 34: Decoder-OR implementation of a Boolean function.

C. N. Zhang, CS400 23

6.6 Encoder
It does inverse operation of a decoder.
Example: 8 to 3 encoder.
Table 7: Truth table for octal to binary encoder.
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

D0 0
(8 to 3) Encoder

D1 1
A0
D2 2
D3 3
A1
D4 4
D5 5 A2
D6 6
D7 7

Figure 35: Octal to binary encoder.

6.7 Multiplexer (MUX)

It selects a binary information from one of many input lines and directs it to a single output line.
Example-1: 4 to 1 MUX.
Y = S 1S 0D0 + S1S0D1 + S1S 0D2 + S1S2D3
C. N. Zhang, CS400 24

Table 8: Function table for 4 to 1 MUX.

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

S0
S1

D0 Y

D1 S0
Y (4 to 1) MUX
S1

D2
D0 D1 D2 D3

D3

Figure 36: Logic diagram of (4 to 1) MUX.

Note: Let n be the number of input lines and k be the number of selection lines, then we
have n = 2k .
Example-2: Construct a (4 to 1) MUX by using (2 to 1) MUXs.
(2 to 1) MUX: Y Y = S D0 + S D1

(2 to 1) MUX S
D0 D1

(4 to 1) MUX: Y Y = S 1 S 0 D 0 + S 1 S 0 D 1 + S 1 S 0 D 2 + S 1 S3 0 D 3
= S1(S0 D 0 + S0 D 1) + S1( S0 D 2 + S0 D 3)
(2 to 1) MUX S1

(2 to 1) MUX S0 (2 to 1) MUX S0
D0 D1 D2 D3

Figure 37: Diagram to construct a (4 to 1) MUX from (2 to 1) MUXs.

C. N. Zhang, CS400 25

Example-3: (2 to 1) MUX is a universal circuit.

Proof:
(i) Inverter: Y=a

(2 to 1) MUX a

1 0

(ii) AND gate: Y=ab

(2 to 1) MUX a

0 b

(iii) OR gate: Y=ab+b=a+b

(2 to 1) MUX b

a 1

Figure 38: (2 to 1) MUX as universal circuit.

6.8 Demultiplexer (DEMUX)

It does inverse operation of a multiplexer.
Example: (1 to 4) DEMUX.
E

D0 D 0 = S 1 S0 E

S0 D1 D 1 = S 1 S0 E

D2 D 2 = S 1 S0 E
S1

D3 D 3 = S 1 S0 E

Figure 39: Diagram of (1 to 4) DEMUX.

C. N. Zhang, CS400 26
6.9 Read Only Memory (ROM)
It is essentially a memory device where permanent binary information is stored.
 ROM can be built by a decoder and a set of OR gates.
Example: Construct a ROM which is a 16-word memory from address 0 to 15. Each
word has 4 bits as shown in Table 9. The table can be viewed as the truth table for four
functions which have the same input variables (X1; X2; X3; X4).
Table 9: Truth table for the ROM.
Address Z1 Z2 Z3 Z4
0000 0 0 0 0
0001 0 0 0 1
0010 0 0 1 1
0011 0 0 1 0
0100 0 1 1 0
0101 0 1 1 1
0110 0 1 0 1
0111 0 1 0 0
1000 1 1 0 0
1001 1 1 0 1
1010 1 1 1 1
1011 1 1 1 0
1100 1 0 1 0
1101 1 0 1 1
1110 1 0 0 1
1111 1 0 0 0
0
1
2
3
4
(4x16) Decoder

X1 5
6
X2 7
8
X3
9
10
X4
11
12
13
14
15
Z1 Z2 Z3 Z4
Figure 40: Logic diagram of a ROM.
C. N. Zhang, CS400 27

The four functions can be represented by:

Z1 = (8; 9; 10; 11; 12; 13; 14; 15)
Z2 = (4; 5; 6; 7; 8; 9; 10; 11)
Z3 = (2; 3; 4; 5; 10; 11; 12; 13)
Z4 = (1; 2; 5; 6; 7; 9; 10; 13; 14)
 Types of ROMs:
1. Mask Programming: is is done by semiconductor company (xed).
2. Programmable ROM (PROM): it allows users to program the PROM in their
own labs.
3. Erasable PROM (EPROM): it can be reprogrammed to a new ROM by user.

6.10 Programmable Logic Array (PLA)

It is similar to ROM in concept, except that the PLA does not provide all minterms (full de-
coder). The decoder is replaced by an array of AND gates.
Example:
F1 = X1X2 + X1X 3 + X 1X 2X3
F2 = X1X2 + X1X3 + X 1X 2X3
X1 I1
I2
X2 I3
I4
X3 I5
I6

P1 P2 P3 P4
F1

F2

Figure 41: Logic diagram of a PLA.

C. N. Zhang, CS400 28

7 Sequential Circuits
 A sequential circuit consists of a combinational circuit and storage elements ( ip- ops)
that together form a feedback system.
Inputs Combinational Outputs
circuit Next state Storage
Present
elements
state

Figure 42: Block diagram of a sequential circuit.

 The values of the outputs are determined by the inputs as well as the present states of
the stotage elements.

7.1 Flip-Flop (Storage Element)

 SR ip- op:
(Reset) R S R Q Q
Q
1 0 1 0
Set state
0 0 1 0
0 1 0 1
Reset state
0 0 0 1
(Set) S Q 1 1 0 0 Undefined

Figure 43: Logic diagram and truth table of a SR ip- op.

 Clocked SR ip- op: Characteristic equation: Q(t + 1) = S + RQ and SR = 0

S
Q S R Q(t+1) Operation Q(t) Q(t+1) S R
0 0 Q(t) No change S Q 0 0 0 x
0 1 0 Reset C 0 1 1 0
1 0 1 Set R Q 1 0 0 1
Q 1 1 ? Indeterminate 1 1 x 0
R
(a) Logic diagram (b) Characteristic table (c) Symbol (d) Excitation table

Figure 44: Clocked SR ip- op.

C. N. Zhang, CS400 29

 JK ip- op: Characteristic equation: Q(t + 1) = JQ + KQ

S R Q(t+1) Operation Q(t) Q(t+1) J K
0 0 Q(t) No change J Q 0 0 0 x
0 1 0 Reset C 0 1 1 x
1 0 1 Set K Q 1 0 x 1
1 1 Q(t) Complement 1 1 x 0
(a) Characteristic table (b) Symbol (c) Excitation table

Figure 45: JK ip- op.

 D ip- op: Characteristic equation: Q(t + 1) = D
Q(t) Q(t+1) D
D Q 0 0 0
D Q(t+1) Operation
0 0 Reset C 0 1 1
1 1 Set Q 1 0 0
1 1 1
(a) Characteristic table (b) Symbol (c) Excitation table

Figure 46: D ip- op.

7.2 Sequential Circuit Design using Flip-Flops

 State: A state of sequential circuits is a possible combination values of ip- ops (a
string of 0 and 1) which can be represented by a binary value or a label.
 State Diagram: A state diagram is a directed graph to represent a sequential cir-
cuit. Each node in the graph represents a state and each directed edge denotes a state
transformation.
For example, A X=Y
! B represents the transformation from state A to state B , the input
X , and the current output value Y . In general, the state diagram of a sequential circuit
with m ip- ops and n inputs has 2m nodes (states), each of which has 2n outgoing edges.
The following example illustrates how to obtain the state diagram of a sequential circuit.
Example: Draw the state diagram of the following circuit.
1. There are up to four states (nodes): 00, 01, 11, and 10. Each node has two outgoing
edges. Each edge has one input X and one output Y .
2. According to the circuit, write down the input equations for all inputs of the ip- op
A and B.
DA = AX + BX
DB = AX
C. N. Zhang, CS400 30

X
DA A
C A

DB B
C B

Clock
Y

Figure 47: Logic diagram for design example.

3. Write down characteristic equation for each ip- op and substitute all inputs by the
input functions obtained in step 2.
A(t + 1) = DA
= A(t)X + B (t)X
B (t + 1) = DB
= A(t)X
4. Write down output equation.
Y = (A + B )X
5. Draw state diagram starting from state 00 by trying all possible input value X
and determining which state is the next state for this input value according to the
equations obtained in step 3, and determine the output value.
0/0 1/0

00 01
0/1

0/1 0/1 1/0

1/0 10 11
1/0

Figure 48: State diagram for design example.

C. N. Zhang, CS400 31

 State table: is a table representing a sequential circuit. It includes columns of present

state, input(s), next state, and output(s). For example, state table for the above circuit
is as follows:
Present state Input Next state Output
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

Figure 49: State table for design example.

Note: Any state diagram can be converted into a state table and vice versa.
 Design Procedure:
1. Obtain state table from state diagram or from design requirements of the circuit.
2. Derive circuit excitation table and output function(s) from state table.
3. Use map to simplify the output functions and ip- op input functions
4. Draw the circuit.
Example-A: Design a sequential circuit whose state diagram is shown below.
0/0

00
1/1 1/0

1/0 01 11 0/0

0/0 1/1
10

0/0

Figure 50: State diagram.

C. N. Zhang, CS400 32

1. Obtain state table from state diagram.

Present state Input Next state Output
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 1
1 1 0 1 1 0
1 1 1 0 0 0

Figure 51: State table for design example-A.

2. Draw excitation table using JK ip- op.

Present state Input Next state Flip-flop Inputs
A B X A B JA K A JB K B
0 0 0 0 0 0 x 0 x
0 0 1 0 1 0 x 1 x
0 1 0 1 0 1 x x 1
0 1 1 0 1 0 x x 0
1 0 0 1 0 x 0 0 x
1 0 1 1 1 x 0 1 x
1 1 0 1 1 x 0 x 0
1 1 1 0 0 x 1 x 1

Figure 52: Excitation table for design example-A.

3. Simplify all functions using map.

BX B BX B
A 00 01 11 10 A 00 01 11 10

0 1 0 x x x x

1 x x x x A 1 1 A B
BX
A 00 01 11 10
X X
JA = B X KA = B X 0 1

BX B BX B 1 A
1
A 00 01 11 10 A 00 01 11 10

x x 1 X
0 1 x x 0
Y =BX
1 1 x x A 1 x x 1 A

X X
JB = X KB = A X + A X
=A X

Figure 53: Map for design example-A.

C. N. Zhang, CS400 33

4. Draw circuit.
X J
A
C
A
K

J
B
C
B
K
Y
X

Clock

Figure 54: Logic diagram for design example-A.

Example-B: Find the state diagram for the following sequential circuit. The circuit has one
input and one output. The output will be in logic '1' if and only if a pattern '101' occurs in
the input sequence, e.g.
if input(X): '001010100101', then output(Y): '000010100001'
Since the pattern has three bits, let (00, 01, 10, 11) be the four states, where each of which
represents the rst two bits of any input received.
Start from one state (node), the next two states and the value of the outputs are determined
by checking the value of the next inputs, i.e. for both X = 0 and X = 1. Repeat this step until
all states have been examined.
0/0

00
0/0
1/0

0/0
10 11 1/0

1/1
0/0 1/0
01

Figure 55: State diagram for example-B.

C. N. Zhang, CS400 34

7.3 Register
It consists of a set of D ip- ops and MUXs.
 The number of D ip- ops = the number of bits of the register.
 The size of the MUX is determined by the functions performed by the register.
Example: Design a 4-bit register which can perform the following functions under the two
control signals S0 and S1.
Mode Control
S1 S0 Register Operation
0 0 No change
0 1 Shift right (down)
1 0 Shift left (up)
1 1 Parallel load

Figure 56: Function table for the 4-bit register.

 The number of D ip- ops = 4 (4-bit)
 The size of MUX is (4 to 1) (4 functions)
 Di = S 1S 0Ai + S 1S0Ai;1 + S1S 0Ai+1 + S1S0Ii
S0 S0
S1 S 1 (4x1) D Q A0

Serial input
0
1
MUX C
2
I0 3

S0
S 1 (4x1) D Q A1
0
1
MUX C
2
I1 3

S0
S 1 (4x1) D Q A2
0
1
MUX C
2
I2 3

S0
S 1 (4x1) D Q A3
0
1
MUX C
Serial input 2
I3 3
Clock

Figure 57: Logic diagram of the 4-bit register.

C. N. Zhang, CS400 35

7.4 Synchronous Binary Counter

Design procedure is the same as with any other synchronous sequential circuit.
Example: Design a 4-bit binary up counter using JK ip- ops.
1. State diagram.
0000 0001 1111

Figure 58: State diagram for binary up counter.

Note: it can be viewed as the state diagram of a sequential circuit without input and
output.
2. Excitation table.
Present state Next state Flip-flop Inputs
A3 A2 A1 A0 A3 A2 A1 A0 J A3 K A3 J A2 K A2 J A1 K A1 J A0 K A0
0 0 0 0 0 0 0 1 0 x 0 x 0 x 1 x
0 0 0 1 0 0 1 0 0 x 0 x 1 x x 1
0 0 1 0 0 0 1 1 0 x 0 x x 0 1 x
0 0 1 1 0 1 0 0 0 x 1 x x 1 x 1
0 1 0 0 0 1 0 1 0 x x 0 0 x 1 x
0 1 0 1 0 1 1 0 0 x x 0 1 x x 1
0 1 1 0 0 1 1 1 0 x x 0 x 0 1 x
0 1 1 1 1 0 0 0 1 x x 1 x 1 x 1
1 0 0 0 1 0 0 1 x 0 0 x 0 x 1 x
1 0 0 1 1 0 1 0 x 0 0 x 1 x x 1
1 0 1 0 1 0 1 1 x 0 0 x x 0 1 x
1 0 1 1 1 1 0 0 x 0 1 x x 1 x 1
1 1 0 0 1 1 0 1 x 0 x 0 0 x 1 x
1 1 0 1 1 1 1 0 x 0 x 0 1 x x 1
1 1 1 0 1 1 1 1 x 0 x 0 x 0 1 x
1 1 1 1 0 0 0 0 x 1 x 1 x 1 x 1

Figure 59: Excitation table for binary up counter.

3. Map simplication.

JA0 = KA0 = 1
JA1 = KA1 = A0
JA2 = KA2 = A0A1
JA3 = KA3 = A0A1A2
C. N. Zhang, CS400 36

A1 A0
A1 A0
A 3A 2 00 01 11 10
00 1 1 x x
01 x x x x 1 x x 1
A2
11 x x x x 1 x x x x x x
A3
10 1 1 x x x x x x

J A2 = A 0 A 1 J A1 = A 0 J A3 = A 0 A 1 A 2

x x x x x x 1 x x x x
1 x x 1 x x x x
1 x x 1 1
x x x x x x 1

K A2 = A 0 A 1 K A1 = A 0 K A3 = A 0 A 1 A 2

Figure 60: Map for binary up counter.

4. The circuit.
J
A0
C
Count Enable E K

J
A1
C
K

J
A2
C
K

J
A3
C
K
Output
Carry
Clock

Figure 61: Circuit of binary up counter.

C. N. Zhang, CS400 37

7.5 Other Synchronous Counters

Example: Design a counter using JK ip- ops which repeats the sequence of six states as
shown below:
000 001 010 100 101 110

Figure 62: Sequence of six states for synchronous counter.

1. State diagram.
000 111

001 110

010 101

100 011

Figure 63: State diagram for synchronous counter.

2. Excitation table.
Present state Next state Flip-flop Inputs
A B C A B C JA K A JB K B JC K C
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 0 0 x 1 x x 1
0 1 0 1 0 0 1 x x 1 0 x
0 1 1 1 0 0 1 x x 1 x 1
1 0 0 1 0 1 x 0 0 x 1 x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 0 0 0 x 1 x 1 0 1
1 1 1 0 0 0 x 1 x 1 x 1

Figure 64: Excitation table for synchronous counter.

C. N. Zhang, CS400 38

3. Map simplication.

BC B BC B BC B
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10

0 1 1 0 1 x x 0 1 x x

1 x x x x A 1 1 x x A 1 1 x x A

C C C
JA = B JB = C JC = B

BC B BC B BC B
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10

0 x x x x 0 x x 1 1 0 x 1 1 x

1 1 1 A 1 x x 1 1 A 1 x 1 1 x A

C C C
KA = B KB = 1 KC = 1

Figure 65: Map for binary up counter.

4. The circuit.
A B C

J C K J C K J C K

Clock

Logic-1

Figure 66: Synchronous counter circuit.