IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO.

6, JUNE 2014 1929

Integration of a Piezoelectric Layer on Si FinFETs

for Tunable Strained Device Applications
Buket Kaleli, Raymond J. E. Hueting, Senior Member, IEEE, Minh D. Nguyen, and Rob A. M. Wolters

Abstract— Earlier theoretical reports predicted that the usage

of a piezoelectric stressor layer around the FinFET, i.e., the
PiezoFET, offers a great potential for steep subthreshold slope
devices. For the first time, we analyzed the practical realization
of such PiezoFETs comprising a piezoelectric stressor layer, lead–
zirconate–titanate (PZT), and aluminum–nitride (AlN) deposited
on n-type silicon FinFETs. A high-piezoelectric response in the
range of 100 pm/V has been obtained for the PZT PiezoFET
evidencing the converse piezoelectric effect in the device. The
piezoelectric response for the AlN device was much less (13 pm/V)
as expected. Underlying device properties, such as subthreshold
swing (SS) and low-field electron mobility have been significantly
affected by the presence of the PZT stressor. A 20%–50% change
in the mobility and a change in the SS (about 5 mV/decade) have
been observed. The change can be attributed to the strain induced
reduction of the interface trap density at the Si/SiO2 interface.
This strain is partly formed by the bias over the piezoelectric
layer, which indicates the converse piezoelectric effect related
tunable strain in both the silicon channel and gate oxide.
Index Terms— Aluminum–nitride (AlN), FinFET, lead–
zirconate–titanate (PZT), piezoelectric effect, strain, stress.
I. I NTRODUCTION
F ERROELECTRIC and piezoelectric materials find appli-
cation in high-density capacitors [1], sensors, microme-
chanical systems [2], [3], and nonvolatile memories [4], [5].
Recently, there has been a growing number of reports on
novel steep-subthreshold devices where ferroelectric and/or
piezoelectric thin films are employed. For instance, Salahuddin
and Datta [6] proposed to use ferroelectrics as a gate dielectric
to obtain a negative capacitance for improvement of the
device properties. Later on, Rusu et al. [7] demonstrated this
concept experimentally on p-MOSFET devices. They show
Manuscript received November 2, 2013; revised January 30, 2014; accepted
March 31, 2014. Date of publication May 1, 2014; date of current version
May 16, 2014. This work was supported in part by the Dutch Technology
Foundation STW, in part by an Applied Science Division, NWO, and in part
by the Technology Program, Ministry of Economic Affairs. The review of
this paper was arranged by Editor J. C. S. Woo.
B. Kaleli and R. J. E. Hueting are with the MESA+ Institute for
Nanotechnology, University of Twente, Enschede 7522, The Netherlands
(e-mail: b.kaleli@utwente.nl; r.j.e.hueting@utwente.nl).
M. D. Nguyen is with the MESA+ Institute for Nanotechnology, University
of Twente, Enschede 7522, The Netherlands, Solmates B.V., Enschede 7522
NB, The Netherlands, and also with the International Training Institute for
Materials Science, Hanoi University of Science and Technology, Hanoi 10000,
Vietnam (e-mail: d.m.nguyen@utwente.nl).
R. A. M. Wolters is with the MESA+ Institute for Nanotechnology,
University of Twente, Enschede 7522, The Netherlands, and also with
NXP Semiconductors, Eindhoven 5656 AE, The Netherlands (e-mail:
r.a.m.wolters@utwente.nl).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2316164
0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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Fig. 1. PiezoFET schematic cross section with narrow fins illustrating the
formed strain condition corresponding to an upward piezoelectric response.
The white arrows show the PZT deformation, while the black arrows show
the corresponding formed stress in the silicon fins. A schematic view of the
layer stack along a vertical line through an Si fin is shown on the left. The
figure is not to scale.
that, it is possible to obtain a device with a subthreshold
swing (SS) below the fundamental limit of 60 mV/decade
at room temperature [8]. Newns et al. [9] proposed the
piezoelectric transistor (PET) based on the piezoresistance
effect on special channel materials manifesting a pressure-
induced metal–insulator transition. Their calculations show
that the PETs performance outpaces the conventional FETs
with respect to the lower supply voltage and higher switching
speed. In [10] and [11], it has been theoretically predicted
that the piezoelectric materials can be utilized in standard
semiconductor materials, such as silicon (Si) or germanium,
for obtaining steep-subthreshold slope switches.
In this paper, the (converse) piezoelectric effect of a ferro-
electric lead–zirconate–titanate (Pb[Zrx Ti1−x ]O3 or PZT) thin
film is experimentally studied as a channel stressor in the Si
FinFET. We call this novel device structure the PiezoFET.
The motivation of using a piezoelectric material as a stressor
for FinFETs is to increase the mobility and to reduce the
SS caused by band-offset modification [10], [11].
The PiezoFET is basically a four terminal device consisting
of two separate gates (Fig. 1): 1) the conventional gate that
electrostatically controls the channel, which we call the bottom
gate (BG) and 2) a top gate (TG or pigate) to control the
channel strain. The PZT material was chosen as a stressor
because of its higher piezoelectric response among the other
piezoelectric materials [3]. In addition, we have investigated
the effect of aluminum–nitride (AlN) film for comparison.
This paper is outlined as follows. In Section II, we describe
the device fabrication followed by the piezoelectric response
in Section III. In Section IV, we report on the electrical
characterization and the analysis of the device properties.
Finally, conclusions are drawn in Section V.
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Fig. 2. Optical micrograph of a typical 5-fin PiezoFET. The bottom gate,
top gate, drain, and source are indicated by BG, TG, D, and S, respectively.
Fig. 3. HR-TEM images of a magnified image of one fin of a PiezoFET
with (a) 100 nm and (b) 20-nm-wide fin and 10-nm LNO + 100-nm PZT
layer stack.
II. D EVICE FABRICATION
Devices were fabricated on a (001)-oriented undoped
silicon-on-insulator (SOI) wafer with a buried-oxide (BOX)
layer of 1-μm thickness. The 1.5-μm-thick Si device layer was
thinned down to 150 nm by thermal oxidation. The (110)/[110]
oriented Si fins with different fin widths (WFIN = 15–1000 nm)
were patterned with e-beam lithography. After dry etching
of the Si fins, a 11-nm-thick gate oxide layer was thermally
grown. A 6-nm-thick TiN and 12-nm-thick α-Si deposition
was done in our in-house built cluster tool using atomic-layer
deposition (ALD) and chemical vapor deposition techniques,
respectively [12]. Following the BG stack patterning, As+ ion
implantation (1015-cm−2 dose, 50 keV), and a rapid thermal
annealing (900 °C, 30 s) were performed. Afterwards, a stack
containing a PZT film and an LaNiO3 (LNO) buffer layer was
deposited using a SolMateS large area pulsed-laser deposition
(PLD) system at 650 °C. PiezoFETs containing sputtered AlN
were also processed. Patterning of the piezoelectric layers was
performed by wet etching. Finally, the Pt/Ti TG and contact
pads were defined by a lift off process. The PiezoFET is shown
in the optical micrograph in Fig. 2. There is a 2 μm overlap
between the TG and the piezoelectric layer.
Fig. 3(a) and (b) shows TEM pictures of a 100- and
20-nm-wide fin PiezoFET with a 10-nm-thick LNO and
100-nm-thick PZT layer. The TG is not visible in the figures
due to the sample preparation (i.e., Pt protective layer). In these
images, good step coverage of the TiN as well as poly-Si is
recognized, whereas the step coverage of the LNO/PZT stack
is poor. The PZT layer thickness decreases to 20–50 nm, while
the LNO layer thickness decreases to 2–5 nm at the sidewalls.
Although the step coverage is poor, electrical measurements
show that there is no direct electrical short circuit between the
TiN BG and the Ti/Pt TG in the structures, as will be discussed
in Section IV.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
III. P IEZOELECTRIC R ESPONSE
Fig. 1 shows a schematic cross section of the fabricated
PiezoFET presenting two Si fins under applied bias across a
homogenously deposited PZT (or AlN) layer. The displace-
ments are indicated here when the PZT is elongated in the
direction of the electric field between BG and TG. The white
arrows indicate the piezoelectric displacement in the PZT
layer, while the black arrows indicate the corresponding strain
formed inside the Si fins. This happens for a negative bias over
the PZT layer (Vπ = VTG − VBG < 0 V). In this case, the
stress formed in the Si fin can be described as follows: 1) due
to the PZT layer at the fin sidewall region, the Si fin is under
biaxial tensile stress along x (fin width) and z (fin height), and
under uniaxial compressive stress along y (channel length);
2) due to the PZT layer on top of the fin, biaxial compressive
stress along x and y (channel length) is formed; and 3) due to
the layer on the BOX region, tensile stress in Si along x and
compressive stress along y is formed.
The overall strain effect depends on the fin width and aspect
ratio. For narrow fins condition 1) dominates, whereas for
wider structures condition 2) is more important. In practice,
condition 3) would not be important for narrow fins, as is
explained in Section IV. It should be noted that for each fin
width, the net stress depends on the amount of the individual
stress components. Fig. 1 is shown for a narrow fin structure
where the PZT on the BOX layer (and at the fin sidewalls)
determines the net component. For downward deflection [at
positive bias over the PZT layer (Vπ = VTG − VBG > 0 V)],
all the stress components change direction. Note that in this
discussion, a possible stress relieving effect of the intermediate
layers was not considered.
A laser Doppler vibrometer (LDV) measurement was per-
formed to characterize the piezoelectric response of the
PZT layer on our FinFET devices. A sinusoidal ac-voltage
of 1 V and at 8-kHz frequency was applied here to a
100-nm-thick PZT layer. The response under these measure-
ment conditions is shown in Fig. 4(a) and (b) for FinFETs
with 30- and 1000-nm fin width, respectively. It is clear that
the vertical displacement is enhanced on top of the fins and
there is a converse piezoelectric effect. The displacement is
also high outside the fin area, under the TG. Fig. 4(c) and (d)
shows the line scan of the displacement across the dotted
lines in Fig. 4(a) and (b). A piezoelectric coefficient of about
d33 , f = 100–110 pm/V on the fin area and about d33, f =
80–90 pm/V outside the fin area above the top contact has
been determined. As will be discussed in Section IV, the
actual voltage drop over the PZT layer is less than the applied
voltage. The values are doubled when the applied nominal
voltage was increased to 2 V. This is an indication that these
values are real displacements.
The enhancement of displacement on the channel region
could be due to the path length difference of the laser beam
between the top and the outer side of the fin area. The
path is shorter (by a fin height amount ≈150 nm) for the
beam deflected from the top. Furthermore, there is a 10%
difference in the maximum displacement between the wide
fin and narrow fin device. The maximum displacement is
enhanced on wide fins possibly due to their relatively wide
KALELI et al.: INTEGRATION OF A PIEZOELECTRIC LAYER ON Si FinFETs
Fig. 4. 2-D upward response scans of a 5-fin PiezoFET with a (a) 30 nm and
(b) 1000-nm fin width and L pigate = 10 μm and L gate = 30 μm. Nominally,
a sinusoidal ac voltage of 1 V and at 8-kHz frequency was used. The graphs
in (c) and (d) are the line scan profiles of the displacement across the dotted
line in (a) and (b), respectively. The channel response is indicated in between
two vertical dotted lines. A stack of 10-nm LNO + 100-nm PZT thin films
was used in this structure.
Fig. 5. Id –Vgs device characteristics of a 5-fin FinFET before and after PZT
deposition with L pigate = 10 μm, L gate = 30 μm, and WFIN = 100 nm at
Vds = 1 V and room temperature.
fin top surface, which is in the order of beam spot size that
helps to obtain more signal from the fin top surface.
The same LDV measurements were performed on
PiezoFETs containing 180-nm-thick AlN layers (not shown)
yielding a piezoelectric coefficient of around 13 pm/V. This
lower value is expected due to material properties. However,
it is higher than the piezoelectric coefficient of bulk AlN. This
is attributed to the mentioned reasons before.
IV. E LECTRICAL C HARACTERIZATION AND A NALYSIS
Fig. 5 shows the Id − Vgs device characteristics of the same
100-nm-wide fin device before and after the 100-nm-thick PZT
deposition. A negative shift of threshold voltage (Vth ) is
observed after PZT deposition. This shift is observed in all
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Fig. 6. Id –Vgs device characteristics of the PiezoFETs for different Vπ with
(a) WFIN = 30 nm and (b) WFIN = 1000 nm.
devices. Deposition and processing of the LNO/PZT layers
show no electrical and physical degradation of the Si body.
The XPS analysis on our planar devices also did not indicate
any diffusion of atoms between the different material layers.
The observed shift in the I –V curve could be due to stress in
the Si FinFET after the PLD process. It has been reported that
due to the difference in coefficient of thermal expansion (CTE)
of the Si and PZT a thermal stress can be developed in the PZT
film [13]. Since Si has a CTE of 2.6 × 10−6 K−1 [14] and
PZT has a CTE of 6.0 × 10−6 K−1 [15], additional thermal
biaxial in-plane tensile stress is formed in the PZT film during
cooling down process from deposition temperature (650 °C)
to room temperature. This will result in biaxial compressive
stress in the Si fin. Thermal expansion related stress profiles
and analysis have been reported previously [16] and [17].
However, the shift cannot be explained with the strain effect
in the Si alone since the observed shift of around 0.15 V
is relatively large. We will elaborate on this further in this
section.
In our analysis for each measured I –V curve, the PZT layer
was biased at a fixed voltage between TG and BG (VBG = Vg )
to observe the converse piezoelectric effect on the operation
of the device. Fig. 6 shows the Id –Vgs curves of PiezoFETs
with a 30- and 1000-nm fin width.
A threshold shift depending on Vπ as well as higher
off current (Ioff ) is observed. Furthermore, unlike reported
for FerroFETs [7], no hysteresis behavior in our PiezoFETs
is observed. Generally, ferroelectric materials show hystere-
sis due to the polarization effect [18]. However, the rela-
tively high leakage current interferes with the polarization
switching in our devices, which results in a nonhysteretic
behavior. When carefully observing Fig. 6, it appears that
there is an exponential dependency of Vth on Vπ , reaching
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Fig. 7. (a) J –Vπ characteristics of the PZT capacitor on a planar sur-
face and on 5-fin 30, 100, and 1000-nm FinFET with L TG = 10 μm.
(b) Modified schematic equivalent circuit of the measurement setup utilized
for the PiezoFET I –V measurements. The piezoelectric layer is represented
by a leaky resonator with a capacitance Cpi .
+1.5 and −2 V under −3 and +3 V applied bias over the
PZT layer, respectively. The results also indicate that there is
an asymmetry regarding the polarity.
Related to this, the leakage current of the PZT of the
PiezoFET shows an exponential dependency with Vπ and an
almost symmetric behavior with the applied bias, see Fig. 7(a).
The 5-fin devices with 30-, 100-, and 1000-nm fin width
show a leakage current within the same range. The planar
capacitor, on the other hand, shows much less leakage. This
is an indication of excess leakage due to nonuniform step
coverage of the PZT layer (see Fig. 3). PiezoFETs with a 180-
nm-thick AlN layer show very similar characteristics with the
same amount of Vth for the 30-nm-wide devices. However,
for wide fins Vth is smaller due to a lower leakage current
(data is not shown here).
All the measurement data indicate a relation between Vth
and the leakage current formed possibly by a leaky piezo-
electric capacitor Cpi on top of the FET connected by the
BG resistance, as shown in a simple electrical dc equivalent
circuit diagram, see Fig. 7(b), where current distribution
effects are neglected. In the ideal case, there is no current
through Cpi and the surface potential in the Si fin equals Vgate .
However, when there is a (variable) resistor (Rpi ) parallel to
the piezoelectric capacitor, the surface potential in the Si fin
will be affected. The influence of Rpi on the surface potential
is determined by the ratio Rgate /Rpi ; the higher this ratio the
greater its influence. Our measurement data indicate that Rgate
is mainly determined by the 30 μm × 50 μm external gate
connection formed by the 6-nm-thick TiN layer, corresponding
to a value of 445 . For estimating Rpi , we need to determine
the leakage current through the PZT layer. For Vπ = 3 V, for
instance, a leakage current of 2.5 mA was measured yielding
Rpi = 755 . Using these calculated resistances, a ≈2/3· Vπ
voltage drop is estimated to be across the PZT layer whereas
the rest of the voltage drop is across the gate. The surface
potential changes by this amount and therefore a threshold
voltage shift occurs.
To analyze the (converse) piezoelectric effect, the SS-Vπ
graph is shown in Fig. 8. Despite the expected improved elec-
trostatic gate control in the narrow channel undoped FinFETs,
the SS is above 60 mV/decade for all devices. This can be
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
Fig. 8. SS-Vπ graph of 5-fin device with WFIN = 30, 100, and 1000 nm at
Vds = 1 V.
explained by charge trapping at the Si/SiO2 interface-induced
during the processing [19]. Further, the SS has reduced after
the PZT deposition for narrow fins. This could indicate that the
gate oxide (SiO2 ) layer has been stressed along its interface
with the Si body, which results in large structural deformation
and possibly even affecting the band alignment. The effect of
fixed strain on the trapping probability and band modulation
was reported previously [20], [21]. We report this on tunable
strain in our devices as well.
Since SiO2 is less stiff than Si, most of the strain will be
absorbed in the oxide and possibly at its interface. Earlier, it
was shown by finite element method (FEM) simulations that
higher strain values in the gate dielectric are present compared
with the Si body [22]. This can result in a reduced effective
interface trapping of charge carriers, hence a lower SS. A part
of the threshold voltage shift could also be explained by this
phenomenon.
Up to 4 mV/decade improvement (decrease) in the SS is
observed after the PZT deposition on narrow fin devices. For
the 1000-nm-wide fin device, however, it increases. Decreasing
the SS for narrow fins indicates a reduction of the interface
trap density. Conversely, for wide fins the SS increases and this
indicates an increase in the interface trap density. Change in
the density of states depending on the fin width is possibly due
to different crystal orientation of the fin at the sidewall and the
surface. In addition, we expect a different stress configuration
for wide and narrow fins due to the dominance of the surface
for wide fins and the sidewalls for narrow fins. This would
have a different effect on the band alignment as well.
Furthermore, the SS is modified (up to 6 mV/decade) by
biasing the PZT layer up to 3 V. This improvement is due
to the converse piezoelectric effect. For devices with 30- and
100-nm fin width, the SS is decreased with an applied PZT
bias (Fig. 8). Note that short channel effects become dominant
for a 1000-nm-wide fin device and the conclusions drawn from
device characteristics will not be accurate.
The effective electron mobility of the PiezoFET has been
calculated by compensating for the Vth . Fig. 9(a)–(c) shows
the effective electron mobility as a function of the electric
field (μeff − E) for our 5-fin (110)/[110] PiezoFETs with
WFIN = 30, 100, and 1000 nm under different bias over the
PZT layer. For comparison, the μeff − E curve of the (100)
KALELI et al.: INTEGRATION OF A PIEZOELECTRIC LAYER ON Si FinFETs
Fig. 9. Effective electron mobility–electric field curves of PiezoFETs for
different biasing over the PZT layer with (a) 5-fins of WFIN = 1000 nm
and (100) MOSFET obtained from Takagi et al. [24], (b) 5-fins of WFIN =
100 nm, and (c) 5-fins of WFIN = 30 nm and (110) FinFET with WFIN =
25 nm obtained from Rudenko et al. [23] and (110) MOSFET obtained from
Takagi et al. [24].
MOSFET and (110) FinFET, (110) MOSFET are shown in
Fig. 9(a) and (c), respectively [23], [24]. Compared with the
mobility values given in [23], the low-field mobility is higher
whereas the high-field mobility is lower in our devices. The
higher mobility at lower fields is an indication of less effective
Coulomb scattering, most probably because of a higher fin and
the use of SiO2 as a gate dielectric in our case. Rudenko et al.
[23] used a high-κ material, in which dipoles that are close to
the channel could increase the Coulomb scattering. However,
the lower mobility at higher fields is an indication of more
surface imperfections in our devices.
Up to ≈20% increase in the mobility was observed for the
WFIN = 1000-nm device after PZT deposition. The effect on
WFIN = 100- and 30-nm devices at low fields is stronger;
yielding up to ≈50% increase in mobility. No significant
change is observed at high fields.
To show the trend in the mobility more clearly, the mobility-
Vπ curve has been plotted when biased at moderate inversion
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Fig. 10. Effective electron mobility-Vπ curves of devices (a) at a
5 × 104 V/cm field for 30- and 100-nm-wide fin devices and at a
1 × 105 V/cm field for a 1000-nm-wide fin device and (b) at a 2 × 105 V/cm
field for 30- and 100-nm-wide fin devices and at a 4 × 105 V/cm field for a
1000-nm-wide fin device.
[Fig. 10(a)] and at strong inversion [Fig. 10(b)]. For the 30-
and 100-nm-wide fin devices, the applied fields are at E = 5 ×
104 and 2 × 105 V/cm for moderate and strong inversion,
respectively. Due to the fact that the WFIN = 1000-nm
device acts as a partially depleted SOI device, a higher
electric field is needed to obtain strong inversion. Therefore,
for a 1000-nm-wide device, the effective mobility-Vπ curve
is plotted at a higher field of 1 × 105 and 4 × 105 V/cm for
moderate and strong inversion, respectively.
At low fields, the mobility of the 30- and 100-nm-wide
devices shows an increasing trend under positive applied bias
and a decreasing trend under negative applied bias. At high
fields, the mobility decreases again under negative applied
bias. But no trend is observed for a positive applied bias. The
next step is to discuss the possible reasons for the observed
mobility behavior.
A. After Deposition of (Before Biasing) the PZT Layer
As shown in Fig. 10, the mobility has increased for 1000-
and 100-nm-wide fin devices after the LNO/PZT deposition for
Vπ = 0 V. Devices show higher mobility values at lower fields
in Fig. 10(a) (in the moderate inversion regime when Coulomb
or ion scattering is important) after the PZT deposition. The
trend is the same at high fields, except for the 30-nm-wide
device, which shows a decrease in mobility [Fig. 10(b)].
The difference in the effective mobility and the shift in
the threshold voltage in the I –V curves indicate that strain is
formed after deposition of the LNO/PZT stack. Furthermore,
as mentioned earlier, oxide deformation after PZT deposition
possibly changes the interface trap density. At low-fields
Coulomb scattering is important and that is affected by the
traps. Fig. 9 shows that the most significant mobility change
occurs at low fields. Since both the mobility and SS are
affected by the PZT deposition, this strongly indicates that
charge trapping is the root cause for the increase in the
low-field mobility [25].
At high fields, on the other hand, surface roughness scat-
tering is important, which could also be affected by strain.
As mentioned earlier, we expect a biaxial tensile stress in
the PZT due to difference in CTE when no external bias
is applied. The step coverage of the PZT is not as ideal as
shown in Fig. 2. Therefore, we expect that the stress profile
is not determined by the PZT layer on the BOX layer, but
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more by the PZT layer located at the fin sidewall. Hence, for
narrow fins (WFIN << HFIN ), a strain gradient parallel to the
surface of the (110) fin sidewall is important. In this case,
for narrow fins, biaxial compressive stress along the fin height
and channel length direction is formed. This results in uniaxial
tensile stress along the fin width direction and consequently
increases the high-field electron mobility [26].
For narrow fins under both tensile and compressive stress
along the fin height direction, the conduction band valleys
move down in energy, though the latter would give a larger
impact both in the band offset and increased mobility [26].
This will result in a negative threshold voltage shift after
deposition [10], [11]. This could cause a relatively small part
of the Vth observed in Fig. 5. Compressive stress along the
fin height direction moves the 2 (“light”) electron valleys
down in energy. The conductivity effective mass of electrons
reduces, thereby increasing the electron mobility. Since we
expect compressive stress along the channel length, this stress
configuration is present for narrow fins in our devices (for
WFIN = 30 and 100 nm). We can observe it in Fig. 10(a) and
(b), except for 30-nm-wide device at high field.
For wide fins (WFIN  HFIN ) on the other hand, the
sidewalls can be neglected compared with the top surface
of the fin. Therefore, wide fins (WFIN = 1000 nm) are
expected to behave like a planar (001) surface [as in a (001)
bulk MOSFET]. Since the Si substrate is much thicker than
the Si fin height, the intermediate layers and the PZT layer,
the in-plane biaxial tensile stress formed in the PZT layer
will be transferred to the underlying layers down to the Si
substrate [17]. Hence, biaxial tensile stress along the fin width
and channel length direction is formed. This configuration
would result in uniaxial compressive stress along the fin height
direction and causes the 2 (“light”) electron valleys to move
down in energy. The conductivity effective mass of electrons
decreases and thereby electron mobility increases. This can be
observed in Fig. 10(a) and (b) for WFIN = 1000 nm.
In summary, before any Vπ biasing, the low-field mobility
(moderate inversion) increases possibly by the oxide defor-
mation that reduces the effective interface traps at the Si/SiO2
interface. On the other hand, the CTE difference formed strain
in Si influences the high-field mobility (strong inversion). For
wide fins, the high-field mobility increases due to biaxial ten-
sile stress along the fin width and channel length direction in
the (001) surface. For narrow fins, the mobility also increases
due to biaxial compressive stress along the fin height and
channel length direction along the (110) surface of the fin
sidewall.
B. Biasing the PZT Layer: Tunable Strain
A varying bias from −3 to 3 V has been applied over the
PZT layer and the mobility has been calculated. According to
Fig. 1, we expect an upward deflection under negative whereas
downward deflection under a positive applied field [27].
Therefore, for a negative field, we expect the narrow Si fin
to be more compressively stressed along the channel length
direction and tensile stressed along the fin height direction
and the mobility decreases. On the other hand, for a positive
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
field, more tensile stress is formed along the channel length
direction and compressive stress in fin height direction and the
mobility increases [26]. The situation is different for a wide
fin. Biaxial tensile stress at the (001) surface is formed under
positive applied field and this tends to increase the electron
mobility [28]. On the other hand, a negative bias will yield
almost no change in the mobility.
1) At Low Field: Fig. 10(a) shows an increasing trend of
the effective mobility of up to 20% at a positive bias for
30- and 100-nm-wide fins. The trend is the opposite at a
negative applied bias. For the 1000-nm-wide device, however,
there is almost no change.
2) At High Field: In Fig. 10(b), a smaller decrease in
effective mobility at a negative bias is observed. However, for
a positive bias, it is almost constant in contrast to Fig. 10(a).
Therefore, the trend in mobility under applied biases for
30- and 100-nm-wide devices can be mainly explained by
the data from literature. However, the effect of tunable strain
is found to be less significant than the strain formed by the
CTE difference.
The tunable strain in the channel can be improved in
different ways. Minimizing the interlayer thicknesses, such as
those of the TiN and the gate oxide, and replacing them with
more stiff materials can be an option. In addition, improving
the step coverage of the piezoelectric layer will prevent the
leakage and will enable straining the channel by the PZT on
the BOX layer. The PZT layer thickness should be reduced
as well, keeping the leakage current in mind. This will lower
the (CMOS compatible) supply voltage required for device
operation, which ultimately leads to a higher switching speed
(GHz range) [9], [11]. In this paper, we did not employ a
poling process. Poling would also greatly improve the ferro-
and piezoelectric properties of the PZT layer (see [29]) and
consequently the tunable strain.
V. C ONCLUSION
We have presented, for the first time, the device fabrication,
characterization, and analysis of a novel four terminal device
structure called the PiezoFET. A negative shift is observed in
the Id − Vgs curves after deposition of PZT and AlN films.
This effect could be related to strong gate oxide deformation
due to CTE difference formed strain. Further, the effect of the
piezoelectric layer on device properties of the transistors was
studied in terms of SS and mobility. It has been shown that
for moderate inversion (low field) both parameters are affected
by the CTE difference formed strain and the converse piezo-
electric effect. This can possibly be attributed by the oxide
deformation that reduces the interface traps at the Si/SiO2
interface. The high-field mobility is increased (up to ≈50%)
caused by the CTE difference formed strain, while a smaller
effect (≈5%) was observed by the converse piezoelectric effect
depending on the fin width. Our results have demonstrated the
feasibility and great potential of the PiezoFET concept.
ACKNOWLEDGMENT
The authors would like to thank A. A. I. Aarnink and
S. Smits for the guidance of the atomic-layer deposi-
KALELI et al.: INTEGRATION OF A PIEZOELECTRIC LAYER ON Si FinFETs 1935

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Research, Eindhoven, The Netherlands, since 1978.
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the MESA+ Institute for Nanotechnology and the
tures and limitations of its description in terms of top and sidewall
Chair of Semiconductor Components, University of
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