IV B.

Tech I-Sem, II Mid Examination, November - 2014 SET-1

(VLSI DESIGN)-ECE

Max. Marks: 10 M Time: 60 min Date:

Answer any TWO Questions 2x 5 Marks= 10 Marks

1. (a) Explain about Carry look ahead adder - (i) Carry Skip adder and (ii) Carry select adder.
    (b) Explain about 4X4 Barrel Shifter.

2. (a) Explain about DRAM cell with neat diagram.

    (b) Explain in detail SRAM cell or CAM cell.

3. (a) Explain about PLA, PAL and standard cell with example.
    (b) Enlist the differences between FPGA and CPLD.

4. (a) Explain about need for testing and discuss any two systems used for system  level testing.   
    (b) Discuss Stuck-at Faults.

IV B.Tech I-Sem, II Mid Examination, November - 2014 SET-2

(VLSI DESIGN)-ECE

Max. Marks: 10 M Time: 60 min Date:

Answer any TWO Questions 2x 5 Marks= 10 Marks

1. (a) Explain about Braun Multiplier or Wallace tree in brief

    (b) Explain about comparator with cmos implementation or counters with cmos implementation.

2. (a) Explain about NOR based ROM or NAND based ROM.

    (b) Explain in detail general memory architecture.

3. (a) Explain about Gate array based ASICs.

    (b Explain about CPLD architecture.

4. (a) Explain about need for testing and discuss about chip level testing.   
    (b) ) Explain about Built-In-Self-Test.