Embedded System

Avalon Switch Fabric

Concepts

A Field Programmable Gate Array (FPGA) is an integrated circuit
designed to be configured by the customer or designer after
manufacturing.

SOC (System on a Chip)

SOPC (System on a Programmable Chip)

SOPC Builder (System on a Programmable Chip Builder) is
software made by Altera that automates connecting soft-hardware
components to create a complete computer system that runs on any
of its various FPGA chips.

PSoC (Programmable System on Chip) is a family of integrated
circuits made by Cypress Semiconductor. These chips include a
CPU and mixed-signal arrays of configurable integrated analog and
digital peripherals.
NIOS II

Nios II is a 32-bit embedded-processor
architecture designed specifically for the
Altera family of FPGAs. Nios II incorporates
many enhancements over the original Nios
architecture, making it more suitable for a
wider range of embedded computing
applications, from DSP to system-control.
IP core

An IP (intellectual property) core is a block of logic
or data that is used in making a field programmable
gate array ( FPGA) or application-specific integrated
circuit ( ASIC ) for a product. As essential elements
of design reuse , IP cores are part of the growing
electronic design automation ( EDA) industry trend
towards repeated use of previously designed
components. Ideally, an IP core should be entirely
portable - that is, able to easily be inserted into any
vendor technology or design methodology.
IP core

IP cores fall into one of three categories: hard cores
, firm cores , or soft cores . Hard cores are physical
manifestations of the IP design. These are best for
plug-and-play applications, and are less portable
and flexible than the other two types of cores. Like
the hard cores, firm (sometimes called semi-hard )
cores also carry placement data but are configurable
to various applications. The most flexible of the
three, soft cores exist either as a netlist (a list of the
logic gate s and associated interconnections making
up an integrated circuit ) or hardware description
language ( HDL) code.
Logic Elements (LEs)

The main building block of the programmable
devices we use in the TM-2a is a Logic
Element (or LE). The only parts of the LE that
we use are the LUT, Cascade chain and
programmable register (or FF).
Note that it is not necessary to use all of
these elements. The FFs and LUTs can be
used independently. However, if one wants to
use both a LUT and a FF in the same LE they
have to be connected in the order shown.
Logic Elements (LEs)
Logic Elements (LEs)

The FPGA LUT (Look-Up Table) is a small
ROM with several address inputs and one
data output. A common size is 16x1 bit, it has
four inputs and one output. By setting the
proper bits in that ROM, it becomes any
desired boolean logic function having up to
four inputs and one output. That's why it is
sometimes called a function generator.
 Cascade Chain

The cascade
chain can use
a logical AND
or logical OR
(via
DeMorgan’s
inversion) to
connect the
outputs of
adjacent LEs.
Avalon Switch Fabric

Avalon switch fabric ?

Nios II uses the Avalon switch fabric as the
interface to its embedded peripherals. Compared
to a traditional bus in a processor-based system,
which lets only one bus master access the bus at
a time, the Avalon switch fabric, using a slave-
side arbitration scheme, lets multiple masters
operate simultaneously.
Six different interface types

Avalon Memory Mapped Interface (Avalon-MM) - an address-based
read/write interface typical of master–slave connections.

Avalon Streaming Interface (Avalon-ST) - an interface that supports
the unidirectional flow of data, including multiplexed streams, packets,
and DSP data.

Avalon Memory Mapped Tristate Interface - an address-based
read/write interface to support off-chip peripherals. Multiple peripherals
can share data and address buses to reduce the pin count of an FPGA
and the number of traces on the PCB.

Avalon Clock - an interface that drives or receives clock and reset
signals to synchronize interfaces and provide reset connectivity.

Avalon Interrupt - an interface that allows components to signal events
to other components.

Avalon Conduit - an interface that allows signals to be exported out at
the top level of an SOPC Builder system where they can be connected
to other modules of the design or FPGA pins.
Wishbone

Wishbone
The Wishbone specification is now controlled by
OpenCores.org. The Wishbone IP core bus was
developed to interconnect IP cores within an FPGA
and does not support external buses. The Wishbone
developer site had provided VHDL code, but that site
has been off-line for months. The specification is
always available by the link provided above. The
Wishbone standard allows IP core interconnection, but
the VHDL code may have to be developed as needed.
The Full title: WISHBONE System-on-Chip (SoC)
Interconnection Architecture for Portable IP Cores