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    Paul Schmitz
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    The document contains a table describing the operation codes of an instruction set architecture. It lists the operation code values in binary, along with the corresponding mnemonic operation and description. The operations include arithmetic logic unit (ALU) operations, data transfer between registers and memory, conditional and unconditional jumps, subroutine calls and returns. The table also identifies the register operands and destination for each operation.

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    The document contains a table describing the operation codes of an instruction set architecture. It lists the operation code values in binary, along with the corresponding mnemonic operation and description. The operations include arithmetic logic unit (ALU) operations, data transfer between registers and memory, conditional and unconditional jumps, subroutine calls and returns. The table also identifies the register operands and destination for each operation.

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    © All Rights Reserved
    Download as ODS, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    11 views3 pages

    Opcodes

    Uploaded by

    Paul Schmitz
    The document contains a table describing the operation codes of an instruction set architecture. It lists the operation code values in binary, along with the corresponding mnemonic operation and description. The operations include arithmetic logic unit (ALU) operations, data transfer between registers and memory, conditional and unconditional jumps, subroutine calls and returns. The table also identifies the register operands and destination for each operation.

    Copyright:

    © All Rights Reserved
    Download as ODS, PDF, TXT or read online from Scribd
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    of 3

    Tabelle1

    F E D C B A 9 8 7 6 5 4 3 2 1 0 SHT
    0 0 0 0 0 0 0 0 NOP
    0 0 0 0 0 0 0 1 HLT
    0 0 0 0 0 0 1 0 Reg1 Reg2 CP
    0 0 0 0 0 0 1 1 Reg1 NUL
    0 0 0 0 0 1 0 0 Reg1 MemReg LD
    0 0 0 0 0 1 0 1 Reg1 LDI
    0 0 0 0 0 1 1 0 Reg1 Reg2 MV
    0 0 0 0 0 1 1 1
    0 0 0 0 1 0 0 0 Reg1 Reg2 WRM
    0 0 0 0 1 0 0 1 Reg1 RTL
    0 0 0 0 1 0 1 0 Reg1 RTR
    0 0 0 0 1 0 1 1 Reg1 SHL
    0 0 0 0 1 1 0 0 Reg1 SHR
    0 0 0 0 1 1 0 1 bit Reg1 TST
    0 0 0 0 1 1 1 0 JMP
    0 0 0 0 1 1 1 1
    0 0 0 1 ALU Code Reg1 Reg2 ALU
    0 0 1 0 0 0 0 0 CAL
    0 0 1 0 0 0 0 1 RET
    0 0 1 0 0 0 1 0
    0 0 1 0 0 0 1 1

    Seite 1
    Tabelle1

    Description Register ID
    00
    01
    Reg1→Reg2 02
    03
    Load Content from memory location in MemReg to Reg1 04
    Load content from next memory location to Reg1 05
    Reg1→Reg2; Reg1→0 06
    07
    Write content of Reg1 into Memory location Reg2
    Rotate Left Hidden F0
    Rotate Right F1
    Shift left
    Shift right
    Test if bit is set in Reg1
    Jump to Address indicated in Jump register

    Puts the result into the output register


    JMP and update PCCALL with current PC
    Return from CAL, put back PCCALL to PC

    Seite 2
    Tabelle1

    Description
    General #1
    General #2
    General #3

    ALUResult
    Jump
    Output

    PC
    PCCALL

    Seite 3

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