74 3 Computer organization

Table 3.2 Data movement instructions

Mnemonic Fmt. Description

MOV reg1,reg2 1 Move register to register: moves the contents of register reg2 to
register reg1.
RTL: reg1 reg2
Example: MOV R1,R2
MOV reg1,[reg2] 1 Move register to register indirect: moves the contents of absolute
memory address pointed by reg2 to register reg1.
RTL: reg1 [reg2]
Example: MOV R0,[R2]
MOV [reg1],reg2 1 Move register indirect to register: moves the contents of register
reg2 to absolute memory address pointed by reg1.
RTL: [reg1] reg2
Example: MOV [R3],R0
MOV reg,addr 4 Move register to memory: moves the contents of memory address
addr to register reg.
RTL: reg [addr]
Example: MOV R1,0x401F
MOV addr,reg 4 Move memory to register: moves the contents of register reg to
memory address addr.
RTL: [addr] reg
Example: MOV 0x40F5,R1
LDR reg,data 4 Load register low byte: loads the contents of register reg to con-
stant value specified by data.
RTL: reg data.
Example: LDR R0,0x0101
SPB reg1,reg2 1 Split into bytes: moves the high byte of register reg2 to the low
byte of register reg1. Sets the high bytes of registers reg1 and
reg2 to zero. Aimed to split reg2 into two bytes in reg2 and
reg1.
RTL: reg10,7 reg28,15 ; reg18,15 0x00;
reg28,15 0x00
Example: MHB R2,R3
MLB reg1,reg2 1 Merge low byte: moves the low byte of register reg2 into the low
byte of register reg1.
RTL: reg10,7 reg20,7
Example: MLB R3,R2
MHB reg1,reg2 1 Merge high byte: moves the low byte of register reg2 into the high
byte of register reg1.
RTL: reg18,15 reg20,7
Example: MHB R3,R2

SEP16 instruction set (I)

3.4 Machine language 75

Table 3.3 Arithmetic instructions

Mnemonic Fmt. Description

ADD reg1,reg2 1 Add register to register: adds register reg1 and register reg2 and store
the result in reg1. Affects flags N,Z and C.
RTL: reg1 (reg1+reg2)
Example: ADD SP,R2
ADD reg,data 4 Add data to register: adds the immediate value data to register reg.
Affects flags N,Z and C.
RTL: reg (reg+data)
Example: ADD R1,0xFF01
ADC reg1,reg2 1 Add with carry register to register: adds with carry register reg1 and
register reg2 and stores the result in reg1. Affects flags N,Z and C.
RTL: reg1 (reg1+reg2+C)
Example: ADC R1,R2
ADC reg,data 4 Add with carry data to register: adds with carry the immediate value
data to register reg. Affects flags N,Z and C.
RTL: reg (reg+data+C)
Example: ADC R1,0xFF01
SUB reg1,reg2 1 Substract register to register: substracts register reg2 to register reg2
and stores the result in reg1. Affects flags N,Z and C.
RTL: reg1 (reg1-reg2)
Example: SUB SP,R2
SUB reg,data 4 Substract data to register: substracts immediate value data to register
reg. Affects flags N,Z and C.
RTL: reg (reg-data)
Example: SUB R1,0xFF01
SBC reg1,reg2 1 Substract with carry register to register: substracts with carry register
reg2 to register reg1 and stores the result in reg1. Affects flags N,Z
and C.
RTL: reg1 (reg1-reg2-C)
Example: SBC R1,R2
SBC reg,data 4 Substract with carry data to register: substracts with carry the immedi-
ate value data to register reg. Affects flags N,Z and C.
RTL: reg (reg-data-C)
Example: SBC R1,0xFF01
INC reg 2 Increment register: increments register reg. Affects flags N,Z and C.
RTL: reg (reg+1)
Example: INC SP
DEC reg 2 Decrement register: decrements register reg. Affects flags N,Z and C.
RTL: reg (reg11)
Example: INC R1

SEP16 instruction set (II)

76 3 Computer organization

Table 3.4 Logic instructions

Mnemonic Fmt. Description

CMP reg1,reg2 1 Compare register to register: compares register reg1 to register reg2.
Affects flags N,Z and C.
RTL: PSR (reg1 ? reg2)
Example: CMP R0,R2
CMP reg,data 4 Compare register to data: compares register reg to immediate value
data. Affects flags N,Z and C.
RTL: PSR (reg ? data)
Example: CMP R0,0xFFFF
AND reg1,reg2 1 And register to register: performs the logical AND of register reg1 and
register reg2 and stores the result in reg1. Affects flags N,Z and C.
RTL: reg1 (reg1&reg2)
Example: AND R1,R2
AND reg,data 4 And register to data: performs the logical AND of register reg and
immediate value data and stores the result in reg. Affects flags N,Z
and C.
RTL: reg (reg&data)
Example: AND R1,0xFF00
OR reg1,reg2 1 Or register to register: performs the logical OR of register reg1 and
register reg2 and stores the result in reg1. Affects flags N,Z and C.
RTL: reg1 (reg1|reg2)
Example: OR R1,R2
OR reg,data 4 Or register to data: performs the logical OR of register reg and imme-
diate value data and stores the result in reg. Affects flags N,Z and
C.
RTL: reg (reg|data)
Example: OR R1,0xFF00
XOR reg1,reg2 1 Xor register to register: performs the logical eXclusive OR of register
reg1 and register reg2 and stores the result in reg1. Affects flags
N,Z and C.
RTL: reg1 (reg1 xor reg2)
Example: OR R1,R2
XOR reg,data 4 Xor register to data: performs the logical eXclusive OR of register reg
and immediate value data and stores the result in reg. Affects flags
N,Z and C.
RTL: reg (reg xor data)
Example: OR R1,0xFF00
BIC reg1,reg2 1 Bit Clear register to register: performs an reg1 AND NOT reg2 op-
eration and stores the result in reg1. Clears the bits of reg1 indicated
by a 1 in reg2. Affects flags N,Z and C.
RTL: reg1 (reg1 & ⇠ reg2)
Example: BIC R1,R"
BIC reg,data 4 Bit Clear register to data: performs an reg AND NOT data operation
and stores the result in reg. Clears the bits of reg indicated by a 1 in
data. Affects flags N,Z and C.
RTL: reg (reg1 & ⇠ data)
Example: BIC R1,0xFF00
SHL reg,data4 1 Shift left register: shifts left the contents of register reg a number of
times given by data4. Shift is performed through carry flag C. Value
data4 is a 4-bit integer in range [0,15]. Affects flags N,Z and C.
RTL: (C reg31 reg30 · · · reg1 reg0 0) * data4 times.
Example: SHR R1,0x0A
SHR reg,data4 1 Shift right register: shifts right the contents of register reg a number of
times given by n. Shift is performed through carry flag C. Value n is a
4-bit positive integer in in range [0,15]. Affects flags N,Z and C.
RTL: (0 ! C ! reg31 ! reg30 ! · · · ! reg1 ! reg0 ) * data4 times.
Example: SHL R1,0x0A

SEP16 instruction set (III)

3.4 Machine language 77

Table 3.5 Control flow and stack handling instructions

Mnemonic Fmt. Description

J cond,addr 4 Jump: set the PC value to addr if cond is met, otherwise set the PC to
point to the next instruction. See cond table.
RTL: if (cond) PC addr; else PC (PC+2); end
Example: JEQ 0x20FF
J cond,[reg] 1 Jump indirect: set the PC value to the contents of register reg if cond is
met, otherwise set the PC to pint to the next instruction. See cond table.
RTL: if (cond) PC reg; else PC (PC+1); end
Example: JEQ R3
C cond,addr 4 Call subroutine pointed by address addr. If cond is met, it pushes the
return address onto the stack and jumps to addr, i.e., sets the PC to addr,
otherwise set the PC to point to the next instruction.See cond table.
RTL: if (cond) [SP] PC; SP (SP-1); PC addr;
else PC (PC+2); end
Example: CAL 0x27FF
C cond,[reg] 1 Call indirect subroutine pointed by address addr. If cond is met, it
pushes the return address onto the stack and jumps to address pointed by
reg, i.e., sets the PC to [reg], otherwise set the PC to point to the next
instruction.See cond table.
RTL: if (cond) [SP] PC; SP (SP-1); PC addr;
else PC (PC+2); end
Example: CAL R3
RET 3 Subroutine return: it pops the value (memory address) on top of the stack
onto the PC and jumps to it.
RTL: SP (SP+1); PC [SP];
Example: RET
PUSH reg 2 Push register: it pushes reg onto the stack.
RTL: [SP] reg; SP (SP-1);
Example: PUSH R3
POP reg 2 Pop register: it pops the value on top of the stack onto register reg.
RTL: SP (SP+1); reg [SP];
Example: POP R3
PUSHSR 3 Push PSR: it pushes the processor status word (PSR) onto the stack.
RTL: [SP] PSR; SP (SP-1);
Example: PUSHSR
POPSR 3 Pop PSR: it pops the value on top of the stack onto the processor status
word (PSR).
RTL: SP (SP+1); PSR [SP];
Example: POPSR
NOP 3 No Operation: It does really nothing, except consuming execution time
and memory space.
RTL:
Example: NOP
STOP 3 Stops the processor: It stops the processor (waiting for some interrupt).
RTL:
Example: STOP

SEP16 instruction set (IV)

78 3 Computer organization

Table 3.6 Conditional codes

Mnemonic Description Flags tested

AL Always.
Always; unconditionally. None
EQ Equal.
If the Z flag is set after a comparison. Z==1
NE Not equal.
If the Z flag is clear after a comparison. Z==0
CS or HS Carry Set or Unsigned Higher or Same.
If the C flag is set after an arithmetical operation OR a shift op- C==1
eration, the result of which cannot be represented in 16 bits. It is
the carry out of bit 15.
CC or LO Carry Clear or Unsigned Lower..
The negated of CS. C==0
MI Minus: negative.
If the N flag is set after an arithmetical operation. N==1
PL Plus: positive or zero
If the N flag is clear after an arithmetical operation. For the pur- N==0
poses of defining ’plus’, zero is positive because it isn’t nega-
tive...
VS Signed overflow.
It is the exclusive-OR of the carries from bits 14 and 15. V==1
VC No signed overflow
Ther negated of VS. V==0
HI Unsigned Higher.
If after a substraction or comparison the C flag is set AND the Z C==1 && Z==0
flag is clear.
LS Unsigned Lower or Same.
If after a substraction or comparison the C flag is clear OR the Z C==0 || Z==1
flag is set.
GE Signed Greater or Equal.
If after a substraction or comparison the N flag is equal to the V N==V
flag.
LT Signed Less Than.
The negated of GE. N != V
GT Signed Greater Than.
If after a a substraction or comparison the N flag is equal to the N==V && Z==0
V flag AND the Z flag is clear.
LE Signed Less or Equal.
The negated of GT. N!=V || Z==1

SEP16 instruction set (V)