Journal of

Low Power Electronics

and Applications

Article
An Improved CMOS Design of Op-Amp Comparator
with Gain Boosting Technique for Data
Converter Circuits
Anil Khatak 1, * , Manoj Kumar 2 and Sanjeev Dhull 3
1 Department of Biomedical Engineering, Guru Jambheshwar University of Science and Technology, Hisar,
Haryana 125001, India
2 University School of Information, Communication & Technology (USICT), Guru Gobind Singh Indraprastha
University, New Delhi 110078, India; manojtaleja@ipu.ac.in
3 Department of ECE, Guru Jambheshwar University of Science and Technology, Hisar, Haryana 125001, India;
sanjeevdhull@gjust.org
* Correspondence: anil1984@gjust.org or khatak10anil@gmail.com; Tel.: +91-941-601-5001




Received: 16 August 2018; Accepted: 18 September 2018; Published: 25 September 2018


Abstract: A modified architecture of a comparator to achieve high slew rate and boosted gain with an
improvement in gain design error is introduced and investigated in this manuscript. It employs the
conventional architecture of common-mode current feedback with the modified gain booster topology
to increase gain, slew rate, and reduced gain error from the conventional structure. Observation
from the simulation results concludes that the modified structure using 24 transistors shows power
dissipation of 362.29 µW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is
a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric
slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the
standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture.
A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte
Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance
parameters in terms of power consumption and slew rate with the reduction in gain error.

Keywords: cascode; current mirrors; power consumption (PC); common mode feedback (CMFD);
gain boosting (GB); complementary mosfet technology (CMOS)

1. Introduction
One of the most significant and critical elements of analog integrated circuits are comparators [1,2].
Comparators play a pivotal role in regulating the decisive parameters of many imperative analog
and digital circuits [3]. Data converters are one such kind of circuit as their speed of conversion,
resolution, and power consumption, along with other prominent parameters, depends directly on
it [4–6]. The CMOS fabrication technologies have entered the submicron domain, and transistor sizing
is scaling down to nano-dimension levels. This, in turn, restrains the maximum power supply voltage
in ICs eventually allowing an audit of the fidelity of these MOS transistors [6–8]. This effect is positive
for digital ICs, but has an adverse impact on analog ICs. The primary consequences of this scaling
are reduced output conductance and small output voltage swing and, hence, led to decreased DC
gains [9]. Thus, the op-amp comparators designed under such CMOS technologies with restrained
supply voltage will not be able to comply with the designer requisites and, thus, adversely affect the
performance parameters of abstract circuits that employ these comparators as their core element [10].
Data converters, such as ADC and DAC conversion speed and accuracy, sturdily depend upon the
comparator’s capability to detect the smallest voltage levels [11,12]. The op-amp comparators with a

J. Low Power Electron. Appl. 2018, 8, 33; doi:10.3390/jlpea8040033 www.mdpi.com/journal/jlpea

J. Low
J. Low Power
Power Electron.
Electron. Appl.
Appl. 2018, 8, 33
2018, 8, x FOR PEER REVIEW 22 of
of 16
16

and accuracy, sturdily depend upon the comparator’s capability to detect the smallest voltage levels
[11,12].
high The
slew op-amp
rate and highcomparators
gain with withhigh aaccuracy
high slew arerate and
to be high gain
designed with high
in order accuracy
to attain are to be
these excellent
designed inin
parameters order
datatoconverters
attain these excellent parameters in data converters [13,14].
[13,14].
A modified architecture is proposed in this paper, which which suggests
suggests useful data information in
understanding the
understanding theperformance
performance of op-amp
of op-amp comparators.
comparators. BetterBetter optimization
optimization for providing
for providing an accuratean
accurate differential
differential mode gain mode andgain
high and high
slew slew
rate rate is achieved
is achieved through through this design
this design [14]. [14].
Thus,Thus, to meet
to meet the
the requirement
requirement of gain
of gain in the
in the op-amp
op-amp comparator
comparator modified
modified architecture
architecture withwith
gaingain a boosting
a boosting block
block is
is used.
used. Common
Common mode
mode feedback
feedback (current
(current feedback)
feedback) is used
is used in in
thethe circuit
circuit of of
thethe op-amp
op-amp comparator
comparator to
to maintain
maintain thethe output
output nodenode at constant
at constant DC [15].
DC [15]. Current
Current biasing
biasing of theofmodified
the modified
designdesign
is done is by
done by
using
using current
current mirrorsmirrors [16].common
[16]. The The common mode mode feedback
feedback with modified
with modified architecture
architecture andboosting
and gain gain boosting
block
block provides
provides a very ahigh
verygain
high gainanwith
with an improved
improved gain
gain error byerror
moreby more
than 95% than
[17].95%
The[17].
use The
of theuse of the
cascode
cascodemirror
current currentstructure
mirror structure in thefeedback
in the current current amplifier,
feedback amplifier,
in additionintoaddition
the highto the also
gain, highprovides
gain, also a
provides
very highaslew
veryrate
high[18].
slew rate [18].
This manuscript
manuscript isis further
furtherassembled
assembledasasfollows:
follows:Section
Section2 dispenses
2 dispenses a quick overview
a quick overview of the
of
modified
the circuit
modified description
circuit in thein
description form
the of a circuit.
form of a Section
circuit. 3Section
provides3 details
provides about the simulation
details about the
results and results
simulation explanations of the analysis
and explanations of the
of the modified
analysis architecture.
of the Section 4 contains
modified architecture. Section comparisons
4 contains
of the modified
comparisons architecture
of the modified with existingwith
architecture op-amp comparators,
existing like DCFIA, like
op-amp comparators, SCFIA [19], and
DCFIA, SCFIA CMFD
[19],
[20–23],
and CMFD which utilize
[20–23], whichcommon
utilize mode
common current
modefeedback through through
current feedback tables and graphs.
tables The paper
and graphs. The
concludes
paper with Section
concludes 5.
with Section 5.

2. Circuit Description

Figure 1 depicts the block architecture for common-mode feedback structure [20]. It incorporates
three major blocks. First, there is a fully
fully differential
differential pair amplifier that works in balanced
balanced mode. Next,
Next,
there is a sensing circuit stage which senses common mode output signal. In the final stage, there is
a comparator which compares this output common mode signal with a reference voltage and feeds
the rectified signal back to the fully differential pair that, in turn,
turn, adjusts
adjusts according
according to
to this
this signal
signal [21].
[21].
The reference voltage ideally equals 0 V. Thus, a rectified signal is formed and applied to the fully
differential pair, such that, finally,
finally, the
the alteration
alteration signal
signal becomes
becomes near
near to zero. The rectified signal is a
subtracted value taken by subtracting the reference
reference voltage
voltage and
and the
the common-mode
common-mode signal
signal [22,24].
[22,24].

Figure 1. Block structure of current mode feedback op-amp.

Figure 2
Figure 2 shows
shows the
the entire
entire architecture
architecture ofof the
the modified
modified op-amp
op-amp comparator
comparator (GB-CMFD)
(GB-CMFD) with with
gain
gain boosting and common
boosting and common mode mode current
current feedback
feedback [23–25].
[23–25]. Inputs
Inputs are
are given
given to
to the
the dual
dual input
input fully
fully
differential
differential pair
pair that
that comprises
comprises of of M1
M1 and
and M2M2 MOSFETS.
MOSFETS. The output of
The output of this
this differential
differential pair
pair is
is taken
taken
from the output node which incorporates folded cascode current mirrors as source and
from the output node which incorporates folded cascode current mirrors as source and sink. M4, M5, sink. M4, M5,
M6,
M6, and
and M7
M7 form
form aa current
current source
source while,
while, on
on the
the other
other hand,
hand, M8,
M8, M9,
M9, M10,
M10, and
and M11
M11 forms
forms aa current
current
sink [26]. The sensing circuit comprises Ms1 and Ms2, which sense the common mode
sink [26]. The sensing circuit comprises Ms1 and Ms2, which sense the common mode signal from signal from the
output node. Next, this signal is compared with the reference voltage through a comparator
the output node. Next, this signal is compared with the reference voltage through a comparator circuit
through M3 andM3
circuit through M12.
and M12.
J. Low Power Electron. Appl. 2018, 8, 33 3 of 16
J. Low Power Electron. Appl. 2018, 8, x FOR PEER REVIEW 3 of 16

Further,
Further, the
the correction
correction signal
signal is
is fed
fed to
to the
the fully
fully differential
differential pair
pair through
through M3
M3 and,
and, thus,
thus, it
it adjusts
adjusts
its
its operating current according to the correction signal and reduces the common mode gain. A
operating current according to the correction signal and reduces the common mode gain. A gain
gain
booster
booster block
block which
which includes MG1, MG2,
includes MG1, MG2, MG3,
MG3, and
and MG4
MG4 isis also
also added
added along
along with
with this
this circuit.
circuit. This
This
block is responsible for the gain boosting.
block is responsible for the gain boosting.

Figure 2. Modified GB-CMFD comparator circuit.

The difference
difference signal
signaltaken
takenfromfromthe
the differential
differential pair
pair M1M1andand
M2M2 is amplified
is amplified further
further bynext
by the the
next
stage,stage,
which which comprises
comprises of eight
of eight MOS MOS devices.
devices. RA and RARBand
areRthe
B are the output
output resistances
resistances at output
at output nodes
nodes
vout(+)vout(+) and vout(
and vout(−), −), respectively.
respectively. These output
These output resistances
resistances are responsible
are responsible for theforhigh
the output
high output
gain
gain
of theofop-amp
the op-amp comparator
comparator circuit
circuit as the
as the gain
gain of of any
any amplifier
amplifier is isestimated
estimatedby bythetheproduct
product ofof its
transconductance
transconductance and andoutput
outputresistance. M8,
resistance. M9,M9,
M8, M10, andand
M10, M11M11MOSMOS devices are arranged
devices and biased
are arranged and
in such a manner as to provide high resistance to the output nodes.
biased in such a manner as to provide high resistance to the output nodes.
In the
the final
finalsegment
segmentofofthe theoperational
operationalamplifier comparator,
amplifier comparator,the the
gaingain
booster blockblock
booster interacts with
interacts
the M8 and M9 MOS devices. The output from the drain terminal of M8
with the M8 and M9 MOS devices. The output from the drain terminal of M8 and M9 NMOS devicesand M9 NMOS devices is
fed into
is fed thethe
into gate terminal
gate terminal of of
MG4MG4 and
andMG3
MG3 MOSFET
MOSFET devices,
devices,respectively,
respectively, which
which are
areworking
working inina
common
a commonsource
sourceamplifier
amplifierconfiguration.
configuration.The TheMOS
MOSdevices
devicesMG2MG2and andMG1MG1are are biased
biased with
with a voltage
vb3 and connected to the drain terminal of MG4 and MG3 devices to increase the resistance at the
output terminal. Thus,
Thus, the
the output
output of the op-amp comparator
comparator getsgets enhanced
enhanced by the gain of the gain
booster block and is again fed back to the gate terminal of M8 and M9 devices and, thus, the overall
output gain of operational amplifier comparator
comparator getsgets boosted.
boosted.
Major differences in this modified schematic with respect to the general CMFD topology [23–25]
are the less complicated structure by utilizing fewer MOS devices, which ultimately reduces power
consumption of this modified structure. For For gain
gain boosting
boosting this
this structure
structure employs
employs only one gain
boosting block
block in
in the
the pull-down
pull-down section.
section.AsAsthere
thereare
arefewer
fewerMOSMOSdevices
devices inin
thethe pull-up
pull-up section,
section, it
it results in the fast charging of the output node, which eventually leads to
results in the fast charging of the output node, which eventually leads to a high slew rate.a high slew rate.

Mathematical
Mathematical Analysis
Analysis
Gain
Gain for
for the
the differential
differential pair
pair is
is given
given as:
as:

𝐺𝑎𝑖𝑛
Gain==𝐸𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒
E f f ective 𝑔gm · E𝐸𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒
f f ective R𝑅out (1)
(1)
where, gm is the effective trans-conductance and Rout is the effective output resistance [1,13]. Looking
where, gm is the effective trans-conductance and Rout is the effective output resistance [1,13]. Looking
at the output node Vout the resistance RB can be calculated as given in Equation (1):
at the output node Vout the resistance RB can be calculated as given in Equation (1):
(𝑟𝑑𝑠 𝑔 𝑟𝑑𝑠 𝑟𝑑𝑠 )
𝑅 = (rds + g ·rds ·rds )
7 𝑔 m9 𝑟𝑑𝑠 9 11
RB =
gm7 rds7
(𝑟𝑜 𝑔 𝑟𝑜 𝑟𝑜 )
𝑅 = (2)
𝑔 𝑟𝑜
Additionally, the current I7 that flows through this output node can be calculated as:
J. Low Power Electron. Appl. 2018, 8, 33 4 of 16

(ro7 + gm9 ·ro9 ·ro11 )

RB = (2)
gm7 ro7
Additionally, the current I7 that flows through this output node can be calculated as:
 
 gm2 (ro2 kro5 ) 
I7 = h  i .Vin (−)
gm9 . ro9 . ro11
2
gm7 ro7 + (ro2 kro5 ) 
 
 gm2 . Vin (−) 
I7 = n h  io (3)
 2 1 + gm9 . ro9 . ro11 . ( gds + gds ) 
gm7 ro7 2 5

From Equations (1) and (3) the output voltage gain comes out to be:
  
Vout g
m1
 gm2 . Vin (−) 
= + .R (4)
 2 1 + gm9 . ro9 . ro11 . ( gds + gds )  out
n h  io
Vin  2
gm7 ro7 2 5

where Rout is given as:

Rout = [ gm9 . ro9 . ro11 ] k [ gm7 ro7 (ro2 kro5 )]

Rearranging and solving the Equation (4) by assuming trans-conductance and output resistance
of all mirrors as gm and ro: ( )
2 . ro2
gm1
Vout
= (5)
Vin 4

Now, solving for the gain boosting circuit, Rout can be calculated as:

Rout = [ A. gm9 . ro9 . ro11 ] k [ gm7 ro7 (ro2 kro5 )]

Again, solving for gain: ( )

2 . ro2
A . gm1
Vout
= (6)
Vin 4

Comparing Equations (5) and (6) it can be easily concluded that with the modified architecture
the gain improves in comparison to the general common feedback structure [23–25].

3. Results
In this segment, all the required simulations, such as transient, AC analysis, along with parameter
variations of the modified circuit using a closed loop configuration is demonstrated. Monte Carlo
simulations have been performed by using SPICE in 90 nm CMOS technology. At least 20 iterations
are performed by utilizing the Monte Carlo simulation methods for concluding the final results.
An op-amp with a feedback circuit is designed to have a gain of 20. The design schematic blocks
of that are shown in Figure 3 [15,27].
parameter variations of the modified circuit using a closed loop configuration is demonstrated.
Monte Carlo simulations have been performed by using SPICE in 90 nm CMOS technology. At least
20 iterations are performed by utilizing the Monte Carlo simulation methods for concluding the final
results.
J. Low An op-amp
Power Electron.with a feedback
Appl. 2018, 8, 33 circuit is designed to have a gain of 20. The design schematic blocks
5 of 16
of that are shown in Figure 3 [15,27].

J. Low Power Electron. Appl. 2018, 8,Figure

x FOR PEERAnREVIEW
3. An operational amplifier with feedback. 5 of 16

Figure 44 represents
Figure represents the
the modified
modified circuit
circuit of
of the
the op-amp
op-amp comparator
comparator employing
employing common
common mode
mode
current feedback with folded cascoded current mirrors along with gain-boosting circuit. The channel
current feedback with folded cascoded current mirrors along with gain-boosting circuit. The channel
length of
length of 90
90 nm
nm and
and the
the channel width of
channel width of 11 μm
µm is
is used
used as
as the
the dimension
dimension ofof MOS
MOS devices in the
devices in the
proposed
proposed op-amp
op-amp comparator
comparator modified
modified architecture.
architecture.

Figure 4. Comparator
Comparator with modified gain boosting current feedback.

Table 11 shows
Table showsthe
thepower
powerconsumption,
consumption,maximum
maximumcurrent
currentdrawn,
drawn,and the
and rise
the time
rise and
time andfallfall
time of
time
thethe
modified op-amp (GB-CMFD) comparator. Simulation is done on a supply voltagevoltage
of 0.7 Vofat0.7 ◦
25 VC.
of modified op-amp (GB-CMFD) comparator. Simulation is done on a supply at
25 °C.
Table 1. Power consumption, current drawn, and rise and fall times of the modified GB-CMFD.
Table 1. Power consumption, current drawn, and rise and fall times of the modified GB-CMFD.
Supply Voltage = 0.7 V Temp = 25 ◦ C
Width (µm) PowerSupply Voltage(µW)
Consumption = 0.7 V Current Drawn (µA) Rise TimeTemp
(ps) = 25°
Fall Time (ps)
Width (µm) Power Consumption (µW) Current Drawn (µA) Rise Time (ps) Fall Time (ps)
1.0 362 517 7 7
1.0
1.5 362
390 517
558 77 77
1.5
2.0 390
416 558
595 77 77
2.0
2.5 416
436 595
623 77 77
2.5
3.0 436
454 623
649 77 77
3.5
3.0 472
454 674
649 77 77
4.0
3.5 489
472 699
674 77 77
4.5
4.0 506
489 724
699 77 77
5.0
4.5 524
506 748
724 77 77
5.0 524 748 7 7

Variations in the parameters when the channel width is varied from 1 μm to 5 μm are also
included in Table 1. This circuit draws a maximum current of 517 μA by consuming the power of 362
μW at 1 μm channel width. The values of power consumption and current drawn are increased by
44% when the channel width is increased to 5 μm. Figure 5a,b shows these variations graphically.
Table 1 also gives the details regarding the rising and falling duration for the output pulse and
 J. Low Power Electron. Appl. 2018, 8, 33 6 of 16

Variations in the parameters when the channel width is varied from 1 µm to 5 µm are also included
in Table 1. This circuit draws a maximum current of 517 µA by consuming the power of 362 µW at
1 µm channel width. The values of power consumption and current drawn are increased by 44% when
the channel width is increased to 5 µm. Figure 5a,b shows these variations graphically.
Table 1 also gives the details regarding the rising and falling duration for the output pulse and its
variation with channel width. Rise and fall times of 7 ps are observed for both rising and falling edges.
The variations in these values are negligible with the variation in channel width.
Figure 6 gives details regarding the output waveforms that are recorded with respect to the
input waves for the modified structure (CMFD-GB). The input voltage at the negative terminal is kept
J. constant
J. Low
Low Power atElectron.
Power 350 millivolts
Electron. Appl.
Appl. 2018, 8,and
2018, 8, then
x FOR
x FOR a varying
PEER
PEER REVIEWvoltage is applied at the positive terminal. The 6output
REVIEW 6ofof1616
waveform at the non-inverting terminal, which is recorded, is shown in Figure 6

600600
Power
Power Consumption
Consumption Current
Current drawn
drawn
750750
Power Consumption (µW)
Power Consumption (µW)

550550
700700

Current drawn (µA)

Current drawn (µA)
500500
650650

450450
600600

400400 550550

350350 500500

300300 450450
1 1 2 2 3 3 4 4 5 5
1 1 2 2 3 3 4 4 5 5
Channel
Channel Width
Width (µm)
(µm) Channel
Channel Width
Width (µm)
(µm)

(a)
(a) (b)
(b)
Figure5.5.
Figure
Figure 5.(a) Powerconsumption
(a)Power
Power consumptionvs.
consumption vs.channel
vs. channelwidth;
width;and (b)current
and(b)
(b) currentdrawn
current drawnvs.
drawn vs.channel
vs. channelwidth.
channel width.
width.

Figure6.6.
Figure
Figure 6.Output
Outputwaveforms
Output waveformsofof
waveforms ofCMFD-gain
CMFD-gainboosting
CMFD-gain boostingcomparator
boosting comparator(transient
comparator (transientanalysis).
(transient analysis).
analysis).

Table222shows
Table
Table showspower
shows powerconsumption,
power consumption,observed
consumption, observedclosed
observed closedloop
loopgain,
gain,open
openlooploopgain,
gain,gain error,and
gainerror,
error, and
and
slew
slew rate
rate ofof
thethe modified
modified GB-CMFD
GB-CMFD comparator.
comparator.
slew rate of the modified GB-CMFD comparator. Simulation
Simulation isis done
done at
at a a supply
supply voltage
voltage ofof 0.7
0.7 V V by
by
by
varyingthe
varying
varying thetemperature
the temperaturefrom
temperature from−5
from ◦
−55°C°C
− toto
C 5555
to 55 ◦
°C.
°C. C.

Table2.2.Power
Table Powerconsumption,
consumption,gain
gainerror,
error,slew
slewrate,
rate,and
andclosed
closedand
andopen
openloop
loopgain
gainofofthe
themodified
modified
GB-CMFDatatdifferent
GB-CMFD differenttemperatures.
temperatures.

Power
Power Open
Open SlewRate
Slew Rate SlewRate
Slew Rate
ObservedClosed
Observed Closed Gain
Gain
Temp(°C)
Temp (°C) Consumption
Consumption Loop
Loop (RiseTime)
(Rise Time) (FallTime)
(Fall Time)
LoopGain
Loop Gain(dB)
(dB) Error%%
Error
(µW)
(µW) Gain
Gain (V/µs)
(V/µs) (V/µs)
(V/µs)
J. Low Power Electron. Appl. 2018, 8, 33 7 of 16

Table 2. Power consumption, gain error, slew rate, and closed and open loop gain of the modified
GB-CMFD at different temperatures.

Power Observed Slew Rate Slew Rate

Open Loop Gain Error
Temp (◦ C) Consumption Closed Loop (Rise Time) (Fall Time)
Gain %
(µW) Gain (dB) (V/µs) (V/µs)
−5 365 13 953 0.69 839 839
0 364 13 953 0.69 839 839
5 364 13 953 0.69 839 839
15 363 13 1075 0.61 839 839
25 362 13 1075 0.61 839 839
35 361 13 1229 0.53 839 839
45 Electron. Appl.
J. Low Power 3612018, 8, x FOR PEER
13 REVIEW 1229 0.53 839 8397 of 16
55 362 13 1229 0.53 839 839
In Table 2 the variations in the power consumption are detailed. The modified circuit consumes
362 μW at 25 2°C.
In Table theThis value increases
variations marginally
in the power but remains
consumption close toThe
are detailed. 362 modified
μW whencircuit
the temperature
consumes
is raised to ◦
55 °C. On the other hand, when the temperature was reduced to −5 °C
362 µW at 25 C. This value increases marginally but remains close to 362 µW when the temperature the power
is
consumption
raised ◦
to 55 C.increased
On the otherfurther
hand,and
whenattained the valuewas
the temperature of reduced
365 μWtoat−−5 ◦
5 C°C.
theFigure
power7a shows the
consumption
variationsfurther
increased of powerandconsumption of 365 µW at −5 ◦ C. Figure 7a shows the variations of power
with temperature.
attained the value
consumption with temperature.

370 13.1 Observed Closed Loop Gain (dB) Designed Closed Loop Gain (dB) 13.1
Power consumption (µW)

Designed Closed Loop Gain (dB)

Observed Closed Loop Gain (dB)

13.1
Power consumption (µW)

368
13.0 13.0

365 13.0

12.9 12.9
363

12.9

360 12.8 12.8

0 10 20 30 40 50
-5 0 5 10 15 20 25 30 35 40 45 50 55
TEMPERATURE (Degree Celsius)
TEMPERATURE (Degree Celsius)

(a) (b)
1400
Open Loop Gain 0.8 Gain Error %

0.7
Open Loop Gain

Gain Error %

1200
0.7

0.6
1000
0.6

0.5
800 -5 0 5 10 15 20 25 30 35 40 45 50 55
0 10 20 30 40 50
TEMPERATURE (Degree Celsius) TEMPERATURE (Degree Celsius)

(c) (d)
Figure 7.
Figure 7. (a) Power
Power consumption
consumptionvs.vs.temperature;
temperature;(b)(b)observed
observedclosed loop
closed gain
loop vs.vs.
gain temperature; (c)
temperature;
(c) open
open loop
loop gain
gain vs.vs. temperature;
temperature; andand
(d)(d) gain
gain error
error vs.vs. temperature.
temperature.

Figure
Figure7b,c7b,cexhibit
exhibit the the
observed closedclosed
observed loop gain
loopand openand
gain loopopen
gain variations
loop gainwith temperature.
variations with
An observed closed loop gain of 12.93 decibels at 25 ◦ C is recorded, which is very close to the designed
temperature. An observed closed loop gain of 12.93 decibels at 25 °C is recorded, which is very close
closed loop gainclosed
to the designed of 13.01loopdecibels. Diminutive
gain of 13.01 decibels. level variations
Diminutive are variations
level recorded when the temperature
are recorded when the
varied from − 5 to 55 ◦ C. Open loop gain is then detailed with its variations with temperature. The open
temperature varied from −5 to 55 °C. Open loop gain is then detailed with its variations with
loop gain of 1075
temperature. Theisopen
observedloop for
gainthe
ofGB-CMFD structure
1075 is observed 25 ◦GB-CMFD
foratthe C, which isstructure
quite large
at as
25 compared
°C, whichto is
standard comparator structures. The open loop gain of 1075 is recorded for the
quite large as compared to standard comparator structures. The open loop gain of 1075 is recorded modified architecture
at ◦ ◦
for25theC,modified
which increases
architectureto 1229
at 25when the temperature
°C, which increases tois1229raised to 55
when theC. However, the
temperature open to
is raised loop
55
gain reduced to 953 when the temperature is reduced to − 5 ◦ C. Overall, the percentage variations of
°C. However, the open loop gain reduced to 953 when the temperature is reduced to −5 °C. Overall,
the
the open loop gain
percentage are 11%oftothe
variations 14% with
open thegain
loop variations
are 11% in to
temperature.
14% with the variations in temperature.
The gain error variations with temperature are shown in Table 2. Though the circuit is designed
in a closed loop configuration for the power gain of 20, which equals 13.01 dB, the values that are
obtained from the magnitude plot are marginally different at different temperatures. The gain error
is almost constant for the temperature range of −5 to 25 °C and has an error of 0.1% from the expected
value, which is relatively acceptable. Figure 7d shows the variations of gain error with temperature.
J. Low Power Electron. Appl. 2018, 8, 33 8 of 16

The gain error variations with temperature are shown in Table 2. Though the circuit is designed
in a closed loop configuration for the power gain of 20, which equals 13.01 dB, the values that are
obtained from the magnitude plot are marginally different at different temperatures. The gain error is
almost constant for the temperature range of −5 to 25 ◦ C and has an error of 0.1% from the expected
value, which is relatively acceptable. Figure 7d shows the variations of gain error with temperature.
Figure 8 represents the frequency response of the closed loop CMFD-GB structure. The variations
in theJ. closed loop gain with respect to temperature can be easily observed from this response.
Low Power Electron. Appl. 2018, 8, x FOR PEER REVIEW 8 of 16

J. Low Power Electron. Appl. 2018, 8, x FOR PEER REVIEW 8 of 16

Figure
Figure 8. Variations
8. Variations ininclosed
closedloop
loop gain
gain with
withtemperature
temperature(AC analysis).
(AC analysis).

In the end Table 2 gives the details regarding the slew

𝑉𝑂𝐿𝑇𝐴𝐺𝐸 rate of
𝐿𝐸𝑉𝐸𝐿 (𝑉)the modified gain boosting CMFD
𝑆𝐿𝐸𝑊 𝑅𝐴𝑇𝐸 =
comparator and its variations with temperature. 𝑅𝐼𝑆𝐸 𝑇𝐼𝑀𝐸Slew (µs) 𝑜𝑟 𝐹𝐴𝐿𝐿
rate 𝑇𝐼𝑀𝐸
is the (µs)
measure of the rate at which the
output voltage Figure
rises with 8.respect
Variations
to in closed
time [28]. loop
Thus,gainif with
a temperature
comparator has (AC
a analysis).
high slew
Thus, from the above relation, if a circuit has a very small value of rising time andrate, it will
fall time lead to
then
the high speed
it will of comparison
eventually have a very [29].
high slew rate.
From Table 1 the rise time and fall time for this 𝑉𝑂𝐿𝑇𝐴𝐺𝐸
modified 𝐿𝐸𝑉𝐸𝐿
GB-CMFD (𝑉) circuit are seven picoseconds
𝑆𝐿𝐸𝑊 𝑅𝐴𝑇𝐸 = VOLTAGE LEVELafter (V ) simulation is 0.006 V for
and the maximum minus SLEW RATE = 𝑅𝐼𝑆𝐸 𝑇𝐼𝑀𝐸 (µs) 𝑜𝑟 𝐹𝐴𝐿𝐿 𝑇𝐼𝑀𝐸the
minimum voltage range that is observed (µs)
both the rising and falling edge. Thus,RISE using TI MEvalues,
these (µs) or FALL
a slew TIofME
rate 839(µs ) is obtained for the
V/μs
Thus,
circuit,from
which the
is above
quite arelation,
high valueif aascircuit has atovery
compared the small value of rising
other comparators. time9a,b
Figure andshows
fall time
the then
Thus, from
it willvariations
eventually the
have
of the
above
a very
slew
relation,
high
rate for
if a circuit
slew rate.
charging
has a very small value
and discharging edge with temperature.
of rising time and fall time then it
will eventually
FromItTable have
can be thearise
1seen very
that high
time
this slew
and fallrate.
variation time
is veryfor this modified
minute and, thus,GB-CMFD circuit
this circuit has areslew
a high sevenratepicoseconds
which
From
and the Table
maximum
is almost 1 the
stable rise
minus
with time
minimumand fall
temperature time for
voltage
variations. rangethisthat
modified GB-CMFD
is observed after circuit are sevenispicoseconds
the simulation 0.006 V for
and the
both themaximum
rising andminus fallingminimum
edge. Thus, voltage
usingrange
these that
values, is observed
a slew rate after
of the
839 simulation is 0.006for
V/μs is obtained V the
for
both thewhich
circuit, risingisand falling
quite a high edge.
valueThus, using these
as compared to values,
the other a slew rate of 839Figure
comparators. V/µs 9a,bis obtained
shows thefor
920 GB-CMFD
the circuit,
variations which is quite a high value as compared to the
920
of the slew rate for charging and discharging edge with temperature. other comparators.
GB-CMFD Figure 9a,b shows the
900 900
Slew rate (rise time) (V/µs)

variations of the slew rate for charging and discharging edge

thus,with
this temperature.
Slew rate (fall time) (V/µs)

It can
880 be seen that this variation is very minute and, 880
circuit has a high slew rate which
It can
is almost be seen
stable
860 withthat this variation
temperature is very minute and,
variations. 860 thus, this circuit has a high slew rate which is

almost stable
840 with temperature variations. 840

820 820

800 800
920 GB-CMFD 920
780 780
GB-CMFD
900 900
Slew rate (rise time) (V/µs)

760 760
Slew rate (fall time) (V/µs)

880 -10 0 10 20 30 40 50 60 880-10 0 10 20 30 40 50 60

Temperature (degree celsius) Temperature (degree celsius)
860 860

840 (a) 840 (b)

820 820
Figure 9. (a) Slew rate (rising edge) vs. temperature; and (b) slew rate (falling edge) vs. temperature.
800 800

780 780
Table 3 summarizes the performance of the modified gain boosting CMFD comparator. CMOS
760 760
technology
-10 0
is used
10
to20design30 this circuit
40
with
50
the60 channel-10length 0of 90 nm
10
and20channel30
width 40
of 150μm. 60
A supply voltage of 0.7(degree
Temperature V is celsius)
deployed for the simulations. Twenty-fourTemperature MOS transistors
(degree celsius) are used for

designing the circuit, along with four capacitors and two resistors. The value of power consumption
at 25 °C is 362 μW while (a) drawing a current of 517 μA, both having a variation (b)of approximately 2%.
A total 9.
Figure of(a)
12.93
(a) Slew
Slewdecibels
rate of closed
rate (rising
(rising edge) loopvs.gain is observed
temperature;
temperature; andat(b)25 slew
°C, which is quiteedge)
rate (falling close vs.to the calculated
temperature.
gain of 13.01 decibels.
TableThe open loop gain
3 summarizes theofperformance
1075 is attained by this
of the structure
modified at 25
gain °C, which
boosting CMFDis large, compared CMOS
comparator. to
normal comparator structures. A gain error of 0.6% is obtained after simulation of this circuit at 25
technology is used to design this circuit with the channel length of 90 nm and channel width of 1 μm.
°C, which is relatively acceptable. A very high slew rate is achieved by this modified design that is
A supply voltage of 0.7 V is deployed for the simulations. Twenty-four MOS transistors are used for
designing the circuit, along with four capacitors and two resistors. The value of power consumption
J. Low Power Electron. Appl. 2018, 8, 33 9 of 16

Table 3 summarizes the performance of the modified gain boosting CMFD comparator. CMOS
technology is used to design this circuit with the channel length of 90 nm and channel width of 1 µm.
A supply voltage of 0.7 V is deployed for the simulations. Twenty-four MOS transistors are used for
designing the circuit, along with four capacitors and two resistors. The value of power consumption
at 25 ◦ C is 362 µW while drawing a current of 517 µA, both having a variation of approximately 2%.
A total of 12.93 decibels of closed loop gain is observed at 25 ◦ C, which is quite close to the calculated
gain of 13.01 decibels.
The open loop gain of 1075 is attained by this structure at 25 ◦ C, which is large, compared to
normal comparator structures. A gain error of 0.6% is obtained after simulation of this circuit at
25 ◦ C, which is relatively acceptable. A very high slew rate is achieved by this modified design that is
839 V/µs that will eventually lead to a very high speed of comparison and, thus, this comparator can
be utilized in designing high-speed analog circuits, such as ADCs and DACs [30–32].

Table 3. Comparison of results at 25 ◦ C.

Temperature 25 ◦ C
Technology CMOS
No. Of Mosfets 24
Channel Length 90 nm
Channel Width 1 µm
Supply voltage 0.7 V
Power consumption 362 µW
Current drawn 517 µA
Observed closed loop gain 13 decibels
Gain error % 0.6
Open loop gain 1075
Slew rate 839 V/µs

Table 4 summarizes the percentage variation of these parameters with temperature. Power
consumption varies substantially with the decrease in temperature. A total of 0.07% of marginal
variations are recorded for observed closed loop gain, which almost equals zero and is acceptable.
Open loop gain variations are then shown in the table, which varies from 12% at −5 ◦ C and 14% at
55 ◦ C. Significant variations in the gain error are recorded when the temperature scales down to −5 ◦ C
on the other hand, when the temperature increased to 55 ◦ C the variations are minimal. Almost null
variations are observed for the slew rate.

Table 4. Percentage variation with temperature.

Temperature −5 ◦ C to +55 ◦ C
Power consumption ∼
=0%
Observed closed loop gain ∼
=0%
Open loop gain 12% to 14%
Gain error 12% to 0.07%
Slew rate ∼
=0%

4. Comparison
To evaluate the proposed modified architecture of the op-amp comparator (GB-CMFD) three
more structures of the op-amp comparator are utilized for analyses and comparison. These three
structures are DCFIA, SCFIA [19], and CMFD [23,24]. The structural design of these three architectures
are depicted in Appendix A (Figures A1–A3). DCFIA and SCFIA are the amplifiers which employ
common mode current feedback from drain and source terminals [10]. CMFD is a common mode
current feedback with conventional cascode amplifier [23,24].
These three structures are again simulated in 90 nm CMOS technology. Results that are obtained
after Monte Carlo simulation are shown in Table 5.
J. Low Power Electron. Appl. 2018, 8, 33 10 of 16
J. Low Power Electron. Appl. 2018, 8, x FOR PEER REVIEW 10 of 16

Table 5. Comparison of simulations results at 25 ◦°C.

Table 5. Comparison of simulations results at 25 C.
GB-CMFD (Proposed
DCFIA [19] SCFIA [19] CMFD [23,24] GB-CMFD (Proposed
DCFIA [19] SCFIA [19] CMFD [23,24] Modified Architecture)
Modified Architecture)
Technology CMOS CMOS CMOS CMOS
Technology CMOS CMOS CMOS CMOS
No. Of Mosfets 19 21 20 24
No. Of Mosfets 19 21 20 24
Channel Length
Channel Length 9090nmnm 90nm
90 nm 90
90 nm
nm 90 nm
90 nm
Channel Width
Channel Width 1 1µm
μm 11 µm
μm 11 μm
µm 11 µm
μm
Supply voltage
Supply voltage 0.8VV
0.8 0.8VV
0.8 1.8
1.8 V 0.7 VV
0.7
Power consumption
Power consumption 1010µWμW 119
119 µWμW 1179 μW
1179 µW 362
362 µWμW
Observed closed loop
Observed closed loopgain(dB)
gain(dB) 13.2
13.2 13.5
13.5 13.1
13.1 13
13
Gain error % 1 3 0.8 0.6
Gain error % 1 3 0.8 0.6
Open loop gain 467 177 801 1075
Open
Slewloop
rategain 467
1 V/µs 177
1 V/µs 307801
V/µs 1075
839 V/µs
Slew rate 1 V/μs 1 V/μs 307 V/μs 839 V/μs

Figure 10
Figure 10 shows
shows the
the variations
variations in
in the
the power
power consumptions
consumptions for
for all
all four
four comparators
comparators structures
structures
when the temperature is varied from − 5 to +55 ◦ C. The proposed modified architecture, despite using
when the temperature is varied from −5 to +55 °C. The proposed modified architecture, despite using
24 MOS transistors, consumes power at a moderate level, which is approximately in
24 MOS transistors, consumes power at a moderate level, which is approximately in the range of 360the range of
360 µW.
μW. It also
It also shows shows marginal
marginal variations
variations withwith temperature
temperature variations.
variations.

DCFIA SCFIA CMFD GB-CMFD

1200
Power Consumption (µW)

1000

800

600

400

200

-200
-10 0 10 20 30 40 50 60
TEMPERATURE (Degree Celsius)

Figure 10. Power consumption vs. temperature.

Figure 11 shows the comparison of the gain error value for all four structures. It can be observed
from the curves that GB-CMFD has the least value of the percentage gain error. Maximum variations
in the gain error is shown by DCFIA
DCFIA and CMFD
CMFD structures
structures which increased substantially when
◦ C. SCFIA show the least variation with temperature
temperature varies
temperature from −
varies from −55 to
to +55
+55°C. SCFIA show the least variation with temperature but has more
gain error value than GB-CMFD.
J. Low Power Electron. Appl. 2018, 8, 33 11 of 16
J. Low Power Electron. Appl. 2018, 8, x FOR PEER REVIEW 11 of 16

GB-CMFD CMFD SCFIA DCFIA

35

30
%
Error %
25
Gain Error

20
Gain

15

10

0
-5 0 5 10 15 20 25 30 35 40 45 50 55
TEMPERATURE (Degree Celsius)

Figure 11. Gain error (%) vs. temperature.

Figure
Figure 1212illustrates
illustrates thethe
variations
variationsof observed closedclosed
of observed loop gain
loop forgain
all four
for comparator structures.
all four comparator
All four structures
structures. All fourare employed
structures areinemployed
the circuitinshown in Figure
the circuit shown 3, in
which
Figureis designed
3, which isfordesigned
a closed for
loopa
gain of 13.01 decibel. The values of actual closed-loop gain that are observed at different
closed loop gain of 13.01 decibel. The values of actual closed-loop gain that are observed at different temperatures
in the simulations
temperatures in theare then plotted
simulations in Figure
are then 12.inThe
plotted magnitude
Figure of the observed
12. The magnitude of theclosed
observedloop gain
closed
for
loopGB-CMFD is almost constant
gain for GB-CMFD is almostand very close
constant and to theclose
very designed
to theclosed loopclosed
designed value. loop
The magnitude
value. The
of observed of
magnitude closed loop gain
observed forloop
closed DCFIA decreases
gain for DCFIA withdecreases
the increase within temperature
the increase opposite to that
in temperature
of the observed
opposite to that ofCMFD closed loop
the observed CMFD gain value,
closed which
loop gainincreases withincreases
value, which the increasewithinthe
temperature.
increase in
The observed The
temperature. SCFIA closed SCFIA
observed loop gain values
closed loopare small
gain as compared
values are small as to compared
DCFIA and CMFD, and
to DCFIA but
substantially large as compared to GB-CMFD.
CMFD, but substantially large as compared to GB-CMFD.

DCFIA SCFIA CMFD GB-CMFD Designed closed loop gain)

15
(dB)
gain (dB)
loop gain

14
closed loop

13
Observed closed

12
Observed

11

-10 0 10 20 30 40 50 60
TEMPERATURE (Degree Celsius)

Figure 12.
Figure 12. Observed closed loop gain vs. temperature.

Figure 13 depicts the variations

variations in open
open loop
loop gain
gain with
with temperature.
temperature. The GB-CMFD structure
again shows the maximum magnitude of the open loop gain at different temperatures in comparison
to other structures.
J. Low Power Electron. Appl. 2018, 8, 33 12 of 16
J. Low Power Electron. Appl. 2018, 8, x FOR PEER REVIEW 12 of 16

GB-CMFD CMFD SCFIA DCFIA

2500

2000
Open Loop Gain

1500

1000

500

0
-5 0 5 10 15 20 25 30 35 40 45 50 55
TEMPERATURE (Degree Celsius)

Figure 13. Open loop gain vs. temperature.

Table 6 summarizes these parametric variations

variations of
of all
all four
four structures
structures atat different
different temperatures.
temperatures.
The modified
modified op-amp
op-ampcomparator
comparator(GB-CMFD)
(GB-CMFD)showsshowsthetheleast variation
least in in
variation comparison
comparison to others in all
to others in
six six
all parameters which
parameters areare
which taken intointo
taken consideration for for
consideration comparison.
comparison.

◦ C.
Table 6. Percentage
Table 6. Percentage variations
variations in
in parameters
parameterswhen
whenthe
thetemperature
temperaturechanges from−
changesfrom −55 to 55 °C.

CMFD GB-CMFD(Proposed
GB-CMFD (Proposed
Parameters
Parameters DCFIA [19] [19]SCFIA
DCFIA [19] [19] CMFD [23,24]
SCFIA
[23,24] Modified
ModifiedArchitecture)
Architecture)
Power
Power consumption
consumption 23 to 23
16 to 16 4 to 4
5 to 5 ∼
=3≅3 ∼
=≅00
Observed closed
Observed closed loop gain
loop gain 15 to 15
12 to 12 3 to 3
2 to 2 16 16
to to
15 15 ∼≅0
= 0
Open loop gain
Open loop gain 88 to 88
89 to 89 212 to
21230to 30 96 96
to to
94 94 1111toto1414
Gain error 16 to 11 1 to 6 15 to 16 12 to 0.07
Gain error ∼ 16 to 11 ∼ 1 to 6 15 to 16 12∼to 0.07
Slew rate (charging) =0 =0 1 to 6 =0
Slew raterate
Slew (charging)
(discharging) ∼
=1
≅0 ∼
=1
≅0 1 to
29 to 27 6 ∼
=0
≅0
Slew rate (discharging) ≅1 ≅1 29 to 27 ≅0

Table 77 gives
Table gives details
details regarding
regarding the
the comparison
comparison on
on the
the basis
basis of
of power
power consumption of this
consumption of this
comparator with other pertinent associated studies.
comparator with other pertinent associated studies.

7. Comparison
Table 7.
Table Comparison with
with other
other associated
associated studies.
studies.
Technology
Technology Supply
Supply Slew Channel
Channel Power
Power
Slew Rate
CMOS
CMOS Voltage
Voltage Rate Length
Length Consumption
Consumption

[29] 350350
nmnm 2.5 V2.5 V 161 V/μs
161 V/µs 350 nm
350 nm 456456
µWμW
[29] 350 nm
350 nm 2.5 V2.5 V 176 V/μs
176 V/µs 350 nm
350 nm 195 μW
195 µW
[32]
[32] 130130
nmnm 1.0 V1.0 V 130 nm
130 nm 100 μW
100 µW
[33] 180 nm
[33] 180 nm 1.1 V1.1 V – -- 180 nm
180 nm 1300 μW
1300 µW
[34] 180 nm -- -- 180 nm ∼ ≅750 μW
[34] 180 nm – – 180 nm =750 µW
[35] 65 nm 1.2 V -- 65 nm 2800 μW
[35] 65 nm 1.2 V – 65 nm 2800 µW
[36] 65 nm 1.2 V 65 nm 370 μW
[36] 65 nm 1.2 V 65 nm 370 µW
[37] 180 nm 0.7 V to 1.1 V 180 nm 420 μW
[37] 180 nm 0.7 V to 1.1 V 180 nm 420 µW
GB-CMFD (Proposed-
GB-CMFD 90 nm 0.7 V 839 V/μs 90 nm 362 μW
architecture) 90 nm 0.7 V 839 V/µs 90 nm 362 µW
(Proposed-architecture)

5. Conclusions
A modified architecture of an op-amp comparator to achieve a high slew rate and boosted gain
with an improvement in gain design error is proposed and investigated in this manuscript.
Deploying the gain booster block and common-mode current feedback structure, the modified
J. Low Power Electron. Appl. 2018, 8, 33 13 of 16

5. Conclusions
A modified architecture of an op-amp comparator to achieve a high slew rate and boosted gain
with an improvement in gain design error is proposed and investigated in this manuscript. Deploying
the gain booster block and common-mode current feedback structure, the modified architecture of the
op-amp comparator (CMFD-GB) achieves an improvement in the overall gain and slew rate with the
reduction in gain error and power consumption. An overall gain of 1075 is attained by implementing
an additional gain booster block at the end segment of the op-amp comparator that is approximately a
34% improvement as compared to the general common-mode current feedback structure. The rise and
fall time also get reduced due to this boosted gain which, in turn, leads to the very high slew rate for this
modified op-amp comparator structure. A slew rate of 839 V/µs is observed for this modified op-amp
comparator structure, which is quite high and which makes this comparator a prominent contender
for high-speed data converters circuits. Closed loop analysis of the modified op-amp comparator
structure is done by utilizing this structure for designing a closed feedback amplifier with a gain
of 13.01 dB. Results from the simulations depict that the observed and design gain is almost equal
for the CMFD-GB comparator with the value of 12.93 decibels. Comparing it to the general CMFD
structure, this is an approximately 27% reduction. Considerable reduction in power consumption is
also attained through this modified op-amp comparator structure. In spite of using more MOS devices,
the power consumption observed for this modified architecture is 362.29 µW, which almost equals
a 70% reduction as compared to general CMFD structure. The modified architecture of the op-amp
comparator along with high slew rate also shows symmetry for charging and discharging output edges
which makes it perfect for the designing of accurate and linear data converter circuits. Temperature
sensitivity of these parameters is also observed for the modified comparator architecture by simulating
this circuit at different temperatures. The results show an optimum variation of these critical parameters
with varying temperature for the modified op-amp comparator architecture (CMFD-GB) as compared
to three other architectures. Boosted gain and a large slew rate with optimum power consumption
of this modified op-amp comparator structure (CMFD-GB) increases its applicability in high-speed
analog and digital circuits, which are designed in ultra deep submicron technologies where high-speed
and low-power consumption are the essential design constraints.

Author Contributions: All the authors have contributed to the paper. The designing, writing, and executing the
simulations to observe and record the results along with analysis is done by A.K. The work is done under the
supervision of M.K. and S.D.
Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflict of interest.

Abbreviations
GB Gain boosting
CM Common mode
CMFD Common mode feedback
PC Power consumption
DCFIA Drain current feedback instrumentation amplifier
SCFIA Source current feedback instrumentation amplifier
J. Low Power Electron. Appl. 2018, 8, 33 14 of 16

J. Low
J. Low Power
Power Electron.
Electron. Appl.
Appl. 2018,
2018, 8,
8, xx FOR
FOR PEER
PEER REVIEW
REVIEW 14 of
14 of 16
16
J. Low Power Electron. Appl. 2018, 8, x FOR PEER REVIEW 14 of 16
Appendix A
Appendix A
Appendix
Appendix A
A

Figure
Figure
Figure
Figure A1.
A1. Drain
Drain
A1.A1. Drain
Drain currentfeedback
current
current
current feedbackinstrumentation
feedback
feedback instrumentation amplifier
instrumentation
instrumentation amplifier
amplifier
amplifier (DCFIA)
(DCFIA)
(DCFIA) schematic.
(DCFIA) schematic.
schematic.
schematic.

Figure A2. Source current feedback instrumentation amplifier (SCFIA) schematic.

Figure
Figure A2. Source currentfeedback
feedback instrumentation
instrumentation amplifier
amplifier (SCFIA) schematic.
Figure A2.A2. Source
Source current
current feedback instrumentation amplifier(SCFIA) schematic.
(SCFIA) schematic.

Figure A3. Common mode current feedback schematic.

Figure
Figure A3.Common
A3. Common mode
Common mode current
mode current feedback schematic.
Figure A3. currentfeedback
feedbackschematic.
schematic.
J. Low Power Electron. Appl. 2018, 8, 33 15 of 16

References
1. Jendernalik, W. An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors.
Circuits Syst. Signal Process. 2017, 36, 4829–4843. [CrossRef]
2. Ay, S.U. Energy Efficient Supply Boosted Comparator Design. J. Low Power Electron. Appl. 2011, 1, 247–260.
[CrossRef]
3. Savani, V.; Devashrayee, N.M. Design and Analysis of Low-Power High-Speed Shared Charge Reset
Technique Based Dynamic Latch Comparator. Microelectron. J. 2018, 74, 116–126. [CrossRef]
4. Xin, X.; Cai, J.; Xie, R.; Wang, P. Ultra-Low Power Comparator with Dynamic Offset Cancellation for SAR
ADC. Electron. Lett. 2017, 53, 1572–1574. [CrossRef]
5. Bindra, H.S.; Lokin, C.E.; Schinkel, D.; Annema, A.J.; Nauta, B. A 1.2-V Dynamic Bias Latch-Type Comparator
in 65-Nm CMOS With 0.4-MV Input Noise. IEEE J. Solid-State Circuits 2018, 53, 1902–1912. [CrossRef]
6. Richelli, A.; Colalongo, L.; Kovacs-Vajna, Z.; Calvetti, G.; Ferrari, D.; Finanzini, M.; Pinetti, S.; Prevosti, E.;
Savoldelli, J.; Scarlassara, S. A Survey of Low Voltage and Low Power Amplifier Topologies. J. Low Power
Electron. Appl. 2018, 8, 1–20. [CrossRef]
7. Savani, V.; Devashrayee, N.M. Analysis and Design of Low-Voltage Low-Power High-Speed Double Tail
Current Dynamic Latch Comparator. Analog Integr. Circuits Signal Process. 2017, 93, 287–298. [CrossRef]
8. Khatak, A.; Dhull, S.; Taleja, M.K. A Study on Advanced High Speed and Ultra Low Power ADC
Architectures. Indian J. Sci. Technol. 2017. [CrossRef]
9. Taghizadeh, A.; Koozehkanani, Z.D.; Sobhi, J. A New High-Speed Low-Power and Low-Offset Dynamic
Comparator with a Current-Mode Offset Compensation Technique. AEU—Int. J. Electron. Commun. 2017, 81,
163–170. [CrossRef]
10. Bano, S.; Narejo, G.B.; Ali Shah, S.M.U. Power Efficient Fully Differential Bulk Driven OTA for Portable
Biomedical Application. Electronics 2018, 7, 41. [CrossRef]
11. Khatak, A.; Kumar, M.; Dhull, S. Analysis of CMOS Comparator in 90nm Technology with Different Power
Reduction Techniques. Int. J. Electr. Comput. Eng. 2018, 8. [CrossRef]
12. Zahrai, S.A.; Onabajo, M. Review of Analog-To-Digital Conversion Characteristics and Design
Considerations for the Creation of Power-Efficient Hybrid Data Converters. J. Low Power Electron. Appl. 2018,
8, 12. [CrossRef]
13. Dubey, A.K.; Nagaria, R.K. Optimization for Offset and Kickback-Noise in Novel CMOS Double-Tail Dynamic
Comparator: A Low-Power, High-Speed Design Approach Using Bulk-Driven Load. Microelectron. J. 2018, 78,
1–10. [CrossRef]
14. Khorami, A.; Sharifkhani, M. A Low-Power High-Speed Comparator for Precise Applications. IEEE Trans.
Very Large Scale Integr. (VLSI) Syst. 2018, 1–12. [CrossRef]
15. Kumaravel, S.; Venkataramani, B. An Improved Recycling Folded Cascode OTA with Positive Feedback.
WSEAS Trans. Circuits Syst. 2014, 13, 85–93.
16. Ragheb, A.N.; Kim, H.W. Ultra-Low Power OTA Based on Bias Recycling and Subthreshold Operation with
Phase Margin Enhancement. Microelectron. J. 2017, 60, 94–101. [CrossRef]
17. Maloberti, F.; Pea-Perez, A.; Gonzalez-Diaz, V.R. Opamp Gain Compensation Technique for Continuous-Time
Σ∆ Modulators. Electron. Lett. 2014, 50, 355–356.
18. Khorami, A.; Sharifkhani, M. Excess Power Elimination in High-Resolution Dynamic Comparators.
Microelectron. J. 2017, 64, 45–52. [CrossRef]
19. Worapishet, A.; Demosthenous, A. Generalized Analysis of Random Common-Mode Rejection Performance
of CMOS Current Feedback Instrumentation Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 2015, 62,
2137–2146. [CrossRef]
20. Lee, J.Y.; Hwang, S.N. A High-Gain Boost Converter Using Voltage-Stacking Cell. Trans. Korean Inst.
Electr. Eng. 2008, 57, 982–984.
21. Ng, K.A.; Xu, Y.P. A Low-Power, High CMRR Neural Amplifier System Employing CMOS Inverter-Based
OTAs With CMFB Through Supply Rails. IEEE J. Solid-State Circuits 2016, 51, 724–737.
22. Mahdavi, S.; Noruzpur, F.; Ghadimi, E.; Khanshan, T.M. A New Fast Rail-to-Rail Continuous-Time
Common-Mode Feedback Circuit. In Proceedings of the 2017 MIXDES—24th International Conference
Mixed Design of Integrated Circuits and Systems, Bydgoszcz, Poland, 22–24 June 2017; pp. 387–391.
J. Low Power Electron. Appl. 2018, 8, 33 16 of 16

23. Haga, Y.; Zare-Hoseini, H.; Berkovi, L.; Kale, I. Design of a 0.8 Volt Fully Differential CMOS OTA Using the
Bulk-Driven Technique. In Proceedings of the 2005 IEEE International Symposium on Circuits and Systems,
Kobe, Japan, 23–26 May 2005; pp. 220–223.
24. Duque-Carrillo, J.F. Control of the Common-Mode Component in CMOS Continuous-Time Fully Differential
Signal Processing. Analog Integr. Circuits Signal Process. 1993, 4, 131–140. [CrossRef]
25. Bult, K.; Geelen, G.J.G.M. The CMOS Gain-Boosting Technique. Analog Integr. Circuits Signal Process. 1991, 1,
119–135. [CrossRef]
26. Hassanpourghadi, M.; Zamani, M.; Sharifkhani, M. A Low-Power Low-Offset Dynamic Comparator for
Analog to Digital Converters. Microelectron. J. 2014, 45, 256–262. [CrossRef]
27. Zhao, X.; Zhang, Q.; Wang, Y.; Deng, M. Transconductance and Slew Rate Improvement Technique for
Current Recycling Folded Cascode Amplifier. AEU—Int. J. Electron. Commun. 2016, 70, 326–330. [CrossRef]
28. Aggarwal, B.; Gupta, M.; Gupta, A.K. A Comparative Study of Various Current Mirror Configurations:
Topologies and Characteristics. Microelectron. J. 2016, 53, 134–155. [CrossRef]
29. Danesh, S.; Hurwitz, J.; Findlater, K.; Renshaw, D.; Henderson, R. A Reconfigurable 1 GSps to 250
MSps, 7-Bit to 9-Bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design. IEEE J.
Solid-State Circuits 2013, 48, 733–748. [CrossRef]
30. Miki, T.; Morie, T.; Matsukawa, K.; Bando, Y.; Okumoto, T.; Obata, K.; Sakiyama, S.; Dosho, S. A 4.2 MW 50
MS/s 13 Bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. IEEE J. Solid-State Circuits
2015, 50, 1372–1381. [CrossRef]
31. Maji, K.B.; Kar, R.; Mandal, D.; Ghoshal, S.P. An Evolutionary Approach Based Design Automation of Low
Power CMOS Two-Stage Comparator and Folded Cascode OTA. AEU—Int. J. Electron. Commun. 2016, 70,
398–408. [CrossRef]
32. Gupta, R.; Gupta, R.; Sharma, S. Design of High Speed and Low Power 4-Bit Comparator Using FGMOS.
AEU—Int. J. Electron. Commun. 2017, 76, 125–131. [CrossRef]
33. Khorami, A.; Sharifkhani, M. High-Speed Low-Power Comparator for Analog to Digital Converters.
AEU—Int. J. Electron. Commun. 2016, 70, 886–894. [CrossRef]
34. De La Fuente-Cortes, G.; Espinosa Flores-Verdad, G.; Gonzalez-Diaz, V.R.; Diaz-Mendez, A. A New CMOS
Comparator Robust to Process and Temperature Variations for SAR ADC Converters. Analog Integr. Circuits
Signal Process. 2017, 90, 301–308. [CrossRef]
35. Goll, B.; Zimmermann, H. A Comparator with Reduced Delay Time in 65-Nm CMOS for Supply Voltages
down to 0.65 V. IEEE Trans. Circuits Syst. II Express Briefs 2009, 56, 810–814. [CrossRef]
36. Chua, C.; Kumar, R.B.N.; Sireesha, B. Design and Analysis of Low-Power and Area Efficient N-Bit Parallel
Binary Comparator. Analog Integr. Circuits Signal Process. 2017, 92, 225–231. [CrossRef]
37. Rahmani, S.; Ghaznavi-Ghoushchi, M.B. Design and Analysis of a High Speed Double-Tail Comparator with
Isomorphic Latch-Preamplifier Pairs and Tail Bootstrapping. Analog Integr. Circuits Signal Process. 2017, 93,
507–521. [CrossRef]

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