LXD381 — Evaluation Board for

Octal E1 Applications
Developer Manual

January 2001

As of January 15, 2001, this document replaces the Level One document Order Number: 249213-001
LXD381 — Evaluation Board for Octal E1 Applications User Guide.
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXD381 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.

LXD381 — Evaluation Board for Octal E1 Applications Developer Manual

Contents
1.0 General Description .................................................................................................. 5
1.1 Features ................................................................................................................ 5
2.0 Evaluation Board Set-Up ......................................................................................... 7
2.1 LXD381 Packing List ............................................................................................. 7
2.2 Equipment Requirements...................................................................................... 7
2.3 Power Connections ............................................................................................... 7
2.4 Loopback Mode Selection ..................................................................................... 7
2.5 Receive Polarity Selection..................................................................................... 8
2.6 Output Enable Selection........................................................................................ 8
2.7 Unused Switches................................................................................................... 8
2.8 Back-End Interface Connection............................................................................. 8
2.9 Line Interface Connection ..................................................................................... 9
2.10 Line Interface Circuit ............................................................................................. 9
2.11 Board Protection.................................................................................................... 9
3.0 Evaluation Board Schematics.............................................................................10

Figures
1 LXD381 Evaluation Board ..................................................................................... 6
2 S2 Factory Switch Settings ................................................................................... 8
3 Typical Back-End Connector................................................................................. 9
4 Evaluation Board Schematic — Data/Control .....................................................10
5 Evaluation Board Schematic — Digital I/O..........................................................11
6 Evaluation Board Schematic — Analog 1 ...........................................................12
7 Evaluation Board Schematic — Analog 2 ...........................................................13

Tables
1 LOOP0 - 7 Switch Settings....................................................................................7

LXD381 — Evaluation Board for Octal E1 Applications Developer Manual iii

 Evaluation Board for Octal E1 Applications — LXD381

1.0 General Description

The LXD381 evaluation board is a versatile tool for engineers designing E1 short haul applications
using the LXT381.

The evaluation board operates in Hardware mode only. All device and channel controls are set
using jumper blocks and DIP switches.

The board provides banana jacks for both power and line interface connections. Connectors are
provided for each framer or back-end ASIC interface. An E1 pattern generator/analyzer may be
used to provide external signals for evaluation.

1.1 Features
• Hardware controllable
• ZIF LQFP socket for easy swapping of LXT381
• Banana jacks for power and line interfaces
• 10-pin connectors for framer/ASIC interface
• Socketed termination components for easy experimentation
• Built-in overvoltage protection for line interface and power supply

Developer Manual 5
LXD381 — Evaluation Board for Octal E1 Applications

Figure 1. LXD381 Evaluation Board

6 Developer Manual
 Evaluation Board for Octal E1 Applications — LXD381

2.0 Evaluation Board Set-Up

Caution: CMOS devices are static (ESD) sensitive. Take all industry standard precautions when handling the
evaluation board, the LXT381 chip and other sensitive electronic components.

Before proceeding with any evaluation board operations, review the specifications for the LXT381
transceiver.

2.1 LXD381 Packing List

The evaluation board kit contains the following components:
• LXD381 board with LXT381 device installed.
• LXD381 User Guide.
• LXT381 Data Sheet.

2.2 Equipment Requirements

The evaluation board kit includes all the circuit components needed for a successful evaluation.
However, the following lab equipment is required:
• Power Supply (+3.3 VDC).
• Telecom cable or cable simulator (optional).
• E1 pattern generator/analyzer

2.3 Power Connections

The evaluation board has two power planes (VCC and TVCC) each of which is tied to a separate
red colored banana jack. Connect the +3.3 VDC power supply to both the VCC (B1) and TVCC
(B3) banana jacks. Connect the power supply ground lead to the black banana jack (B2).

2.4 Loopback Mode Selection

The LXT381 LOOP signals for channels 0 through 7 are set by the switches in switch block S1. As
shown in Table 1, these switches have three positions to select Remote Loopback, Analog
Loopback or No Loopback.

Table 1. LOOP0 - 7 Switch Settings

S1 Switch Position Operation

High Analog Loopback

Center No Loopback
Low Remote Loopback

Developer Manual 7
LXD381 — Evaluation Board for Octal E1 Applications

2.5 Receive Polarity Selection

The polarity of RPOS/RNEG is determined by the CLKE switch in switch block S2. When the
CLKE switch is OFF, RPOS/RNEG are active Low. When set to the ON position, RPOS/RNEG
are active High. Note that the CLKE switch controls the LXT381’s RPOL pin.

2.6 Output Enable Selection

The OE switch in switch block S3 controls the operation of the LXT381 output drivers. For normal
operation (driver outputs enabled), set the OE switch to the ON position. Setting the OE switch to
OFF forces the output drivers to the high impedance state.

2.7 Unused Switches

Switches 3 and 4, in switch block S2, have no function on the LXD381 and should be set to the
OFF position. Figure 2 shows the factory default settings for switch block S2.
Figure 2. S2 Factory Switch Settings

S2
O
F
F

CLKE
1

OE
2
3
4

NOTE: OFF position = Low

2.8 Back-End Interface Connection

Eight 10 pin connectors (JP1 - JP8) provide access to the LXT381 digital signals to allow
interfacing the back-end Framer/Mapper or ASIC with an external pattern generator. Figure 3
shows a typical connector (JP1 for channel 0) with the factory installed jumper connecting RCLK
to TCLK. This jumper is normally installed when feeding analog test data from the line interface
(TIP and RING).

8 Developer Manual
 Evaluation Board for Octal E1 Applications — LXD381

Figure 3. Typical Back-End Connector

JP1

TCLK 0 1 2 GND

TCLK 0 3 4 RCLK 0

TPOS 0 5 6 RPOS 0

TNEG 0 7 8 RNEG 0

LOS 0 9 10 GND

2.9 Line Interface Connection

Access to the line interface is provided through the green and white banana jacks. The TIP signal is
routed to the white jacks for both transmit and receive directions. The RING signal is routed to the
green jacks for both directions.

2.10 Line Interface Circuit

Two octal transformers are used for channels 0 to 3 and 4 to 7. Transformers, resistors and
capacitors for channels 0 and 4 are socketed for easy swapping (see the LXT381 data sheet for line
interface information). Jumper blocks are provided to configure the receive transformer operation
for 1:1 or 1:2 turns ratio (see “Evaluation Board Schematics” on page 10). Factory installed
jumpers configure the transformers for a 1:1 ratio.

2.11 Board Protection

The evaluation board provides line surge protection for both the power supply and the line. Two
transient voltage suppressors (TVS) are included for power supply protection. The E1 line interface
transmitters are protected with Schottky diodes and the receivers are protected by series input
resistors. This protection is sufficient for G.703 Annex B compliance.

Developer Manual 9
10
3.0
VCC VCC

JA CONTROL
VCC
S2
1 8 CLKE
2 7 OE
3 6 RN2_8
4 5 RN2_9

SW DIP-4 C1 0.1uF
RN1
10 RN2
CM1 9 RN1_9 10 C2 0.1uF
R8 8 RN1_8 CM1 9
R7 7 RN1_7 R8 8
R6 6 RN1_6 R7 7 C3 0.1uF
R5 5 R6 6
CM2 4 RN1_4 R5 5
R4 3 RN1_3 CM2 4 C4 0.1uF
R3 2 RN1_2 R4 3
R2 1 RN1_1 R3 2 RN2_2
R1 R2 1 RN2_1
R1
R.NETWORK 4.7K VCC
R.NETWORK 4.7K

19
90
17
92
U1A
10
11 RPD 42
MODE LOS0 LOS0

VCC0
VCC1
CLKE 115 35
RN2_9 43 CLKE LOS1 75 LOS1

VCCIO0
VCCIO1
RN2_8 88 GND LOS2 68 LOS2
GND LOS3 113 LOS3
RN1_1 16 LOS4 106 LOS4
RN1_2 15 GND LOS5 3 LOS5
TVCC RN1_3 14 GND LOS6 140 LOS6
RN1_4 13 GND LOS7 LOS7
RN1_6 12 GND
GND
RN1_8 85
S3_9 87 GND
BN1
BANANA JACK OE 114 GND
TVCC 1 RN1_7 86 OE
RN1_9 84 GND
+ GND
LXD381 — Evaluation Board for Octal E1 Applications

C5 C6
RED 68 uF .01uf D1
BN2 VCC
GROUND TVS 5V 21
LOOP0/D0
Figure 4. Evaluation Board Schematic — Data/Control

1 22
R1 S3 23 LOOP1/D1 97 RN2_1
24 LOOP2/D2 GND
- 4.7K - LOOP3/D3
Evaluation Board Schematics

BLACK 25
18 1 26 LOOP4/D4
27 LOOP5/D5 94 RN2_2
28 LOOP6/D6 GND
2 LOOP7/D7
GND0
GNDIO0
GND1
GNDIO1

BOPx
20
18
89
91

3
VCC

BN3 5
BANANA JACK
3.3 VOLTS 1
+ 6

RED D2
C7 C8 7
TVS 3.3V
68 uF .01uf
8

10 9 S3_9

TriState9

Developer Manual
 JP1 JP2
1 2 1 2
TCLK0 3 4 RCLK0 TCLK4 3 4 RCLK4
TPOS0/TDATA0 5 6 RPOS0/RDATA0 TPOS4/TDATA4 5 6 RPOS4/RDATA4
TNEG0/UBS0 7 8 RNEG0/BPV0 TNEG4/UBS4 7 8 RNEG4/BPV4
LOS0 9 10 LOS4 9 10

Developer Manual
HEADER 5X2 HEADER 5X2
RN3 CHANNEL 0 CHANNEL 4
10
CM1 9 TCLK0
R8 8 TCLK1
R7 7 TCLK2
R6 6 TCLK3
R5 5
CM2 4 TCLK4
R4 3 TCLK5 JP3 JP4
R3 2 TCLK6
R2 1 TCLK7 1 2 1 2
R1 TCLK1 3 4 RCLK1 TCLK5 3 4 RCLK5
TPOS1/TDATA1 5 6 RPOS1/RDATA1 TPOS5/TDATA5 5 6 RPOS5/RDATA5
TNEG1/UBS1 7 8 RNEG1/BPV1 TNEG5/UBS5 7 8 RNEG5/BPV5
R.NETWORK 100K
LOS1 9 10 LOS5 9 10
RN4 HEADER 5X2 HEADER 5X2
CM1
10 CHANNEL 5
R8
9 TPOS0/TDATA0 CHANNEL 1
8 TPOS1/TDATA1
R7 7 TPOS2/TDATA2
R6 6 TPOS3/TDATA3
R5 5
CM2 4 TPOS4/TDATA4
R4 3 TPOS5/TDATA5
R3 2 TPOS6/TDATA6
R2 1 TPOS7/TDATA7 JP5 JP6
R1
1 2 1 2
TCLK2 3 4 RCLK2 TCLK6 3 4 RCLK6
R.NETWORK 100K RPOS2/RDATA2 TPOS6/TDATA6 RPOS6/RDATA6
TPOS2/TDATA2 5 6 5 6
Figure 5. Evaluation Board Schematic — Digital I/O

TNEG2/UBS2 7 8 RNEG2/BPV2 TNEG6/UBS6 7 8 RNEG6/BPV6

RN5
10 LOS2 9 10 LOS6 9 10
CM1 9 TNEG0/UBS0 HEADER 5X2 HEADER 5X2
R8 8 TNEG1/UBS1 CHANNEL 2 CHANNEL 6
R7 7 TNEG2/UBS2
R6 6 TNEG3/UBS3
R5 5
CM2 4 TNEG4/UBS4
R4 3 TNEG5/UBS5
R3 2 TNEG6/UBS6
R2 1 TNEG7/UBS7
R1

R.NETWORK 100K
JP7 JP8
1 2 1 2
TCLK3 3 4 RCLK3 TCLK7 3 4 RCLK7
TPOS3/TDATA3 5 6 RPOS3/RDATA3 TPOS7/TDATA7 5 6 RPOS7/RDATA7
TNEG3/UBS3 7 8 RNEG3/BPV3 TNEG7/UBS7 7 8 RNEG7/BPV7
LOS3 9 10 LOS7 9 10
HEADER 5X2 HEADER 5X2
CHANNEL 3
CHANNEL 7

11
Evaluation Board for Octal E1 Applications — LXD381
12
B1
B2 R2 RTIP2x 1 GREEN

2
R3 RTIP2
RTIP0x 1 GREEN

2
RTIP0 1K
1K R4 3 1
R5 3 1 C19
C20 60 T1C JP9
60 T1A B3
JP10
B4 R6 14 28 1 WHITE
0.22uF
R7 5 36 1 WHITE 27
0.22uF R8
37 RRING2 60 15 26 RRING2x
R9 60 4 38 RRING0x
RRING0 1K
TVCC 11 30 TTIP2x
1K
TVCC 3 39 TTIP0x 12 B5
2 B6 JP11 13 29 TRING2x 1 GREEN
JP12 1 40 TRING0x 1 GREEN D3
D4 C21 ?pF
C22 ?pF TG-49-1505-NX
TG-49-1505-NX TTIP2
11 B7
TTIP0
11 B8 D5 TVCC R10 1 WHITE
D6 TVCC R11 1 WHITE C23
C24
D7 560pF
D8 560pF
R12
R13 11
TRING2
11
TRING0 JP13
D9
D10

JP14

B9
B11 R14 RTIP3x 1 GREEN
2

R17 RTIP3
RTIP1x 1 GREEN

2
RTIP1 1K
LXD381 — Evaluation Board for Octal E1 Applications

R15 3 1
Figure 6. Evaluation Board Schematic — Analog 1

1K C25
R19 3 1
C26 60 T1D JP15
60 T1B B10
JP16
B13 R16 19 23 1 WHITE
0.22uF
R20 9 33 1 WHITE 22
0.22uF R18
32 RRING3 60 20 21 RRING3x
R21 60 10 31 RRING1x
RRING1 1K
TVCC 16 25 TTIP3x
1K
TVCC 6 35 TTIP1x 17 B12
7 B15 JP17 18 24 TRING3x 1 GREEN
JP18 8 34 TRING1x 1 GREEN D11
D13 C27 ?pF
C29 ?pF TG-49-1505-NX
TG-49-1505-NX TTIP3
11 B14
TTIP1
11 B16 D12 TVCC R22 1 WHITE
D15 TVCC R23 1 WHITE C28
C30
D14 560pF
D17 560pF
R24
R25 11
TRING3
11
TRING1 JP19
D16
D18

JP20

Developer Manual
 B17 B18
R26 RTIP4x 1 R27 RTIP6x 1

2
2
RTIP4 RTIP6
1K 1K

Developer Manual
R28 3 1 R29 3 1
C31 GREEN C32 GREEN
60 T2A B19 60 T2C B20
JP21 JP22
R30 5 36 1 R31 14 28 1
0.22uF 0.22uF
37 27
R32 60 4 38 RRING4x R33 60 15 26 RRING6x
RRING4 RRING6
1K WHITE 1K WHITE
TVCC 3 39 TTIP4x B21 TVCC 11 30 TTIP6x B22
2 12
JP23 1 40 TRING4x 1 JP24 13 29 TRING6x 1
D19 D20
C33 ?pF C34 ?pF
TG-49-1505-NX GREEN TG-49-1505-NX GREEN
TTIP4 B23 TTIP6 B24
11 11
D21 TVCC R34 1 D22 TVCC R35 1
C35 C36

D23 560pF WHITE D24 560pF WHITE

R36 R37
11 11
TRING4 TRING6
D25 JP25 D26 JP26

B25
B27
R38 RTIP7x 1
2

R41 RTIP7
RTIP5x 1

2
RTIP5 1K
Figure 7. Evaluation Board Schematic — Analog 2

1K R39 3 1
R43 3 1 C37 GREEN
C38 GREEN 60 T2D B26
JP27
60 T2B B29
JP28
R40 19 23 1
0.22uF
R44 9 33 1 22
0.22uF R42
32 60 20 21 RRING7x
R45 RRING7
RRING5 60 10 31 RRING5x WHITE
1K
WHITE TVCC 16 25 TTIP7x B28
1K
TVCC 6 35 TTIP5x B31 17
7 JP29 18 24 TRING7x 1
JP30 8 34 TRING5x 1 D27
D29 C39 ?pF
C41 ?pF TG-49-1505-NX GREEN
TG-49-1505-NX GREEN TTIP7 B30
B32 11
TTIP5 11 D28 TVCC R46 1
D31 TVCC R47 1 C40
C42
D30 560pF WHITE
D33 560pF WHITE
R48
R49 11
TRING7
11
TRING5 JP31
D32
D34 JP32

13
Evaluation Board for Octal E1 Applications — LXD381